arch/arm/kernel/perf_event.c

   1 #undef DEBUG
   2
   3 /*
   4  * ARM performance counter support.
   5  *
   6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
   8  *
   9  * This code is based on the sparc64 perf event code, which is in turn based
  10  * on the x86 code. Callchain code is based on the ARM OProfile backtrace
  11  * code.
  12  */
  13 #define pr_fmt(fmt) "hw perfevents: " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/uaccess.h>
  19
  20 #include <asm/irq_regs.h>
  21 #include <asm/pmu.h>
  22 #include <asm/stacktrace.h>
  23
  24 static int
  25 armpmu_map_cache_event(const unsigned (*cache_map)
  26                                       [PERF_COUNT_HW_CACHE_MAX]
  27                                       [PERF_COUNT_HW_CACHE_OP_MAX]
  28                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
  29                        u64 config)
  30 {
  31         unsigned int cache_type, cache_op, cache_result, ret;
  32
  33         cache_type = (config >>  0) & 0xff;
  34         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  35                 return -EINVAL;
  36
  37         cache_op = (config >>  8) & 0xff;
  38         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  39                 return -EINVAL;
  40
  41         cache_result = (config >> 16) & 0xff;
  42         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  43                 return -EINVAL;
  44
  45         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
  46
  47         if (ret == CACHE_OP_UNSUPPORTED)
  48                 return -ENOENT;
  49
  50         return ret;
  51 }
  52
  53 static int
  54 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
  55 {
  56         int mapping = (*event_map)[config];
  57         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
  58 }
  59
  60 static int
  61 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
  62 {
  63         return (int)(config & raw_event_mask);
  64 }
  65
  66 int
  67 armpmu_map_event(struct perf_event *event,
  68                  const unsigned (*event_map)[PERF_COUNT_HW_MAX],
  69                  const unsigned (*cache_map)
  70                                 [PERF_COUNT_HW_CACHE_MAX]
  71                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  72                                 [PERF_COUNT_HW_CACHE_RESULT_MAX],
  73                  u32 raw_event_mask)
  74 {
  75         u64 config = event->attr.config;
  76
  77         switch (event->attr.type) {
  78         case PERF_TYPE_HARDWARE:
  79                 return armpmu_map_hw_event(event_map, config);
  80         case PERF_TYPE_HW_CACHE:
  81                 return armpmu_map_cache_event(cache_map, config);
  82         case PERF_TYPE_RAW:
  83                 return armpmu_map_raw_event(raw_event_mask, config);
  84         }
  85
  86         return -ENOENT;
  87 }
  88
  89 int
  90 armpmu_event_set_period(struct perf_event *event,
  91                         struct hw_perf_event *hwc,
  92                         int idx)
  93 {
  94         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  95         s64 left = local64_read(&hwc->period_left);
  96         s64 period = hwc->sample_period;
  97         int ret = 0;
  98
  99         if (unlikely(left <= -period)) {
 100                 left = period;
 101                 local64_set(&hwc->period_left, left);
 102                 hwc->last_period = period;
 103                 ret = 1;
 104         }
 105
 106         if (unlikely(left <= 0)) {
 107                 left += period;
 108                 local64_set(&hwc->period_left, left);
 109                 hwc->last_period = period;
 110                 ret = 1;
 111         }
 112
 113         if (left > (s64)armpmu->max_period)
 114                 left = armpmu->max_period;
 115
 116         local64_set(&hwc->prev_count, (u64)-left);
 117
 118         armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
 119
 120         perf_event_update_userpage(event);
 121
 122         return ret;
 123 }
 124
 125 u64
 126 armpmu_event_update(struct perf_event *event,
 127                     struct hw_perf_event *hwc,
 128                     int idx)
 129 {
 130         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 131         u64 delta, prev_raw_count, new_raw_count;
 132
 133 again:
 134         prev_raw_count = local64_read(&hwc->prev_count);
 135         new_raw_count = armpmu->read_counter(idx);
 136
 137         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 138                              new_raw_count) != prev_raw_count)
 139                 goto again;
 140
 141         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
 142
 143         local64_add(delta, &event->count);
 144         local64_sub(delta, &hwc->period_left);
 145
 146         return new_raw_count;
 147 }
 148
 149 static void
 150 armpmu_read(struct perf_event *event)
 151 {
 152         struct hw_perf_event *hwc = &event->hw;
 153
 154         /* Don't read disabled counters! */
 155         if (hwc->idx < 0)
 156                 return;
 157
 158         armpmu_event_update(event, hwc, hwc->idx);
 159 }
 160
 161 static void
 162 armpmu_stop(struct perf_event *event, int flags)
 163 {
 164         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 165         struct hw_perf_event *hwc = &event->hw;
 166
 167         /*
 168          * ARM pmu always has to update the counter, so ignore
 169          * PERF_EF_UPDATE, see comments in armpmu_start().
 170          */
 171         if (!(hwc->state & PERF_HES_STOPPED)) {
 172                 armpmu->disable(hwc, hwc->idx);
 173                 armpmu_event_update(event, hwc, hwc->idx);
 174                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 175         }
 176 }
 177
 178 static void
 179 armpmu_start(struct perf_event *event, int flags)
 180 {
 181         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 182         struct hw_perf_event *hwc = &event->hw;
 183
 184         /*
 185          * ARM pmu always has to reprogram the period, so ignore
 186          * PERF_EF_RELOAD, see the comment below.
 187          */
 188         if (flags & PERF_EF_RELOAD)
 189                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 190
 191         hwc->state = 0;
 192         /*
 193          * Set the period again. Some counters can't be stopped, so when we
 194          * were stopped we simply disabled the IRQ source and the counter
 195          * may have been left counting. If we don't do this step then we may
 196          * get an interrupt too soon or *way* too late if the overflow has
 197          * happened since disabling.
 198          */
 199         armpmu_event_set_period(event, hwc, hwc->idx);
 200         armpmu->enable(hwc, hwc->idx);
 201 }
 202
 203 static void
 204 armpmu_del(struct perf_event *event, int flags)
 205 {
 206         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 207         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 208         struct hw_perf_event *hwc = &event->hw;
 209         int idx = hwc->idx;
 210
 211         WARN_ON(idx < 0);
 212
 213         armpmu_stop(event, PERF_EF_UPDATE);
 214         hw_events->events[idx] = NULL;
 215         clear_bit(idx, hw_events->used_mask);
 216
 217         perf_event_update_userpage(event);
 218 }
 219
 220 static int
 221 armpmu_add(struct perf_event *event, int flags)
 222 {
 223         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 224         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 225         struct hw_perf_event *hwc = &event->hw;
 226         int idx;
 227         int err = 0;
 228
 229         perf_pmu_disable(event->pmu);
 230
 231         /* If we don't have a space for the counter then finish early. */
 232         idx = armpmu->get_event_idx(hw_events, hwc);
 233         if (idx < 0) {
 234                 err = idx;
 235                 goto out;
 236         }
 237
 238         /*
 239          * If there is an event in the counter we are going to use then make
 240          * sure it is disabled.
 241          */
 242         event->hw.idx = idx;
 243         armpmu->disable(hwc, idx);
 244         hw_events->events[idx] = event;
 245
 246         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 247         if (flags & PERF_EF_START)
 248                 armpmu_start(event, PERF_EF_RELOAD);
 249
 250         /* Propagate our changes to the userspace mapping. */
 251         perf_event_update_userpage(event);
 252
 253 out:
 254         perf_pmu_enable(event->pmu);
 255         return err;
 256 }
 257
 258 static int
 259 validate_event(struct pmu_hw_events *hw_events,
 260                struct perf_event *event)
 261 {
 262         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 263         struct hw_perf_event fake_event = event->hw;
 264         struct pmu *leader_pmu = event->group_leader->pmu;
 265
 266         if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
 267                 return 1;
 268
 269         return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
 270 }
 271
 272 static int
 273 validate_group(struct perf_event *event)
 274 {
 275         struct perf_event *sibling, *leader = event->group_leader;
 276         struct pmu_hw_events fake_pmu;
 277         DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
 278
 279         /*
 280          * Initialise the fake PMU. We only need to populate the
 281          * used_mask for the purposes of validation.
 282          */
 283         memset(fake_used_mask, 0, sizeof(fake_used_mask));
 284         fake_pmu.used_mask = fake_used_mask;
 285
 286         if (!validate_event(&fake_pmu, leader))
 287                 return -EINVAL;
 288
 289         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 290                 if (!validate_event(&fake_pmu, sibling))
 291                         return -EINVAL;
 292         }
 293
 294         if (!validate_event(&fake_pmu, event))
 295                 return -EINVAL;
 296
 297         return 0;
 298 }
 299
 300 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 301 {
 302         struct arm_pmu *armpmu = (struct arm_pmu *) dev;
 303         struct platform_device *plat_device = armpmu->plat_device;
 304         struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
 305
 306         if (plat && plat->handle_irq)
 307                 return plat->handle_irq(irq, dev, armpmu->handle_irq);
 308         else
 309                 return armpmu->handle_irq(irq, dev);
 310 }
 311
 312 static void
 313 armpmu_release_hardware(struct arm_pmu *armpmu)
 314 {
 315         armpmu->free_irq();
 316         pm_runtime_put_sync(&armpmu->plat_device->dev);
 317 }
 318
 319 static int
 320 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 321 {
 322         int err;
 323         struct platform_device *pmu_device = armpmu->plat_device;
 324
 325         if (!pmu_device)
 326                 return -ENODEV;
 327
 328         pm_runtime_get_sync(&pmu_device->dev);
 329         err = armpmu->request_irq(armpmu_dispatch_irq);
 330         if (err) {
 331                 armpmu_release_hardware(armpmu);
 332                 return err;
 333         }
 334
 335         return 0;
 336 }
 337
 338 static void
 339 hw_perf_event_destroy(struct perf_event *event)
 340 {
 341         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 342         atomic_t *active_events  = &armpmu->active_events;
 343         struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
 344
 345         if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
 346                 armpmu_release_hardware(armpmu);
 347                 mutex_unlock(pmu_reserve_mutex);
 348         }
 349 }
 350
 351 static int
 352 event_requires_mode_exclusion(struct perf_event_attr *attr)
 353 {
 354         return attr->exclude_idle || attr->exclude_user ||
 355                attr->exclude_kernel || attr->exclude_hv;
 356 }
 357
 358 static int
 359 __hw_perf_event_init(struct perf_event *event)
 360 {
 361         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 362         struct hw_perf_event *hwc = &event->hw;
 363         int mapping, err;
 364
 365         mapping = armpmu->map_event(event);
 366
 367         if (mapping < 0) {
 368                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 369                          event->attr.config);
 370                 return mapping;
 371         }
 372
 373         /*
 374          * We don't assign an index until we actually place the event onto
 375          * hardware. Use -1 to signify that we haven't decided where to put it
 376          * yet. For SMP systems, each core has it's own PMU so we can't do any
 377          * clever allocation or constraints checking at this point.
 378          */
 379         hwc->idx                = -1;
 380         hwc->config_base        = 0;
 381         hwc->config             = 0;
 382         hwc->event_base         = 0;
 383
 384         /*
 385          * Check whether we need to exclude the counter from certain modes.
 386          */
 387         if ((!armpmu->set_event_filter ||
 388              armpmu->set_event_filter(hwc, &event->attr)) &&
 389              event_requires_mode_exclusion(&event->attr)) {
 390                 pr_debug("ARM performance counters do not support "
 391                          "mode exclusion\n");
 392                 return -EOPNOTSUPP;
 393         }
 394
 395         /*
 396          * Store the event encoding into the config_base field.
 397          */
 398         hwc->config_base            |= (unsigned long)mapping;
 399
 400         if (!hwc->sample_period) {
 401                 /*
 402                  * For non-sampling runs, limit the sample_period to half
 403                  * of the counter width. That way, the new counter value
 404                  * is far less likely to overtake the previous one unless
 405                  * you have some serious IRQ latency issues.
 406                  */
 407                 hwc->sample_period  = armpmu->max_period >> 1;
 408                 hwc->last_period    = hwc->sample_period;
 409                 local64_set(&hwc->period_left, hwc->sample_period);
 410         }
 411
 412         err = 0;
 413         if (event->group_leader != event) {
 414                 err = validate_group(event);
 415                 if (err)
 416                         return -EINVAL;
 417         }
 418
 419         return err;
 420 }
 421
 422 static int armpmu_event_init(struct perf_event *event)
 423 {
 424         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 425         int err = 0;
 426         atomic_t *active_events = &armpmu->active_events;
 427
 428         /* does not support taken branch sampling */
 429         if (has_branch_stack(event))
 430                 return -EOPNOTSUPP;
 431
 432         if (armpmu->map_event(event) == -ENOENT)
 433                 return -ENOENT;
 434
 435         event->destroy = hw_perf_event_destroy;
 436
 437         if (!atomic_inc_not_zero(active_events)) {
 438                 mutex_lock(&armpmu->reserve_mutex);
 439                 if (atomic_read(active_events) == 0)
 440                         err = armpmu_reserve_hardware(armpmu);
 441
 442                 if (!err)
 443                         atomic_inc(active_events);
 444                 mutex_unlock(&armpmu->reserve_mutex);
 445         }
 446
 447         if (err)
 448                 return err;
 449
 450         err = __hw_perf_event_init(event);
 451         if (err)
 452                 hw_perf_event_destroy(event);
 453
 454         return err;
 455 }
 456
 457 static void armpmu_enable(struct pmu *pmu)
 458 {
 459         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 460         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 461         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 462
 463         if (enabled)
 464                 armpmu->start();
 465 }
 466
 467 static void armpmu_disable(struct pmu *pmu)
 468 {
 469         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 470         armpmu->stop();
 471 }
 472
 473 #ifdef CONFIG_PM_RUNTIME
 474 static int armpmu_runtime_resume(struct device *dev)
 475 {
 476         struct arm_pmu_platdata *plat = dev_get_platdata(dev);
 477
 478         if (plat && plat->runtime_resume)
 479                 return plat->runtime_resume(dev);
 480
 481         return 0;
 482 }
 483
 484 static int armpmu_runtime_suspend(struct device *dev)
 485 {
 486         struct arm_pmu_platdata *plat = dev_get_platdata(dev);
 487
 488         if (plat && plat->runtime_suspend)
 489                 return plat->runtime_suspend(dev);
 490
 491         return 0;
 492 }
 493 #endif
 494
 495 const struct dev_pm_ops armpmu_dev_pm_ops = {
 496         SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
 497 };
 498
 499 static void __init armpmu_init(struct arm_pmu *armpmu)
 500 {
 501         atomic_set(&armpmu->active_events, 0);
 502         mutex_init(&armpmu->reserve_mutex);
 503
 504         armpmu->pmu = (struct pmu) {
 505                 .pmu_enable     = armpmu_enable,
 506                 .pmu_disable    = armpmu_disable,
 507                 .event_init     = armpmu_event_init,
 508                 .add            = armpmu_add,
 509                 .del            = armpmu_del,
 510                 .start          = armpmu_start,
 511                 .stop           = armpmu_stop,
 512                 .read           = armpmu_read,
 513         };
 514 }
 515
 516 int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
 517 {
 518         armpmu_init(armpmu);
 519         pr_info("enabled with %s PMU driver, %d counters available\n",
 520                         armpmu->name, armpmu->num_events);
 521         return perf_pmu_register(&armpmu->pmu, name, type);
 522 }
 523
 524 /*
 525  * Callchain handling code.
 526  */
 527
 528 /*
 529  * The registers we're interested in are at the end of the variable
 530  * length saved register structure. The fp points at the end of this
 531  * structure so the address of this struct is:
 532  * (struct frame_tail *)(xxx->fp)-1
 533  *
 534  * This code has been adapted from the ARM OProfile support.
 535  */
 536 struct frame_tail {
 537         struct frame_tail __user *fp;
 538         unsigned long sp;
 539         unsigned long lr;
 540 } __attribute__((packed));
 541
 542 /*
 543  * Get the return address for a single stackframe and return a pointer to the
 544  * next frame tail.
 545  */
 546 static struct frame_tail __user *
 547 user_backtrace(struct frame_tail __user *tail,
 548                struct perf_callchain_entry *entry)
 549 {
 550         struct frame_tail buftail;
 551
 552         /* Also check accessibility of one struct frame_tail beyond */
 553         if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
 554                 return NULL;
 555         if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
 556                 return NULL;
 557
 558         perf_callchain_store(entry, buftail.lr);
 559
 560         /*
 561          * Frame pointers should strictly progress back up the stack
 562          * (towards higher addresses).
 563          */
 564         if (tail + 1 >= buftail.fp)
 565                 return NULL;
 566
 567         return buftail.fp - 1;
 568 }
 569
 570 void
 571 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 572 {
 573         struct frame_tail __user *tail;
 574
 575
 576         tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 577
 578         while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
 579                tail && !((unsigned long)tail & 0x3))
 580                 tail = user_backtrace(tail, entry);
 581 }
 582
 583 /*
 584  * Gets called by walk_stackframe() for every stackframe. This will be called
 585  * whist unwinding the stackframe and is like a subroutine return so we use
 586  * the PC.
 587  */
 588 static int
 589 callchain_trace(struct stackframe *fr,
 590                 void *data)
 591 {
 592         struct perf_callchain_entry *entry = data;
 593         perf_callchain_store(entry, fr->pc);
 594         return 0;
 595 }
 596
 597 void
 598 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 599 {
 600         struct stackframe fr;
 601
 602         fr.fp = regs->ARM_fp;
 603         fr.sp = regs->ARM_sp;
 604         fr.lr = regs->ARM_lr;
 605         fr.pc = regs->ARM_pc;
 606         walk_stackframe(&fr, callchain_trace, entry);
 607 }