arch/arm/kernel/perf_event.c

   1 #undef DEBUG
   2
   3 /*
   4  * ARM performance counter support.
   5  *
   6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
   8  *
   9  * This code is based on the sparc64 perf event code, which is in turn based
  10  * on the x86 code. Callchain code is based on the ARM OProfile backtrace
  11  * code.
  12  */
  13 #define pr_fmt(fmt) "hw perfevents: " fmt
  14
  15 #include <linux/bitmap.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/kernel.h>
  18 #include <linux/export.h>
  19 #include <linux/perf_event.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/uaccess.h>
  23
  24 #include <asm/cputype.h>
  25 #include <asm/irq.h>
  26 #include <asm/irq_regs.h>
  27 #include <asm/pmu.h>
  28 #include <asm/stacktrace.h>
  29
  30 /*
  31  * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
  32  * another platform that supports more, we need to increase this to be the
  33  * largest of all platforms.
  34  *
  35  * ARMv7 supports up to 32 events:
  36  *  cycle counter CCNT + 31 events counters CNT0..30.
  37  *  Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
  38  */
  39 #define ARMPMU_MAX_HWEVENTS             32
  40
  41 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
  42 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
  43 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
  44
  45 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
  46
  47 /* Set at runtime when we know what CPU type we are. */
  48 static struct arm_pmu *cpu_pmu;
  49
  50 enum arm_perf_pmu_ids
  51 armpmu_get_pmu_id(void)
  52 {
  53         int id = -ENODEV;
  54
  55         if (cpu_pmu != NULL)
  56                 id = cpu_pmu->id;
  57
  58         return id;
  59 }
  60 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
  61
  62 int perf_num_counters(void)
  63 {
  64         int max_events = 0;
  65
  66         if (cpu_pmu != NULL)
  67                 max_events = cpu_pmu->num_events;
  68
  69         return max_events;
  70 }
  71 EXPORT_SYMBOL_GPL(perf_num_counters);
  72
  73 #define HW_OP_UNSUPPORTED               0xFFFF
  74
  75 #define C(_x) \
  76         PERF_COUNT_HW_CACHE_##_x
  77
  78 #define CACHE_OP_UNSUPPORTED            0xFFFF
  79
  80 static int
  81 armpmu_map_cache_event(const unsigned (*cache_map)
  82                                       [PERF_COUNT_HW_CACHE_MAX]
  83                                       [PERF_COUNT_HW_CACHE_OP_MAX]
  84                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
  85                        u64 config)
  86 {
  87         unsigned int cache_type, cache_op, cache_result, ret;
  88
  89         cache_type = (config >>  0) & 0xff;
  90         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  91                 return -EINVAL;
  92
  93         cache_op = (config >>  8) & 0xff;
  94         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  95                 return -EINVAL;
  96
  97         cache_result = (config >> 16) & 0xff;
  98         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  99                 return -EINVAL;
 100
 101         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
 102
 103         if (ret == CACHE_OP_UNSUPPORTED)
 104                 return -ENOENT;
 105
 106         return ret;
 107 }
 108
 109 static int
 110 armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
 111 {
 112         int mapping = (*event_map)[config];
 113         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
 114 }
 115
 116 static int
 117 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
 118 {
 119         return (int)(config & raw_event_mask);
 120 }
 121
 122 static int map_cpu_event(struct perf_event *event,
 123                          const unsigned (*event_map)[PERF_COUNT_HW_MAX],
 124                          const unsigned (*cache_map)
 125                                         [PERF_COUNT_HW_CACHE_MAX]
 126                                         [PERF_COUNT_HW_CACHE_OP_MAX]
 127                                         [PERF_COUNT_HW_CACHE_RESULT_MAX],
 128                          u32 raw_event_mask)
 129 {
 130         u64 config = event->attr.config;
 131
 132         switch (event->attr.type) {
 133         case PERF_TYPE_HARDWARE:
 134                 return armpmu_map_event(event_map, config);
 135         case PERF_TYPE_HW_CACHE:
 136                 return armpmu_map_cache_event(cache_map, config);
 137         case PERF_TYPE_RAW:
 138                 return armpmu_map_raw_event(raw_event_mask, config);
 139         }
 140
 141         return -ENOENT;
 142 }
 143
 144 int
 145 armpmu_event_set_period(struct perf_event *event,
 146                         struct hw_perf_event *hwc,
 147                         int idx)
 148 {
 149         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 150         s64 left = local64_read(&hwc->period_left);
 151         s64 period = hwc->sample_period;
 152         int ret = 0;
 153
 154         if (unlikely(left <= -period)) {
 155                 left = period;
 156                 local64_set(&hwc->period_left, left);
 157                 hwc->last_period = period;
 158                 ret = 1;
 159         }
 160
 161         if (unlikely(left <= 0)) {
 162                 left += period;
 163                 local64_set(&hwc->period_left, left);
 164                 hwc->last_period = period;
 165                 ret = 1;
 166         }
 167
 168         if (left > (s64)armpmu->max_period)
 169                 left = armpmu->max_period;
 170
 171         local64_set(&hwc->prev_count, (u64)-left);
 172
 173         armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
 174
 175         perf_event_update_userpage(event);
 176
 177         return ret;
 178 }
 179
 180 u64
 181 armpmu_event_update(struct perf_event *event,
 182                     struct hw_perf_event *hwc,
 183                     int idx)
 184 {
 185         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 186         u64 delta, prev_raw_count, new_raw_count;
 187
 188 again:
 189         prev_raw_count = local64_read(&hwc->prev_count);
 190         new_raw_count = armpmu->read_counter(idx);
 191
 192         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 193                              new_raw_count) != prev_raw_count)
 194                 goto again;
 195
 196         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
 197
 198         local64_add(delta, &event->count);
 199         local64_sub(delta, &hwc->period_left);
 200
 201         return new_raw_count;
 202 }
 203
 204 static void
 205 armpmu_read(struct perf_event *event)
 206 {
 207         struct hw_perf_event *hwc = &event->hw;
 208
 209         /* Don't read disabled counters! */
 210         if (hwc->idx < 0)
 211                 return;
 212
 213         armpmu_event_update(event, hwc, hwc->idx);
 214 }
 215
 216 static void
 217 armpmu_stop(struct perf_event *event, int flags)
 218 {
 219         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 220         struct hw_perf_event *hwc = &event->hw;
 221
 222         /*
 223          * ARM pmu always has to update the counter, so ignore
 224          * PERF_EF_UPDATE, see comments in armpmu_start().
 225          */
 226         if (!(hwc->state & PERF_HES_STOPPED)) {
 227                 armpmu->disable(hwc, hwc->idx);
 228                 barrier(); /* why? */
 229                 armpmu_event_update(event, hwc, hwc->idx);
 230                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 231         }
 232 }
 233
 234 static void
 235 armpmu_start(struct perf_event *event, int flags)
 236 {
 237         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 238         struct hw_perf_event *hwc = &event->hw;
 239
 240         /*
 241          * ARM pmu always has to reprogram the period, so ignore
 242          * PERF_EF_RELOAD, see the comment below.
 243          */
 244         if (flags & PERF_EF_RELOAD)
 245                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 246
 247         hwc->state = 0;
 248         /*
 249          * Set the period again. Some counters can't be stopped, so when we
 250          * were stopped we simply disabled the IRQ source and the counter
 251          * may have been left counting. If we don't do this step then we may
 252          * get an interrupt too soon or *way* too late if the overflow has
 253          * happened since disabling.
 254          */
 255         armpmu_event_set_period(event, hwc, hwc->idx);
 256         armpmu->enable(hwc, hwc->idx);
 257 }
 258
 259 static void
 260 armpmu_del(struct perf_event *event, int flags)
 261 {
 262         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 263         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 264         struct hw_perf_event *hwc = &event->hw;
 265         int idx = hwc->idx;
 266
 267         WARN_ON(idx < 0);
 268
 269         armpmu_stop(event, PERF_EF_UPDATE);
 270         hw_events->events[idx] = NULL;
 271         clear_bit(idx, hw_events->used_mask);
 272
 273         perf_event_update_userpage(event);
 274 }
 275
 276 static int
 277 armpmu_add(struct perf_event *event, int flags)
 278 {
 279         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 280         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 281         struct hw_perf_event *hwc = &event->hw;
 282         int idx;
 283         int err = 0;
 284
 285         perf_pmu_disable(event->pmu);
 286
 287         /* If we don't have a space for the counter then finish early. */
 288         idx = armpmu->get_event_idx(hw_events, hwc);
 289         if (idx < 0) {
 290                 err = idx;
 291                 goto out;
 292         }
 293
 294         /*
 295          * If there is an event in the counter we are going to use then make
 296          * sure it is disabled.
 297          */
 298         event->hw.idx = idx;
 299         armpmu->disable(hwc, idx);
 300         hw_events->events[idx] = event;
 301
 302         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 303         if (flags & PERF_EF_START)
 304                 armpmu_start(event, PERF_EF_RELOAD);
 305
 306         /* Propagate our changes to the userspace mapping. */
 307         perf_event_update_userpage(event);
 308
 309 out:
 310         perf_pmu_enable(event->pmu);
 311         return err;
 312 }
 313
 314 static int
 315 validate_event(struct pmu_hw_events *hw_events,
 316                struct perf_event *event)
 317 {
 318         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 319         struct hw_perf_event fake_event = event->hw;
 320         struct pmu *leader_pmu = event->group_leader->pmu;
 321
 322         if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
 323                 return 1;
 324
 325         return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
 326 }
 327
 328 static int
 329 validate_group(struct perf_event *event)
 330 {
 331         struct perf_event *sibling, *leader = event->group_leader;
 332         struct pmu_hw_events fake_pmu;
 333         DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
 334
 335         /*
 336          * Initialise the fake PMU. We only need to populate the
 337          * used_mask for the purposes of validation.
 338          */
 339         memset(fake_used_mask, 0, sizeof(fake_used_mask));
 340         fake_pmu.used_mask = fake_used_mask;
 341
 342         if (!validate_event(&fake_pmu, leader))
 343                 return -EINVAL;
 344
 345         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 346                 if (!validate_event(&fake_pmu, sibling))
 347                         return -EINVAL;
 348         }
 349
 350         if (!validate_event(&fake_pmu, event))
 351                 return -EINVAL;
 352
 353         return 0;
 354 }
 355
 356 static irqreturn_t armpmu_platform_irq(int irq, void *dev)
 357 {
 358         struct arm_pmu *armpmu = (struct arm_pmu *) dev;
 359         struct platform_device *plat_device = armpmu->plat_device;
 360         struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
 361
 362         return plat->handle_irq(irq, dev, armpmu->handle_irq);
 363 }
 364
 365 static void
 366 armpmu_release_hardware(struct arm_pmu *armpmu)
 367 {
 368         int i, irq, irqs;
 369         struct platform_device *pmu_device = armpmu->plat_device;
 370         struct arm_pmu_platdata *plat =
 371                 dev_get_platdata(&pmu_device->dev);
 372
 373         irqs = min(pmu_device->num_resources, num_possible_cpus());
 374
 375         for (i = 0; i < irqs; ++i) {
 376                 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
 377                         continue;
 378                 irq = platform_get_irq(pmu_device, i);
 379                 if (irq >= 0) {
 380                         if (plat && plat->disable_irq)
 381                                 plat->disable_irq(irq);
 382                         free_irq(irq, armpmu);
 383                 }
 384         }
 385
 386         release_pmu(armpmu->type);
 387 }
 388
 389 static int
 390 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 391 {
 392         struct arm_pmu_platdata *plat;
 393         irq_handler_t handle_irq;
 394         int i, err, irq, irqs;
 395         struct platform_device *pmu_device = armpmu->plat_device;
 396
 397         if (!pmu_device)
 398                 return -ENODEV;
 399
 400         err = reserve_pmu(armpmu->type);
 401         if (err) {
 402                 pr_warning("unable to reserve pmu\n");
 403                 return err;
 404         }
 405
 406         plat = dev_get_platdata(&pmu_device->dev);
 407         if (plat && plat->handle_irq)
 408                 handle_irq = armpmu_platform_irq;
 409         else
 410                 handle_irq = armpmu->handle_irq;
 411
 412         irqs = min(pmu_device->num_resources, num_possible_cpus());
 413         if (irqs < 1) {
 414                 pr_err("no irqs for PMUs defined\n");
 415                 return -ENODEV;
 416         }
 417
 418         for (i = 0; i < irqs; ++i) {
 419                 err = 0;
 420                 irq = platform_get_irq(pmu_device, i);
 421                 if (irq < 0)
 422                         continue;
 423
 424                 /*
 425                  * If we have a single PMU interrupt that we can't shift,
 426                  * assume that we're running on a uniprocessor machine and
 427                  * continue. Otherwise, continue without this interrupt.
 428                  */
 429                 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
 430                         pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
 431                                     irq, i);
 432                         continue;
 433                 }
 434
 435                 err = request_irq(irq, handle_irq,
 436                                   IRQF_DISABLED | IRQF_NOBALANCING,
 437                                   "arm-pmu", armpmu);
 438                 if (err) {
 439                         pr_err("unable to request IRQ%d for ARM PMU counters\n",
 440                                 irq);
 441                         armpmu_release_hardware(armpmu);
 442                         return err;
 443                 } else if (plat && plat->enable_irq)
 444                         plat->enable_irq(irq);
 445
 446                 cpumask_set_cpu(i, &armpmu->active_irqs);
 447         }
 448
 449         return 0;
 450 }
 451
 452 static void
 453 hw_perf_event_destroy(struct perf_event *event)
 454 {
 455         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 456         atomic_t *active_events  = &armpmu->active_events;
 457         struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
 458
 459         if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
 460                 armpmu_release_hardware(armpmu);
 461                 mutex_unlock(pmu_reserve_mutex);
 462         }
 463 }
 464
 465 static int
 466 event_requires_mode_exclusion(struct perf_event_attr *attr)
 467 {
 468         return attr->exclude_idle || attr->exclude_user ||
 469                attr->exclude_kernel || attr->exclude_hv;
 470 }
 471
 472 static int
 473 __hw_perf_event_init(struct perf_event *event)
 474 {
 475         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 476         struct hw_perf_event *hwc = &event->hw;
 477         int mapping, err;
 478
 479         mapping = armpmu->map_event(event);
 480
 481         if (mapping < 0) {
 482                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 483                          event->attr.config);
 484                 return mapping;
 485         }
 486
 487         /*
 488          * We don't assign an index until we actually place the event onto
 489          * hardware. Use -1 to signify that we haven't decided where to put it
 490          * yet. For SMP systems, each core has it's own PMU so we can't do any
 491          * clever allocation or constraints checking at this point.
 492          */
 493         hwc->idx                = -1;
 494         hwc->config_base        = 0;
 495         hwc->config             = 0;
 496         hwc->event_base         = 0;
 497
 498         /*
 499          * Check whether we need to exclude the counter from certain modes.
 500          */
 501         if ((!armpmu->set_event_filter ||
 502              armpmu->set_event_filter(hwc, &event->attr)) &&
 503              event_requires_mode_exclusion(&event->attr)) {
 504                 pr_debug("ARM performance counters do not support "
 505                          "mode exclusion\n");
 506                 return -EPERM;
 507         }
 508
 509         /*
 510          * Store the event encoding into the config_base field.
 511          */
 512         hwc->config_base            |= (unsigned long)mapping;
 513
 514         if (!hwc->sample_period) {
 515                 /*
 516                  * For non-sampling runs, limit the sample_period to half
 517                  * of the counter width. That way, the new counter value
 518                  * is far less likely to overtake the previous one unless
 519                  * you have some serious IRQ latency issues.
 520                  */
 521                 hwc->sample_period  = armpmu->max_period >> 1;
 522                 hwc->last_period    = hwc->sample_period;
 523                 local64_set(&hwc->period_left, hwc->sample_period);
 524         }
 525
 526         err = 0;
 527         if (event->group_leader != event) {
 528                 err = validate_group(event);
 529                 if (err)
 530                         return -EINVAL;
 531         }
 532
 533         return err;
 534 }
 535
 536 static int armpmu_event_init(struct perf_event *event)
 537 {
 538         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 539         int err = 0;
 540         atomic_t *active_events = &armpmu->active_events;
 541
 542         if (armpmu->map_event(event) == -ENOENT)
 543                 return -ENOENT;
 544
 545         event->destroy = hw_perf_event_destroy;
 546
 547         if (!atomic_inc_not_zero(active_events)) {
 548                 mutex_lock(&armpmu->reserve_mutex);
 549                 if (atomic_read(active_events) == 0)
 550                         err = armpmu_reserve_hardware(armpmu);
 551
 552                 if (!err)
 553                         atomic_inc(active_events);
 554                 mutex_unlock(&armpmu->reserve_mutex);
 555         }
 556
 557         if (err)
 558                 return err;
 559
 560         err = __hw_perf_event_init(event);
 561         if (err)
 562                 hw_perf_event_destroy(event);
 563
 564         return err;
 565 }
 566
 567 static void armpmu_enable(struct pmu *pmu)
 568 {
 569         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 570         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 571         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 572
 573         if (enabled)
 574                 armpmu->start();
 575 }
 576
 577 static void armpmu_disable(struct pmu *pmu)
 578 {
 579         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 580         armpmu->stop();
 581 }
 582
 583 static void __init armpmu_init(struct arm_pmu *armpmu)
 584 {
 585         atomic_set(&armpmu->active_events, 0);
 586         mutex_init(&armpmu->reserve_mutex);
 587
 588         armpmu->pmu = (struct pmu) {
 589                 .pmu_enable     = armpmu_enable,
 590                 .pmu_disable    = armpmu_disable,
 591                 .event_init     = armpmu_event_init,
 592                 .add            = armpmu_add,
 593                 .del            = armpmu_del,
 594                 .start          = armpmu_start,
 595                 .stop           = armpmu_stop,
 596                 .read           = armpmu_read,
 597         };
 598 }
 599
 600 int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
 601 {
 602         armpmu_init(armpmu);
 603         return perf_pmu_register(&armpmu->pmu, name, type);
 604 }
 605
 606 /* Include the PMU-specific implementations. */
 607 #include "perf_event_xscale.c"
 608 #include "perf_event_v6.c"
 609 #include "perf_event_v7.c"
 610
 611 /*
 612  * Ensure the PMU has sane values out of reset.
 613  * This requires SMP to be available, so exists as a separate initcall.
 614  */
 615 static int __init
 616 cpu_pmu_reset(void)
 617 {
 618         if (cpu_pmu && cpu_pmu->reset)
 619                 return on_each_cpu(cpu_pmu->reset, NULL, 1);
 620         return 0;
 621 }
 622 arch_initcall(cpu_pmu_reset);
 623
 624 /*
 625  * PMU platform driver and devicetree bindings.
 626  */
 627 static struct of_device_id armpmu_of_device_ids[] = {
 628         {.compatible = "arm,cortex-a9-pmu"},
 629         {.compatible = "arm,cortex-a8-pmu"},
 630         {.compatible = "arm,arm1136-pmu"},
 631         {.compatible = "arm,arm1176-pmu"},
 632         {},
 633 };
 634
 635 static struct platform_device_id armpmu_plat_device_ids[] = {
 636         {.name = "arm-pmu"},
 637         {},
 638 };
 639
 640 static int __devinit armpmu_device_probe(struct platform_device *pdev)
 641 {
 642         if (!cpu_pmu)
 643                 return -ENODEV;
 644
 645         cpu_pmu->plat_device = pdev;
 646         return 0;
 647 }
 648
 649 static struct platform_driver armpmu_driver = {
 650         .driver         = {
 651                 .name   = "arm-pmu",
 652                 .of_match_table = armpmu_of_device_ids,
 653         },
 654         .probe          = armpmu_device_probe,
 655         .id_table       = armpmu_plat_device_ids,
 656 };
 657
 658 static int __init register_pmu_driver(void)
 659 {
 660         return platform_driver_register(&armpmu_driver);
 661 }
 662 device_initcall(register_pmu_driver);
 663
 664 static struct pmu_hw_events *armpmu_get_cpu_events(void)
 665 {
 666         return &__get_cpu_var(cpu_hw_events);
 667 }
 668
 669 static void __init cpu_pmu_init(struct arm_pmu *armpmu)
 670 {
 671         int cpu;
 672         for_each_possible_cpu(cpu) {
 673                 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
 674                 events->events = per_cpu(hw_events, cpu);
 675                 events->used_mask = per_cpu(used_mask, cpu);
 676                 raw_spin_lock_init(&events->pmu_lock);
 677         }
 678         armpmu->get_hw_events = armpmu_get_cpu_events;
 679         armpmu->type = ARM_PMU_DEVICE_CPU;
 680 }
 681
 682 /*
 683  * PMU hardware loses all context when a CPU goes offline.
 684  * When a CPU is hotplugged back in, since some hardware registers are
 685  * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
 686  * junk values out of them.
 687  */
 688 static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
 689                                         unsigned long action, void *hcpu)
 690 {
 691         if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
 692                 return NOTIFY_DONE;
 693
 694         if (cpu_pmu && cpu_pmu->reset)
 695                 cpu_pmu->reset(NULL);
 696
 697         return NOTIFY_OK;
 698 }
 699
 700 static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
 701         .notifier_call = pmu_cpu_notify,
 702 };
 703
 704 /*
 705  * CPU PMU identification and registration.
 706  */
 707 static int __init
 708 init_hw_perf_events(void)
 709 {
 710         unsigned long cpuid = read_cpuid_id();
 711         unsigned long implementor = (cpuid & 0xFF000000) >> 24;
 712         unsigned long part_number = (cpuid & 0xFFF0);
 713
 714         /* ARM Ltd CPUs. */
 715         if (0x41 == implementor) {
 716                 switch (part_number) {
 717                 case 0xB360:    /* ARM1136 */
 718                 case 0xB560:    /* ARM1156 */
 719                 case 0xB760:    /* ARM1176 */
 720                         cpu_pmu = armv6pmu_init();
 721                         break;
 722                 case 0xB020:    /* ARM11mpcore */
 723                         cpu_pmu = armv6mpcore_pmu_init();
 724                         break;
 725                 case 0xC080:    /* Cortex-A8 */
 726                         cpu_pmu = armv7_a8_pmu_init();
 727                         break;
 728                 case 0xC090:    /* Cortex-A9 */
 729                         cpu_pmu = armv7_a9_pmu_init();
 730                         break;
 731                 case 0xC050:    /* Cortex-A5 */
 732                         cpu_pmu = armv7_a5_pmu_init();
 733                         break;
 734                 case 0xC0F0:    /* Cortex-A15 */
 735                         cpu_pmu = armv7_a15_pmu_init();
 736                         break;
 737                 }
 738         /* Intel CPUs [xscale]. */
 739         } else if (0x69 == implementor) {
 740                 part_number = (cpuid >> 13) & 0x7;
 741                 switch (part_number) {
 742                 case 1:
 743                         cpu_pmu = xscale1pmu_init();
 744                         break;
 745                 case 2:
 746                         cpu_pmu = xscale2pmu_init();
 747                         break;
 748                 }
 749         }
 750
 751         if (cpu_pmu) {
 752                 pr_info("enabled with %s PMU driver, %d counters available\n",
 753                         cpu_pmu->name, cpu_pmu->num_events);
 754                 cpu_pmu_init(cpu_pmu);
 755                 register_cpu_notifier(&pmu_cpu_notifier);
 756                 armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
 757         } else {
 758                 pr_info("no hardware support available\n");
 759         }
 760
 761         return 0;
 762 }
 763 early_initcall(init_hw_perf_events);
 764
 765 /*
 766  * Callchain handling code.
 767  */
 768
 769 /*
 770  * The registers we're interested in are at the end of the variable
 771  * length saved register structure. The fp points at the end of this
 772  * structure so the address of this struct is:
 773  * (struct frame_tail *)(xxx->fp)-1
 774  *
 775  * This code has been adapted from the ARM OProfile support.
 776  */
 777 struct frame_tail {
 778         struct frame_tail __user *fp;
 779         unsigned long sp;
 780         unsigned long lr;
 781 } __attribute__((packed));
 782
 783 /*
 784  * Get the return address for a single stackframe and return a pointer to the
 785  * next frame tail.
 786  */
 787 static struct frame_tail __user *
 788 user_backtrace(struct frame_tail __user *tail,
 789                struct perf_callchain_entry *entry)
 790 {
 791         struct frame_tail buftail;
 792
 793         /* Also check accessibility of one struct frame_tail beyond */
 794         if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
 795                 return NULL;
 796         if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
 797                 return NULL;
 798
 799         perf_callchain_store(entry, buftail.lr);
 800
 801         /*
 802          * Frame pointers should strictly progress back up the stack
 803          * (towards higher addresses).
 804          */
 805         if (tail + 1 >= buftail.fp)
 806                 return NULL;
 807
 808         return buftail.fp - 1;
 809 }
 810
 811 void
 812 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 813 {
 814         struct frame_tail __user *tail;
 815
 816
 817         tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 818
 819         while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
 820                tail && !((unsigned long)tail & 0x3))
 821                 tail = user_backtrace(tail, entry);
 822 }
 823
 824 /*
 825  * Gets called by walk_stackframe() for every stackframe. This will be called
 826  * whist unwinding the stackframe and is like a subroutine return so we use
 827  * the PC.
 828  */
 829 static int
 830 callchain_trace(struct stackframe *fr,
 831                 void *data)
 832 {
 833         struct perf_callchain_entry *entry = data;
 834         perf_callchain_store(entry, fr->pc);
 835         return 0;
 836 }
 837
 838 void
 839 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 840 {
 841         struct stackframe fr;
 842
 843         fr.fp = regs->ARM_fp;
 844         fr.sp = regs->ARM_sp;
 845         fr.lr = regs->ARM_lr;
 846         fr.pc = regs->ARM_pc;
 847         walk_stackframe(&fr, callchain_trace, entry);
 848 }