4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
13 #define pr_fmt(fmt) "hw perfevents: " fmt
15 #include <linux/bitmap.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/export.h>
19 #include <linux/perf_event.h>
20 #include <linux/platform_device.h>
21 #include <linux/spinlock.h>
22 #include <linux/uaccess.h>
24 #include <asm/cputype.h>
26 #include <asm/irq_regs.h>
28 #include <asm/stacktrace.h>
31 * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
32 * another platform that supports more, we need to increase this to be the
33 * largest of all platforms.
35 * ARMv7 supports up to 32 events:
36 * cycle counter CCNT + 31 events counters CNT0..30.
37 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
39 #define ARMPMU_MAX_HWEVENTS 32
41 static DEFINE_PER_CPU(struct perf_event
* [ARMPMU_MAX_HWEVENTS
], hw_events
);
42 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS
)], used_mask
);
43 static DEFINE_PER_CPU(struct pmu_hw_events
, cpu_hw_events
);
45 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
47 /* Set at runtime when we know what CPU type we are. */
48 static struct arm_pmu
*cpu_pmu
;
51 armpmu_get_pmu_id(void)
60 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id
);
62 int perf_num_counters(void)
67 max_events
= cpu_pmu
->num_events
;
71 EXPORT_SYMBOL_GPL(perf_num_counters
);
73 #define HW_OP_UNSUPPORTED 0xFFFF
76 PERF_COUNT_HW_CACHE_##_x
78 #define CACHE_OP_UNSUPPORTED 0xFFFF
81 armpmu_map_cache_event(const unsigned (*cache_map
)
82 [PERF_COUNT_HW_CACHE_MAX
]
83 [PERF_COUNT_HW_CACHE_OP_MAX
]
84 [PERF_COUNT_HW_CACHE_RESULT_MAX
],
87 unsigned int cache_type
, cache_op
, cache_result
, ret
;
89 cache_type
= (config
>> 0) & 0xff;
90 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
93 cache_op
= (config
>> 8) & 0xff;
94 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
97 cache_result
= (config
>> 16) & 0xff;
98 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
101 ret
= (int)(*cache_map
)[cache_type
][cache_op
][cache_result
];
103 if (ret
== CACHE_OP_UNSUPPORTED
)
110 armpmu_map_event(const unsigned (*event_map
)[PERF_COUNT_HW_MAX
], u64 config
)
112 int mapping
= (*event_map
)[config
];
113 return mapping
== HW_OP_UNSUPPORTED
? -ENOENT
: mapping
;
117 armpmu_map_raw_event(u32 raw_event_mask
, u64 config
)
119 return (int)(config
& raw_event_mask
);
122 static int map_cpu_event(struct perf_event
*event
,
123 const unsigned (*event_map
)[PERF_COUNT_HW_MAX
],
124 const unsigned (*cache_map
)
125 [PERF_COUNT_HW_CACHE_MAX
]
126 [PERF_COUNT_HW_CACHE_OP_MAX
]
127 [PERF_COUNT_HW_CACHE_RESULT_MAX
],
130 u64 config
= event
->attr
.config
;
132 switch (event
->attr
.type
) {
133 case PERF_TYPE_HARDWARE
:
134 return armpmu_map_event(event_map
, config
);
135 case PERF_TYPE_HW_CACHE
:
136 return armpmu_map_cache_event(cache_map
, config
);
138 return armpmu_map_raw_event(raw_event_mask
, config
);
145 armpmu_event_set_period(struct perf_event
*event
,
146 struct hw_perf_event
*hwc
,
149 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
150 s64 left
= local64_read(&hwc
->period_left
);
151 s64 period
= hwc
->sample_period
;
154 if (unlikely(left
<= -period
)) {
156 local64_set(&hwc
->period_left
, left
);
157 hwc
->last_period
= period
;
161 if (unlikely(left
<= 0)) {
163 local64_set(&hwc
->period_left
, left
);
164 hwc
->last_period
= period
;
168 if (left
> (s64
)armpmu
->max_period
)
169 left
= armpmu
->max_period
;
171 local64_set(&hwc
->prev_count
, (u64
)-left
);
173 armpmu
->write_counter(idx
, (u64
)(-left
) & 0xffffffff);
175 perf_event_update_userpage(event
);
181 armpmu_event_update(struct perf_event
*event
,
182 struct hw_perf_event
*hwc
,
183 int idx
, int overflow
)
185 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
186 u64 delta
, prev_raw_count
, new_raw_count
;
189 prev_raw_count
= local64_read(&hwc
->prev_count
);
190 new_raw_count
= armpmu
->read_counter(idx
);
192 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
193 new_raw_count
) != prev_raw_count
)
196 new_raw_count
&= armpmu
->max_period
;
197 prev_raw_count
&= armpmu
->max_period
;
200 delta
= armpmu
->max_period
- prev_raw_count
+ new_raw_count
+ 1;
202 delta
= new_raw_count
- prev_raw_count
;
204 local64_add(delta
, &event
->count
);
205 local64_sub(delta
, &hwc
->period_left
);
207 return new_raw_count
;
211 armpmu_read(struct perf_event
*event
)
213 struct hw_perf_event
*hwc
= &event
->hw
;
215 /* Don't read disabled counters! */
219 armpmu_event_update(event
, hwc
, hwc
->idx
, 0);
223 armpmu_stop(struct perf_event
*event
, int flags
)
225 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
226 struct hw_perf_event
*hwc
= &event
->hw
;
229 * ARM pmu always has to update the counter, so ignore
230 * PERF_EF_UPDATE, see comments in armpmu_start().
232 if (!(hwc
->state
& PERF_HES_STOPPED
)) {
233 armpmu
->disable(hwc
, hwc
->idx
);
234 barrier(); /* why? */
235 armpmu_event_update(event
, hwc
, hwc
->idx
, 0);
236 hwc
->state
|= PERF_HES_STOPPED
| PERF_HES_UPTODATE
;
241 armpmu_start(struct perf_event
*event
, int flags
)
243 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
244 struct hw_perf_event
*hwc
= &event
->hw
;
247 * ARM pmu always has to reprogram the period, so ignore
248 * PERF_EF_RELOAD, see the comment below.
250 if (flags
& PERF_EF_RELOAD
)
251 WARN_ON_ONCE(!(hwc
->state
& PERF_HES_UPTODATE
));
255 * Set the period again. Some counters can't be stopped, so when we
256 * were stopped we simply disabled the IRQ source and the counter
257 * may have been left counting. If we don't do this step then we may
258 * get an interrupt too soon or *way* too late if the overflow has
259 * happened since disabling.
261 armpmu_event_set_period(event
, hwc
, hwc
->idx
);
262 armpmu
->enable(hwc
, hwc
->idx
);
266 armpmu_del(struct perf_event
*event
, int flags
)
268 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
269 struct pmu_hw_events
*hw_events
= armpmu
->get_hw_events();
270 struct hw_perf_event
*hwc
= &event
->hw
;
275 armpmu_stop(event
, PERF_EF_UPDATE
);
276 hw_events
->events
[idx
] = NULL
;
277 clear_bit(idx
, hw_events
->used_mask
);
279 perf_event_update_userpage(event
);
283 armpmu_add(struct perf_event
*event
, int flags
)
285 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
286 struct pmu_hw_events
*hw_events
= armpmu
->get_hw_events();
287 struct hw_perf_event
*hwc
= &event
->hw
;
291 perf_pmu_disable(event
->pmu
);
293 /* If we don't have a space for the counter then finish early. */
294 idx
= armpmu
->get_event_idx(hw_events
, hwc
);
301 * If there is an event in the counter we are going to use then make
302 * sure it is disabled.
305 armpmu
->disable(hwc
, idx
);
306 hw_events
->events
[idx
] = event
;
308 hwc
->state
= PERF_HES_STOPPED
| PERF_HES_UPTODATE
;
309 if (flags
& PERF_EF_START
)
310 armpmu_start(event
, PERF_EF_RELOAD
);
312 /* Propagate our changes to the userspace mapping. */
313 perf_event_update_userpage(event
);
316 perf_pmu_enable(event
->pmu
);
321 validate_event(struct pmu_hw_events
*hw_events
,
322 struct perf_event
*event
)
324 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
325 struct hw_perf_event fake_event
= event
->hw
;
326 struct pmu
*leader_pmu
= event
->group_leader
->pmu
;
328 if (event
->pmu
!= leader_pmu
|| event
->state
<= PERF_EVENT_STATE_OFF
)
331 return armpmu
->get_event_idx(hw_events
, &fake_event
) >= 0;
335 validate_group(struct perf_event
*event
)
337 struct perf_event
*sibling
, *leader
= event
->group_leader
;
338 struct pmu_hw_events fake_pmu
;
339 DECLARE_BITMAP(fake_used_mask
, ARMPMU_MAX_HWEVENTS
);
342 * Initialise the fake PMU. We only need to populate the
343 * used_mask for the purposes of validation.
345 memset(fake_used_mask
, 0, sizeof(fake_used_mask
));
346 fake_pmu
.used_mask
= fake_used_mask
;
348 if (!validate_event(&fake_pmu
, leader
))
351 list_for_each_entry(sibling
, &leader
->sibling_list
, group_entry
) {
352 if (!validate_event(&fake_pmu
, sibling
))
356 if (!validate_event(&fake_pmu
, event
))
362 static irqreturn_t
armpmu_platform_irq(int irq
, void *dev
)
364 struct arm_pmu
*armpmu
= (struct arm_pmu
*) dev
;
365 struct platform_device
*plat_device
= armpmu
->plat_device
;
366 struct arm_pmu_platdata
*plat
= dev_get_platdata(&plat_device
->dev
);
368 return plat
->handle_irq(irq
, dev
, armpmu
->handle_irq
);
372 armpmu_release_hardware(struct arm_pmu
*armpmu
)
375 struct platform_device
*pmu_device
= armpmu
->plat_device
;
376 struct arm_pmu_platdata
*plat
=
377 dev_get_platdata(&pmu_device
->dev
);
379 irqs
= min(pmu_device
->num_resources
, num_possible_cpus());
381 for (i
= 0; i
< irqs
; ++i
) {
382 if (!cpumask_test_and_clear_cpu(i
, &armpmu
->active_irqs
))
384 irq
= platform_get_irq(pmu_device
, i
);
386 if (plat
&& plat
->disable_irq
)
387 plat
->disable_irq(irq
);
388 free_irq(irq
, armpmu
);
392 release_pmu(armpmu
->type
);
396 armpmu_reserve_hardware(struct arm_pmu
*armpmu
)
398 struct arm_pmu_platdata
*plat
;
399 irq_handler_t handle_irq
;
400 int i
, err
, irq
, irqs
;
401 struct platform_device
*pmu_device
= armpmu
->plat_device
;
406 err
= reserve_pmu(armpmu
->type
);
408 pr_warning("unable to reserve pmu\n");
412 plat
= dev_get_platdata(&pmu_device
->dev
);
413 if (plat
&& plat
->handle_irq
)
414 handle_irq
= armpmu_platform_irq
;
416 handle_irq
= armpmu
->handle_irq
;
418 irqs
= min(pmu_device
->num_resources
, num_possible_cpus());
420 pr_err("no irqs for PMUs defined\n");
424 for (i
= 0; i
< irqs
; ++i
) {
426 irq
= platform_get_irq(pmu_device
, i
);
431 * If we have a single PMU interrupt that we can't shift,
432 * assume that we're running on a uniprocessor machine and
433 * continue. Otherwise, continue without this interrupt.
435 if (irq_set_affinity(irq
, cpumask_of(i
)) && irqs
> 1) {
436 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
441 err
= request_irq(irq
, handle_irq
,
442 IRQF_DISABLED
| IRQF_NOBALANCING
,
445 pr_err("unable to request IRQ%d for ARM PMU counters\n",
447 armpmu_release_hardware(armpmu
);
449 } else if (plat
&& plat
->enable_irq
)
450 plat
->enable_irq(irq
);
452 cpumask_set_cpu(i
, &armpmu
->active_irqs
);
459 hw_perf_event_destroy(struct perf_event
*event
)
461 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
462 atomic_t
*active_events
= &armpmu
->active_events
;
463 struct mutex
*pmu_reserve_mutex
= &armpmu
->reserve_mutex
;
465 if (atomic_dec_and_mutex_lock(active_events
, pmu_reserve_mutex
)) {
466 armpmu_release_hardware(armpmu
);
467 mutex_unlock(pmu_reserve_mutex
);
472 event_requires_mode_exclusion(struct perf_event_attr
*attr
)
474 return attr
->exclude_idle
|| attr
->exclude_user
||
475 attr
->exclude_kernel
|| attr
->exclude_hv
;
479 __hw_perf_event_init(struct perf_event
*event
)
481 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
482 struct hw_perf_event
*hwc
= &event
->hw
;
485 mapping
= armpmu
->map_event(event
);
488 pr_debug("event %x:%llx not supported\n", event
->attr
.type
,
494 * We don't assign an index until we actually place the event onto
495 * hardware. Use -1 to signify that we haven't decided where to put it
496 * yet. For SMP systems, each core has it's own PMU so we can't do any
497 * clever allocation or constraints checking at this point.
500 hwc
->config_base
= 0;
505 * Check whether we need to exclude the counter from certain modes.
507 if ((!armpmu
->set_event_filter
||
508 armpmu
->set_event_filter(hwc
, &event
->attr
)) &&
509 event_requires_mode_exclusion(&event
->attr
)) {
510 pr_debug("ARM performance counters do not support "
516 * Store the event encoding into the config_base field.
518 hwc
->config_base
|= (unsigned long)mapping
;
520 if (!hwc
->sample_period
) {
521 hwc
->sample_period
= armpmu
->max_period
;
522 hwc
->last_period
= hwc
->sample_period
;
523 local64_set(&hwc
->period_left
, hwc
->sample_period
);
527 if (event
->group_leader
!= event
) {
528 err
= validate_group(event
);
536 static int armpmu_event_init(struct perf_event
*event
)
538 struct arm_pmu
*armpmu
= to_arm_pmu(event
->pmu
);
540 atomic_t
*active_events
= &armpmu
->active_events
;
542 if (armpmu
->map_event(event
) == -ENOENT
)
545 event
->destroy
= hw_perf_event_destroy
;
547 if (!atomic_inc_not_zero(active_events
)) {
548 mutex_lock(&armpmu
->reserve_mutex
);
549 if (atomic_read(active_events
) == 0)
550 err
= armpmu_reserve_hardware(armpmu
);
553 atomic_inc(active_events
);
554 mutex_unlock(&armpmu
->reserve_mutex
);
560 err
= __hw_perf_event_init(event
);
562 hw_perf_event_destroy(event
);
567 static void armpmu_enable(struct pmu
*pmu
)
569 struct arm_pmu
*armpmu
= to_arm_pmu(pmu
);
570 struct pmu_hw_events
*hw_events
= armpmu
->get_hw_events();
571 int enabled
= bitmap_weight(hw_events
->used_mask
, armpmu
->num_events
);
577 static void armpmu_disable(struct pmu
*pmu
)
579 struct arm_pmu
*armpmu
= to_arm_pmu(pmu
);
583 static void __init
armpmu_init(struct arm_pmu
*armpmu
)
585 atomic_set(&armpmu
->active_events
, 0);
586 mutex_init(&armpmu
->reserve_mutex
);
588 armpmu
->pmu
= (struct pmu
) {
589 .pmu_enable
= armpmu_enable
,
590 .pmu_disable
= armpmu_disable
,
591 .event_init
= armpmu_event_init
,
594 .start
= armpmu_start
,
600 int __init
armpmu_register(struct arm_pmu
*armpmu
, char *name
, int type
)
603 return perf_pmu_register(&armpmu
->pmu
, name
, type
);
606 /* Include the PMU-specific implementations. */
607 #include "perf_event_xscale.c"
608 #include "perf_event_v6.c"
609 #include "perf_event_v7.c"
612 * Ensure the PMU has sane values out of reset.
613 * This requires SMP to be available, so exists as a separate initcall.
618 if (cpu_pmu
&& cpu_pmu
->reset
)
619 return on_each_cpu(cpu_pmu
->reset
, NULL
, 1);
622 arch_initcall(cpu_pmu_reset
);
625 * PMU platform driver and devicetree bindings.
627 static struct of_device_id armpmu_of_device_ids
[] = {
628 {.compatible
= "arm,cortex-a9-pmu"},
629 {.compatible
= "arm,cortex-a8-pmu"},
630 {.compatible
= "arm,arm1136-pmu"},
631 {.compatible
= "arm,arm1176-pmu"},
635 static struct platform_device_id armpmu_plat_device_ids
[] = {
640 static int __devinit
armpmu_device_probe(struct platform_device
*pdev
)
645 cpu_pmu
->plat_device
= pdev
;
649 static struct platform_driver armpmu_driver
= {
652 .of_match_table
= armpmu_of_device_ids
,
654 .probe
= armpmu_device_probe
,
655 .id_table
= armpmu_plat_device_ids
,
658 static int __init
register_pmu_driver(void)
660 return platform_driver_register(&armpmu_driver
);
662 device_initcall(register_pmu_driver
);
664 static struct pmu_hw_events
*armpmu_get_cpu_events(void)
666 return &__get_cpu_var(cpu_hw_events
);
669 static void __init
cpu_pmu_init(struct arm_pmu
*armpmu
)
672 for_each_possible_cpu(cpu
) {
673 struct pmu_hw_events
*events
= &per_cpu(cpu_hw_events
, cpu
);
674 events
->events
= per_cpu(hw_events
, cpu
);
675 events
->used_mask
= per_cpu(used_mask
, cpu
);
676 raw_spin_lock_init(&events
->pmu_lock
);
678 armpmu
->get_hw_events
= armpmu_get_cpu_events
;
679 armpmu
->type
= ARM_PMU_DEVICE_CPU
;
683 * CPU PMU identification and registration.
686 init_hw_perf_events(void)
688 unsigned long cpuid
= read_cpuid_id();
689 unsigned long implementor
= (cpuid
& 0xFF000000) >> 24;
690 unsigned long part_number
= (cpuid
& 0xFFF0);
693 if (0x41 == implementor
) {
694 switch (part_number
) {
695 case 0xB360: /* ARM1136 */
696 case 0xB560: /* ARM1156 */
697 case 0xB760: /* ARM1176 */
698 cpu_pmu
= armv6pmu_init();
700 case 0xB020: /* ARM11mpcore */
701 cpu_pmu
= armv6mpcore_pmu_init();
703 case 0xC080: /* Cortex-A8 */
704 cpu_pmu
= armv7_a8_pmu_init();
706 case 0xC090: /* Cortex-A9 */
707 cpu_pmu
= armv7_a9_pmu_init();
709 case 0xC050: /* Cortex-A5 */
710 cpu_pmu
= armv7_a5_pmu_init();
712 case 0xC0F0: /* Cortex-A15 */
713 cpu_pmu
= armv7_a15_pmu_init();
715 case 0xC070: /* Cortex-A7 */
716 cpu_pmu
= armv7_a7_pmu_init();
719 /* Intel CPUs [xscale]. */
720 } else if (0x69 == implementor
) {
721 part_number
= (cpuid
>> 13) & 0x7;
722 switch (part_number
) {
724 cpu_pmu
= xscale1pmu_init();
727 cpu_pmu
= xscale2pmu_init();
733 pr_info("enabled with %s PMU driver, %d counters available\n",
734 cpu_pmu
->name
, cpu_pmu
->num_events
);
735 cpu_pmu_init(cpu_pmu
);
736 armpmu_register(cpu_pmu
, "cpu", PERF_TYPE_RAW
);
738 pr_info("no hardware support available\n");
743 early_initcall(init_hw_perf_events
);
746 * Callchain handling code.
750 * The registers we're interested in are at the end of the variable
751 * length saved register structure. The fp points at the end of this
752 * structure so the address of this struct is:
753 * (struct frame_tail *)(xxx->fp)-1
755 * This code has been adapted from the ARM OProfile support.
758 struct frame_tail __user
*fp
;
761 } __attribute__((packed
));
764 * Get the return address for a single stackframe and return a pointer to the
767 static struct frame_tail __user
*
768 user_backtrace(struct frame_tail __user
*tail
,
769 struct perf_callchain_entry
*entry
)
771 struct frame_tail buftail
;
773 /* Also check accessibility of one struct frame_tail beyond */
774 if (!access_ok(VERIFY_READ
, tail
, sizeof(buftail
)))
776 if (__copy_from_user_inatomic(&buftail
, tail
, sizeof(buftail
)))
779 perf_callchain_store(entry
, buftail
.lr
);
782 * Frame pointers should strictly progress back up the stack
783 * (towards higher addresses).
785 if (tail
+ 1 >= buftail
.fp
)
788 return buftail
.fp
- 1;
792 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
794 struct frame_tail __user
*tail
;
797 tail
= (struct frame_tail __user
*)regs
->ARM_fp
- 1;
799 while ((entry
->nr
< PERF_MAX_STACK_DEPTH
) &&
800 tail
&& !((unsigned long)tail
& 0x3))
801 tail
= user_backtrace(tail
, entry
);
805 * Gets called by walk_stackframe() for every stackframe. This will be called
806 * whist unwinding the stackframe and is like a subroutine return so we use
810 callchain_trace(struct stackframe
*fr
,
813 struct perf_callchain_entry
*entry
= data
;
814 perf_callchain_store(entry
, fr
->pc
);
819 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
821 struct stackframe fr
;
823 fr
.fp
= regs
->ARM_fp
;
824 fr
.sp
= regs
->ARM_sp
;
825 fr
.lr
= regs
->ARM_lr
;
826 fr
.pc
= regs
->ARM_pc
;
827 walk_stackframe(&fr
, callchain_trace
, entry
);