2 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
4 * ARMv7 support: Jean Pihet <jpihet@mvista.com>
5 * 2010 (c) MontaVista Software, LLC.
7 * Copied from ARMv6 code, with the low level code inspired
8 * by the ARMv7 Oprofile code.
10 * Cortex-A8 has up to 4 configurable performance counters and
11 * a single cycle counter.
12 * Cortex-A9 has up to 31 configurable performance counters and
13 * a single cycle counter.
15 * All counters can be enabled/disabled and IRQ masked separately. The cycle
16 * counter and all 4 performance counters together can be reset separately.
22 #include <asm/cputype.h>
23 #include <asm/irq_regs.h>
25 #include "../vfp/vfpinstr.h"
28 #include <linux/perf/arm_pmu.h>
29 #include <linux/platform_device.h>
32 * Common ARMv7 event types
34 * Note: An implementation may not be able to count all of these events
35 * but the encodings are considered to be `reserved' in the case that
36 * they are not available.
38 #define ARMV7_PERFCTR_PMNC_SW_INCR 0x00
39 #define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01
40 #define ARMV7_PERFCTR_ITLB_REFILL 0x02
41 #define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03
42 #define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04
43 #define ARMV7_PERFCTR_DTLB_REFILL 0x05
44 #define ARMV7_PERFCTR_MEM_READ 0x06
45 #define ARMV7_PERFCTR_MEM_WRITE 0x07
46 #define ARMV7_PERFCTR_INSTR_EXECUTED 0x08
47 #define ARMV7_PERFCTR_EXC_TAKEN 0x09
48 #define ARMV7_PERFCTR_EXC_EXECUTED 0x0A
49 #define ARMV7_PERFCTR_CID_WRITE 0x0B
52 * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
54 * - all (taken) branch instructions,
55 * - instructions that explicitly write the PC,
56 * - exception generating instructions.
58 #define ARMV7_PERFCTR_PC_WRITE 0x0C
59 #define ARMV7_PERFCTR_PC_IMM_BRANCH 0x0D
60 #define ARMV7_PERFCTR_PC_PROC_RETURN 0x0E
61 #define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F
62 #define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0x10
63 #define ARMV7_PERFCTR_CLOCK_CYCLES 0x11
64 #define ARMV7_PERFCTR_PC_BRANCH_PRED 0x12
66 /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
67 #define ARMV7_PERFCTR_MEM_ACCESS 0x13
68 #define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0x14
69 #define ARMV7_PERFCTR_L1_DCACHE_WB 0x15
70 #define ARMV7_PERFCTR_L2_CACHE_ACCESS 0x16
71 #define ARMV7_PERFCTR_L2_CACHE_REFILL 0x17
72 #define ARMV7_PERFCTR_L2_CACHE_WB 0x18
73 #define ARMV7_PERFCTR_BUS_ACCESS 0x19
74 #define ARMV7_PERFCTR_MEM_ERROR 0x1A
75 #define ARMV7_PERFCTR_INSTR_SPEC 0x1B
76 #define ARMV7_PERFCTR_TTBR_WRITE 0x1C
77 #define ARMV7_PERFCTR_BUS_CYCLES 0x1D
79 #define ARMV7_PERFCTR_CPU_CYCLES 0xFF
81 /* ARMv7 Cortex-A8 specific event types */
82 #define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0x43
83 #define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0x44
84 #define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0x50
85 #define ARMV7_A8_PERFCTR_STALL_ISIDE 0x56
87 /* ARMv7 Cortex-A9 specific event types */
88 #define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0x68
89 #define ARMV7_A9_PERFCTR_STALL_ICACHE 0x60
90 #define ARMV7_A9_PERFCTR_STALL_DISPATCH 0x66
92 /* ARMv7 Cortex-A5 specific event types */
93 #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0xc2
94 #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0xc3
96 /* ARMv7 Cortex-A15 specific event types */
97 #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
98 #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
99 #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0x42
100 #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0x43
102 #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0x4C
103 #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0x4D
105 #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0x50
106 #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
107 #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0x52
108 #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0x53
110 #define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0x76
112 /* ARMv7 Cortex-A12 specific event types */
113 #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0x40
114 #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41
116 #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0x50
117 #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51
119 #define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0x76
121 #define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0xe7
123 /* ARMv7 Krait specific event types */
124 #define KRAIT_PMRESR0_GROUP0 0xcc
125 #define KRAIT_PMRESR1_GROUP0 0xd0
126 #define KRAIT_PMRESR2_GROUP0 0xd4
127 #define KRAIT_VPMRESR0_GROUP0 0xd8
129 #define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0x10011
130 #define KRAIT_PERFCTR_L1_ICACHE_MISS 0x10010
132 #define KRAIT_PERFCTR_L1_ITLB_ACCESS 0x12222
133 #define KRAIT_PERFCTR_L1_DTLB_ACCESS 0x12210
135 /* ARMv7 Scorpion specific event types */
136 #define SCORPION_LPM0_GROUP0 0x4c
137 #define SCORPION_LPM1_GROUP0 0x50
138 #define SCORPION_LPM2_GROUP0 0x54
139 #define SCORPION_L2LPM_GROUP0 0x58
140 #define SCORPION_VLPM_GROUP0 0x5c
142 #define SCORPION_ICACHE_ACCESS 0x10053
143 #define SCORPION_ICACHE_MISS 0x10052
145 #define SCORPION_DTLB_ACCESS 0x12013
146 #define SCORPION_DTLB_MISS 0x12012
148 #define SCORPION_ITLB_MISS 0x12021
151 * Cortex-A8 HW events mapping
153 * The hardware events that we support. We do support cache operations but
154 * we have harvard caches and no way to combine instruction and data
155 * accesses/misses in hardware.
157 static const unsigned armv7_a8_perf_map
[PERF_COUNT_HW_MAX
] = {
158 PERF_MAP_ALL_UNSUPPORTED
,
159 [PERF_COUNT_HW_CPU_CYCLES
] = ARMV7_PERFCTR_CPU_CYCLES
,
160 [PERF_COUNT_HW_INSTRUCTIONS
] = ARMV7_PERFCTR_INSTR_EXECUTED
,
161 [PERF_COUNT_HW_CACHE_REFERENCES
] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
162 [PERF_COUNT_HW_CACHE_MISSES
] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
163 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = ARMV7_PERFCTR_PC_WRITE
,
164 [PERF_COUNT_HW_BRANCH_MISSES
] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
165 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
] = ARMV7_A8_PERFCTR_STALL_ISIDE
,
168 static const unsigned armv7_a8_perf_cache_map
[PERF_COUNT_HW_CACHE_MAX
]
169 [PERF_COUNT_HW_CACHE_OP_MAX
]
170 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
171 PERF_CACHE_MAP_ALL_UNSUPPORTED
,
174 * The performance counters don't differentiate between read and write
175 * accesses/misses so this isn't strictly correct, but it's the best we
176 * can do. Writes and reads get combined.
178 [C(L1D
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
179 [C(L1D
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
180 [C(L1D
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
181 [C(L1D
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
183 [C(L1I
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS
,
184 [C(L1I
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_ICACHE_REFILL
,
186 [C(LL
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS
,
187 [C(LL
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL
,
188 [C(LL
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS
,
189 [C(LL
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL
,
191 [C(DTLB
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_DTLB_REFILL
,
192 [C(DTLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_DTLB_REFILL
,
194 [C(ITLB
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_ITLB_REFILL
,
195 [C(ITLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_ITLB_REFILL
,
197 [C(BPU
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
198 [C(BPU
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
199 [C(BPU
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
200 [C(BPU
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
204 * Cortex-A9 HW events mapping
206 static const unsigned armv7_a9_perf_map
[PERF_COUNT_HW_MAX
] = {
207 PERF_MAP_ALL_UNSUPPORTED
,
208 [PERF_COUNT_HW_CPU_CYCLES
] = ARMV7_PERFCTR_CPU_CYCLES
,
209 [PERF_COUNT_HW_INSTRUCTIONS
] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME
,
210 [PERF_COUNT_HW_CACHE_REFERENCES
] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
211 [PERF_COUNT_HW_CACHE_MISSES
] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
212 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = ARMV7_PERFCTR_PC_WRITE
,
213 [PERF_COUNT_HW_BRANCH_MISSES
] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
214 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
] = ARMV7_A9_PERFCTR_STALL_ICACHE
,
215 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND
] = ARMV7_A9_PERFCTR_STALL_DISPATCH
,
218 static const unsigned armv7_a9_perf_cache_map
[PERF_COUNT_HW_CACHE_MAX
]
219 [PERF_COUNT_HW_CACHE_OP_MAX
]
220 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
221 PERF_CACHE_MAP_ALL_UNSUPPORTED
,
224 * The performance counters don't differentiate between read and write
225 * accesses/misses so this isn't strictly correct, but it's the best we
226 * can do. Writes and reads get combined.
228 [C(L1D
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
229 [C(L1D
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
230 [C(L1D
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
231 [C(L1D
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
233 [C(L1I
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_ICACHE_REFILL
,
235 [C(DTLB
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_DTLB_REFILL
,
236 [C(DTLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_DTLB_REFILL
,
238 [C(ITLB
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_ITLB_REFILL
,
239 [C(ITLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_ITLB_REFILL
,
241 [C(BPU
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
242 [C(BPU
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
243 [C(BPU
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
244 [C(BPU
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
248 * Cortex-A5 HW events mapping
250 static const unsigned armv7_a5_perf_map
[PERF_COUNT_HW_MAX
] = {
251 PERF_MAP_ALL_UNSUPPORTED
,
252 [PERF_COUNT_HW_CPU_CYCLES
] = ARMV7_PERFCTR_CPU_CYCLES
,
253 [PERF_COUNT_HW_INSTRUCTIONS
] = ARMV7_PERFCTR_INSTR_EXECUTED
,
254 [PERF_COUNT_HW_CACHE_REFERENCES
] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
255 [PERF_COUNT_HW_CACHE_MISSES
] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
256 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = ARMV7_PERFCTR_PC_WRITE
,
257 [PERF_COUNT_HW_BRANCH_MISSES
] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
260 static const unsigned armv7_a5_perf_cache_map
[PERF_COUNT_HW_CACHE_MAX
]
261 [PERF_COUNT_HW_CACHE_OP_MAX
]
262 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
263 PERF_CACHE_MAP_ALL_UNSUPPORTED
,
265 [C(L1D
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
266 [C(L1D
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
267 [C(L1D
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
268 [C(L1D
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
269 [C(L1D
)][C(OP_PREFETCH
)][C(RESULT_ACCESS
)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL
,
270 [C(L1D
)][C(OP_PREFETCH
)][C(RESULT_MISS
)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP
,
272 [C(L1I
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
273 [C(L1I
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_ICACHE_REFILL
,
275 * The prefetch counters don't differentiate between the I side and the
278 [C(L1I
)][C(OP_PREFETCH
)][C(RESULT_ACCESS
)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL
,
279 [C(L1I
)][C(OP_PREFETCH
)][C(RESULT_MISS
)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP
,
281 [C(DTLB
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_DTLB_REFILL
,
282 [C(DTLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_DTLB_REFILL
,
284 [C(ITLB
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_ITLB_REFILL
,
285 [C(ITLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_ITLB_REFILL
,
287 [C(BPU
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
288 [C(BPU
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
289 [C(BPU
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
290 [C(BPU
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
294 * Cortex-A15 HW events mapping
296 static const unsigned armv7_a15_perf_map
[PERF_COUNT_HW_MAX
] = {
297 PERF_MAP_ALL_UNSUPPORTED
,
298 [PERF_COUNT_HW_CPU_CYCLES
] = ARMV7_PERFCTR_CPU_CYCLES
,
299 [PERF_COUNT_HW_INSTRUCTIONS
] = ARMV7_PERFCTR_INSTR_EXECUTED
,
300 [PERF_COUNT_HW_CACHE_REFERENCES
] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
301 [PERF_COUNT_HW_CACHE_MISSES
] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
302 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC
,
303 [PERF_COUNT_HW_BRANCH_MISSES
] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
304 [PERF_COUNT_HW_BUS_CYCLES
] = ARMV7_PERFCTR_BUS_CYCLES
,
307 static const unsigned armv7_a15_perf_cache_map
[PERF_COUNT_HW_CACHE_MAX
]
308 [PERF_COUNT_HW_CACHE_OP_MAX
]
309 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
310 PERF_CACHE_MAP_ALL_UNSUPPORTED
,
312 [C(L1D
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ
,
313 [C(L1D
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ
,
314 [C(L1D
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE
,
315 [C(L1D
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE
,
318 * Not all performance counters differentiate between read and write
319 * accesses/misses so we're not always strictly correct, but it's the
320 * best we can do. Writes and reads get combined in these cases.
322 [C(L1I
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
323 [C(L1I
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_ICACHE_REFILL
,
325 [C(LL
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ
,
326 [C(LL
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ
,
327 [C(LL
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE
,
328 [C(LL
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE
,
330 [C(DTLB
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ
,
331 [C(DTLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE
,
333 [C(ITLB
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_ITLB_REFILL
,
334 [C(ITLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_ITLB_REFILL
,
336 [C(BPU
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
337 [C(BPU
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
338 [C(BPU
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
339 [C(BPU
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
343 * Cortex-A7 HW events mapping
345 static const unsigned armv7_a7_perf_map
[PERF_COUNT_HW_MAX
] = {
346 PERF_MAP_ALL_UNSUPPORTED
,
347 [PERF_COUNT_HW_CPU_CYCLES
] = ARMV7_PERFCTR_CPU_CYCLES
,
348 [PERF_COUNT_HW_INSTRUCTIONS
] = ARMV7_PERFCTR_INSTR_EXECUTED
,
349 [PERF_COUNT_HW_CACHE_REFERENCES
] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
350 [PERF_COUNT_HW_CACHE_MISSES
] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
351 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = ARMV7_PERFCTR_PC_WRITE
,
352 [PERF_COUNT_HW_BRANCH_MISSES
] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
353 [PERF_COUNT_HW_BUS_CYCLES
] = ARMV7_PERFCTR_BUS_CYCLES
,
356 static const unsigned armv7_a7_perf_cache_map
[PERF_COUNT_HW_CACHE_MAX
]
357 [PERF_COUNT_HW_CACHE_OP_MAX
]
358 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
359 PERF_CACHE_MAP_ALL_UNSUPPORTED
,
362 * The performance counters don't differentiate between read and write
363 * accesses/misses so this isn't strictly correct, but it's the best we
364 * can do. Writes and reads get combined.
366 [C(L1D
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
367 [C(L1D
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
368 [C(L1D
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
369 [C(L1D
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
371 [C(L1I
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
372 [C(L1I
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_ICACHE_REFILL
,
374 [C(LL
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L2_CACHE_ACCESS
,
375 [C(LL
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L2_CACHE_REFILL
,
376 [C(LL
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L2_CACHE_ACCESS
,
377 [C(LL
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L2_CACHE_REFILL
,
379 [C(DTLB
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_DTLB_REFILL
,
380 [C(DTLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_DTLB_REFILL
,
382 [C(ITLB
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_ITLB_REFILL
,
383 [C(ITLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_ITLB_REFILL
,
385 [C(BPU
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
386 [C(BPU
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
387 [C(BPU
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
388 [C(BPU
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
392 * Cortex-A12 HW events mapping
394 static const unsigned armv7_a12_perf_map
[PERF_COUNT_HW_MAX
] = {
395 PERF_MAP_ALL_UNSUPPORTED
,
396 [PERF_COUNT_HW_CPU_CYCLES
] = ARMV7_PERFCTR_CPU_CYCLES
,
397 [PERF_COUNT_HW_INSTRUCTIONS
] = ARMV7_PERFCTR_INSTR_EXECUTED
,
398 [PERF_COUNT_HW_CACHE_REFERENCES
] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
399 [PERF_COUNT_HW_CACHE_MISSES
] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
400 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = ARMV7_A12_PERFCTR_PC_WRITE_SPEC
,
401 [PERF_COUNT_HW_BRANCH_MISSES
] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
402 [PERF_COUNT_HW_BUS_CYCLES
] = ARMV7_PERFCTR_BUS_CYCLES
,
405 static const unsigned armv7_a12_perf_cache_map
[PERF_COUNT_HW_CACHE_MAX
]
406 [PERF_COUNT_HW_CACHE_OP_MAX
]
407 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
408 PERF_CACHE_MAP_ALL_UNSUPPORTED
,
410 [C(L1D
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ
,
411 [C(L1D
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
412 [C(L1D
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE
,
413 [C(L1D
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
416 * Not all performance counters differentiate between read and write
417 * accesses/misses so we're not always strictly correct, but it's the
418 * best we can do. Writes and reads get combined in these cases.
420 [C(L1I
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS
,
421 [C(L1I
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_ICACHE_REFILL
,
423 [C(LL
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ
,
424 [C(LL
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L2_CACHE_REFILL
,
425 [C(LL
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE
,
426 [C(LL
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L2_CACHE_REFILL
,
428 [C(DTLB
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_DTLB_REFILL
,
429 [C(DTLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_DTLB_REFILL
,
430 [C(DTLB
)][C(OP_PREFETCH
)][C(RESULT_MISS
)] = ARMV7_A12_PERFCTR_PF_TLB_REFILL
,
432 [C(ITLB
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_ITLB_REFILL
,
433 [C(ITLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_ITLB_REFILL
,
435 [C(BPU
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
436 [C(BPU
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
437 [C(BPU
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
438 [C(BPU
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
442 * Krait HW events mapping
444 static const unsigned krait_perf_map
[PERF_COUNT_HW_MAX
] = {
445 PERF_MAP_ALL_UNSUPPORTED
,
446 [PERF_COUNT_HW_CPU_CYCLES
] = ARMV7_PERFCTR_CPU_CYCLES
,
447 [PERF_COUNT_HW_INSTRUCTIONS
] = ARMV7_PERFCTR_INSTR_EXECUTED
,
448 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = ARMV7_PERFCTR_PC_WRITE
,
449 [PERF_COUNT_HW_BRANCH_MISSES
] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
450 [PERF_COUNT_HW_BUS_CYCLES
] = ARMV7_PERFCTR_CLOCK_CYCLES
,
453 static const unsigned krait_perf_map_no_branch
[PERF_COUNT_HW_MAX
] = {
454 PERF_MAP_ALL_UNSUPPORTED
,
455 [PERF_COUNT_HW_CPU_CYCLES
] = ARMV7_PERFCTR_CPU_CYCLES
,
456 [PERF_COUNT_HW_INSTRUCTIONS
] = ARMV7_PERFCTR_INSTR_EXECUTED
,
457 [PERF_COUNT_HW_BRANCH_MISSES
] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
458 [PERF_COUNT_HW_BUS_CYCLES
] = ARMV7_PERFCTR_CLOCK_CYCLES
,
461 static const unsigned krait_perf_cache_map
[PERF_COUNT_HW_CACHE_MAX
]
462 [PERF_COUNT_HW_CACHE_OP_MAX
]
463 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
464 PERF_CACHE_MAP_ALL_UNSUPPORTED
,
467 * The performance counters don't differentiate between read and write
468 * accesses/misses so this isn't strictly correct, but it's the best we
469 * can do. Writes and reads get combined.
471 [C(L1D
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
472 [C(L1D
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
473 [C(L1D
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
474 [C(L1D
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
476 [C(L1I
)][C(OP_READ
)][C(RESULT_ACCESS
)] = KRAIT_PERFCTR_L1_ICACHE_ACCESS
,
477 [C(L1I
)][C(OP_READ
)][C(RESULT_MISS
)] = KRAIT_PERFCTR_L1_ICACHE_MISS
,
479 [C(DTLB
)][C(OP_READ
)][C(RESULT_ACCESS
)] = KRAIT_PERFCTR_L1_DTLB_ACCESS
,
480 [C(DTLB
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = KRAIT_PERFCTR_L1_DTLB_ACCESS
,
482 [C(ITLB
)][C(OP_READ
)][C(RESULT_ACCESS
)] = KRAIT_PERFCTR_L1_ITLB_ACCESS
,
483 [C(ITLB
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = KRAIT_PERFCTR_L1_ITLB_ACCESS
,
485 [C(BPU
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
486 [C(BPU
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
487 [C(BPU
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
488 [C(BPU
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
492 * Scorpion HW events mapping
494 static const unsigned scorpion_perf_map
[PERF_COUNT_HW_MAX
] = {
495 PERF_MAP_ALL_UNSUPPORTED
,
496 [PERF_COUNT_HW_CPU_CYCLES
] = ARMV7_PERFCTR_CPU_CYCLES
,
497 [PERF_COUNT_HW_INSTRUCTIONS
] = ARMV7_PERFCTR_INSTR_EXECUTED
,
498 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = ARMV7_PERFCTR_PC_WRITE
,
499 [PERF_COUNT_HW_BRANCH_MISSES
] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
500 [PERF_COUNT_HW_BUS_CYCLES
] = ARMV7_PERFCTR_CLOCK_CYCLES
,
503 static const unsigned scorpion_perf_cache_map
[PERF_COUNT_HW_CACHE_MAX
]
504 [PERF_COUNT_HW_CACHE_OP_MAX
]
505 [PERF_COUNT_HW_CACHE_RESULT_MAX
] = {
506 PERF_CACHE_MAP_ALL_UNSUPPORTED
,
508 * The performance counters don't differentiate between read and write
509 * accesses/misses so this isn't strictly correct, but it's the best we
510 * can do. Writes and reads get combined.
512 [C(L1D
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
513 [C(L1D
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
514 [C(L1D
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS
,
515 [C(L1D
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_L1_DCACHE_REFILL
,
516 [C(L1I
)][C(OP_READ
)][C(RESULT_ACCESS
)] = SCORPION_ICACHE_ACCESS
,
517 [C(L1I
)][C(OP_READ
)][C(RESULT_MISS
)] = SCORPION_ICACHE_MISS
,
519 * Only ITLB misses and DTLB refills are supported. If users want the
520 * DTLB refills misses a raw counter must be used.
522 [C(DTLB
)][C(OP_READ
)][C(RESULT_ACCESS
)] = SCORPION_DTLB_ACCESS
,
523 [C(DTLB
)][C(OP_READ
)][C(RESULT_MISS
)] = SCORPION_DTLB_MISS
,
524 [C(DTLB
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = SCORPION_DTLB_ACCESS
,
525 [C(DTLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = SCORPION_DTLB_MISS
,
526 [C(ITLB
)][C(OP_READ
)][C(RESULT_MISS
)] = SCORPION_ITLB_MISS
,
527 [C(ITLB
)][C(OP_WRITE
)][C(RESULT_MISS
)] = SCORPION_ITLB_MISS
,
528 [C(BPU
)][C(OP_READ
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
529 [C(BPU
)][C(OP_READ
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
530 [C(BPU
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = ARMV7_PERFCTR_PC_BRANCH_PRED
,
531 [C(BPU
)][C(OP_WRITE
)][C(RESULT_MISS
)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED
,
535 * Perf Events' indices
537 #define ARMV7_IDX_CYCLE_COUNTER 0
538 #define ARMV7_IDX_COUNTER0 1
539 #define ARMV7_IDX_COUNTER_LAST(cpu_pmu) \
540 (ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
542 #define ARMV7_MAX_COUNTERS 32
543 #define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1)
546 * ARMv7 low level PMNC access
550 * Perf Event to low level counters mapping
552 #define ARMV7_IDX_TO_COUNTER(x) \
553 (((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK)
556 * Per-CPU PMNC: config reg
558 #define ARMV7_PMNC_E (1 << 0) /* Enable all counters */
559 #define ARMV7_PMNC_P (1 << 1) /* Reset all counters */
560 #define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */
561 #define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
562 #define ARMV7_PMNC_X (1 << 4) /* Export to ETM */
563 #define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
564 #define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */
565 #define ARMV7_PMNC_N_MASK 0x1f
566 #define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */
569 * FLAG: counters overflow flag status reg
571 #define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */
572 #define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK
575 * PMXEVTYPER: Event selection reg
577 #define ARMV7_EVTYPE_MASK 0xc80000ff /* Mask for writable bits */
578 #define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */
581 * Event filters for PMUv2
583 #define ARMV7_EXCLUDE_PL1 (1 << 31)
584 #define ARMV7_EXCLUDE_USER (1 << 30)
585 #define ARMV7_INCLUDE_HYP (1 << 27)
587 static inline u32
armv7_pmnc_read(void)
590 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val
));
594 static inline void armv7_pmnc_write(u32 val
)
596 val
&= ARMV7_PMNC_MASK
;
598 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val
));
601 static inline int armv7_pmnc_has_overflowed(u32 pmnc
)
603 return pmnc
& ARMV7_OVERFLOWED_MASK
;
606 static inline int armv7_pmnc_counter_valid(struct arm_pmu
*cpu_pmu
, int idx
)
608 return idx
>= ARMV7_IDX_CYCLE_COUNTER
&&
609 idx
<= ARMV7_IDX_COUNTER_LAST(cpu_pmu
);
612 static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc
, int idx
)
614 return pmnc
& BIT(ARMV7_IDX_TO_COUNTER(idx
));
617 static inline void armv7_pmnc_select_counter(int idx
)
619 u32 counter
= ARMV7_IDX_TO_COUNTER(idx
);
620 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter
));
624 static inline u32
armv7pmu_read_counter(struct perf_event
*event
)
626 struct arm_pmu
*cpu_pmu
= to_arm_pmu(event
->pmu
);
627 struct hw_perf_event
*hwc
= &event
->hw
;
631 if (!armv7_pmnc_counter_valid(cpu_pmu
, idx
)) {
632 pr_err("CPU%u reading wrong counter %d\n",
633 smp_processor_id(), idx
);
634 } else if (idx
== ARMV7_IDX_CYCLE_COUNTER
) {
635 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value
));
637 armv7_pmnc_select_counter(idx
);
638 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value
));
644 static inline void armv7pmu_write_counter(struct perf_event
*event
, u32 value
)
646 struct arm_pmu
*cpu_pmu
= to_arm_pmu(event
->pmu
);
647 struct hw_perf_event
*hwc
= &event
->hw
;
650 if (!armv7_pmnc_counter_valid(cpu_pmu
, idx
)) {
651 pr_err("CPU%u writing wrong counter %d\n",
652 smp_processor_id(), idx
);
653 } else if (idx
== ARMV7_IDX_CYCLE_COUNTER
) {
654 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value
));
656 armv7_pmnc_select_counter(idx
);
657 asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (value
));
661 static inline void armv7_pmnc_write_evtsel(int idx
, u32 val
)
663 armv7_pmnc_select_counter(idx
);
664 val
&= ARMV7_EVTYPE_MASK
;
665 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val
));
668 static inline void armv7_pmnc_enable_counter(int idx
)
670 u32 counter
= ARMV7_IDX_TO_COUNTER(idx
);
671 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter
)));
674 static inline void armv7_pmnc_disable_counter(int idx
)
676 u32 counter
= ARMV7_IDX_TO_COUNTER(idx
);
677 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter
)));
680 static inline void armv7_pmnc_enable_intens(int idx
)
682 u32 counter
= ARMV7_IDX_TO_COUNTER(idx
);
683 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter
)));
686 static inline void armv7_pmnc_disable_intens(int idx
)
688 u32 counter
= ARMV7_IDX_TO_COUNTER(idx
);
689 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter
)));
691 /* Clear the overflow flag in case an interrupt is pending. */
692 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter
)));
696 static inline u32
armv7_pmnc_getreset_flags(void)
701 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val
));
703 /* Write to clear flags */
704 val
&= ARMV7_FLAG_MASK
;
705 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val
));
711 static void armv7_pmnc_dump_regs(struct arm_pmu
*cpu_pmu
)
716 pr_info("PMNC registers dump:\n");
718 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val
));
719 pr_info("PMNC =0x%08x\n", val
);
721 asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val
));
722 pr_info("CNTENS=0x%08x\n", val
);
724 asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val
));
725 pr_info("INTENS=0x%08x\n", val
);
727 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val
));
728 pr_info("FLAGS =0x%08x\n", val
);
730 asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val
));
731 pr_info("SELECT=0x%08x\n", val
);
733 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val
));
734 pr_info("CCNT =0x%08x\n", val
);
736 for (cnt
= ARMV7_IDX_COUNTER0
;
737 cnt
<= ARMV7_IDX_COUNTER_LAST(cpu_pmu
); cnt
++) {
738 armv7_pmnc_select_counter(cnt
);
739 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val
));
740 pr_info("CNT[%d] count =0x%08x\n",
741 ARMV7_IDX_TO_COUNTER(cnt
), val
);
742 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val
));
743 pr_info("CNT[%d] evtsel=0x%08x\n",
744 ARMV7_IDX_TO_COUNTER(cnt
), val
);
749 static void armv7pmu_enable_event(struct perf_event
*event
)
752 struct hw_perf_event
*hwc
= &event
->hw
;
753 struct arm_pmu
*cpu_pmu
= to_arm_pmu(event
->pmu
);
754 struct pmu_hw_events
*events
= this_cpu_ptr(cpu_pmu
->hw_events
);
757 if (!armv7_pmnc_counter_valid(cpu_pmu
, idx
)) {
758 pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
759 smp_processor_id(), idx
);
764 * Enable counter and interrupt, and set the counter to count
765 * the event that we're interested in.
767 raw_spin_lock_irqsave(&events
->pmu_lock
, flags
);
772 armv7_pmnc_disable_counter(idx
);
775 * Set event (if destined for PMNx counters)
776 * We only need to set the event for the cycle counter if we
777 * have the ability to perform event filtering.
779 if (cpu_pmu
->set_event_filter
|| idx
!= ARMV7_IDX_CYCLE_COUNTER
)
780 armv7_pmnc_write_evtsel(idx
, hwc
->config_base
);
783 * Enable interrupt for this counter
785 armv7_pmnc_enable_intens(idx
);
790 armv7_pmnc_enable_counter(idx
);
792 raw_spin_unlock_irqrestore(&events
->pmu_lock
, flags
);
795 static void armv7pmu_disable_event(struct perf_event
*event
)
798 struct hw_perf_event
*hwc
= &event
->hw
;
799 struct arm_pmu
*cpu_pmu
= to_arm_pmu(event
->pmu
);
800 struct pmu_hw_events
*events
= this_cpu_ptr(cpu_pmu
->hw_events
);
803 if (!armv7_pmnc_counter_valid(cpu_pmu
, idx
)) {
804 pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
805 smp_processor_id(), idx
);
810 * Disable counter and interrupt
812 raw_spin_lock_irqsave(&events
->pmu_lock
, flags
);
817 armv7_pmnc_disable_counter(idx
);
820 * Disable interrupt for this counter
822 armv7_pmnc_disable_intens(idx
);
824 raw_spin_unlock_irqrestore(&events
->pmu_lock
, flags
);
827 static irqreturn_t
armv7pmu_handle_irq(int irq_num
, void *dev
)
830 struct perf_sample_data data
;
831 struct arm_pmu
*cpu_pmu
= (struct arm_pmu
*)dev
;
832 struct pmu_hw_events
*cpuc
= this_cpu_ptr(cpu_pmu
->hw_events
);
833 struct pt_regs
*regs
;
837 * Get and reset the IRQ flags
839 pmnc
= armv7_pmnc_getreset_flags();
842 * Did an overflow occur?
844 if (!armv7_pmnc_has_overflowed(pmnc
))
848 * Handle the counter(s) overflow(s)
850 regs
= get_irq_regs();
852 for (idx
= 0; idx
< cpu_pmu
->num_events
; ++idx
) {
853 struct perf_event
*event
= cpuc
->events
[idx
];
854 struct hw_perf_event
*hwc
;
856 /* Ignore if we don't have an event. */
861 * We have a single interrupt for all counters. Check that
862 * each counter has overflowed before we process it.
864 if (!armv7_pmnc_counter_has_overflowed(pmnc
, idx
))
868 armpmu_event_update(event
);
869 perf_sample_data_init(&data
, 0, hwc
->last_period
);
870 if (!armpmu_event_set_period(event
))
873 if (perf_event_overflow(event
, &data
, regs
))
874 cpu_pmu
->disable(event
);
878 * Handle the pending perf events.
880 * Note: this call *must* be run with interrupts disabled. For
881 * platforms that can have the PMU interrupts raised as an NMI, this
889 static void armv7pmu_start(struct arm_pmu
*cpu_pmu
)
892 struct pmu_hw_events
*events
= this_cpu_ptr(cpu_pmu
->hw_events
);
894 raw_spin_lock_irqsave(&events
->pmu_lock
, flags
);
895 /* Enable all counters */
896 armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E
);
897 raw_spin_unlock_irqrestore(&events
->pmu_lock
, flags
);
900 static void armv7pmu_stop(struct arm_pmu
*cpu_pmu
)
903 struct pmu_hw_events
*events
= this_cpu_ptr(cpu_pmu
->hw_events
);
905 raw_spin_lock_irqsave(&events
->pmu_lock
, flags
);
906 /* Disable all counters */
907 armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E
);
908 raw_spin_unlock_irqrestore(&events
->pmu_lock
, flags
);
911 static int armv7pmu_get_event_idx(struct pmu_hw_events
*cpuc
,
912 struct perf_event
*event
)
915 struct arm_pmu
*cpu_pmu
= to_arm_pmu(event
->pmu
);
916 struct hw_perf_event
*hwc
= &event
->hw
;
917 unsigned long evtype
= hwc
->config_base
& ARMV7_EVTYPE_EVENT
;
919 /* Always place a cycle counter into the cycle counter. */
920 if (evtype
== ARMV7_PERFCTR_CPU_CYCLES
) {
921 if (test_and_set_bit(ARMV7_IDX_CYCLE_COUNTER
, cpuc
->used_mask
))
924 return ARMV7_IDX_CYCLE_COUNTER
;
928 * For anything other than a cycle counter, try and use
929 * the events counters
931 for (idx
= ARMV7_IDX_COUNTER0
; idx
< cpu_pmu
->num_events
; ++idx
) {
932 if (!test_and_set_bit(idx
, cpuc
->used_mask
))
936 /* The counters are all in use. */
941 * Add an event filter to a given event. This will only work for PMUv2 PMUs.
943 static int armv7pmu_set_event_filter(struct hw_perf_event
*event
,
944 struct perf_event_attr
*attr
)
946 unsigned long config_base
= 0;
948 if (attr
->exclude_idle
)
950 if (attr
->exclude_user
)
951 config_base
|= ARMV7_EXCLUDE_USER
;
952 if (attr
->exclude_kernel
)
953 config_base
|= ARMV7_EXCLUDE_PL1
;
954 if (!attr
->exclude_hv
)
955 config_base
|= ARMV7_INCLUDE_HYP
;
958 * Install the filter into config_base as this is used to
959 * construct the event type.
961 event
->config_base
= config_base
;
966 static void armv7pmu_reset(void *info
)
968 struct arm_pmu
*cpu_pmu
= (struct arm_pmu
*)info
;
969 u32 idx
, nb_cnt
= cpu_pmu
->num_events
;
971 /* The counter and interrupt enable registers are unknown at reset. */
972 for (idx
= ARMV7_IDX_CYCLE_COUNTER
; idx
< nb_cnt
; ++idx
) {
973 armv7_pmnc_disable_counter(idx
);
974 armv7_pmnc_disable_intens(idx
);
977 /* Initialize & Reset PMNC: C and P bits */
978 armv7_pmnc_write(ARMV7_PMNC_P
| ARMV7_PMNC_C
);
981 static int armv7_a8_map_event(struct perf_event
*event
)
983 return armpmu_map_event(event
, &armv7_a8_perf_map
,
984 &armv7_a8_perf_cache_map
, 0xFF);
987 static int armv7_a9_map_event(struct perf_event
*event
)
989 return armpmu_map_event(event
, &armv7_a9_perf_map
,
990 &armv7_a9_perf_cache_map
, 0xFF);
993 static int armv7_a5_map_event(struct perf_event
*event
)
995 return armpmu_map_event(event
, &armv7_a5_perf_map
,
996 &armv7_a5_perf_cache_map
, 0xFF);
999 static int armv7_a15_map_event(struct perf_event
*event
)
1001 return armpmu_map_event(event
, &armv7_a15_perf_map
,
1002 &armv7_a15_perf_cache_map
, 0xFF);
1005 static int armv7_a7_map_event(struct perf_event
*event
)
1007 return armpmu_map_event(event
, &armv7_a7_perf_map
,
1008 &armv7_a7_perf_cache_map
, 0xFF);
1011 static int armv7_a12_map_event(struct perf_event
*event
)
1013 return armpmu_map_event(event
, &armv7_a12_perf_map
,
1014 &armv7_a12_perf_cache_map
, 0xFF);
1017 static int krait_map_event(struct perf_event
*event
)
1019 return armpmu_map_event(event
, &krait_perf_map
,
1020 &krait_perf_cache_map
, 0xFFFFF);
1023 static int krait_map_event_no_branch(struct perf_event
*event
)
1025 return armpmu_map_event(event
, &krait_perf_map_no_branch
,
1026 &krait_perf_cache_map
, 0xFFFFF);
1029 static int scorpion_map_event(struct perf_event
*event
)
1031 return armpmu_map_event(event
, &scorpion_perf_map
,
1032 &scorpion_perf_cache_map
, 0xFFFFF);
1035 static void armv7pmu_init(struct arm_pmu
*cpu_pmu
)
1037 cpu_pmu
->handle_irq
= armv7pmu_handle_irq
;
1038 cpu_pmu
->enable
= armv7pmu_enable_event
;
1039 cpu_pmu
->disable
= armv7pmu_disable_event
;
1040 cpu_pmu
->read_counter
= armv7pmu_read_counter
;
1041 cpu_pmu
->write_counter
= armv7pmu_write_counter
;
1042 cpu_pmu
->get_event_idx
= armv7pmu_get_event_idx
;
1043 cpu_pmu
->start
= armv7pmu_start
;
1044 cpu_pmu
->stop
= armv7pmu_stop
;
1045 cpu_pmu
->reset
= armv7pmu_reset
;
1046 cpu_pmu
->max_period
= (1LLU << 32) - 1;
1049 static void armv7_read_num_pmnc_events(void *info
)
1053 /* Read the nb of CNTx counters supported from PMNC */
1054 *nb_cnt
= (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT
) & ARMV7_PMNC_N_MASK
;
1056 /* Add the CPU cycles counter */
1060 static int armv7_probe_num_events(struct arm_pmu
*arm_pmu
)
1062 return smp_call_function_any(&arm_pmu
->supported_cpus
,
1063 armv7_read_num_pmnc_events
,
1064 &arm_pmu
->num_events
, 1);
1067 static int armv7_a8_pmu_init(struct arm_pmu
*cpu_pmu
)
1069 armv7pmu_init(cpu_pmu
);
1070 cpu_pmu
->name
= "armv7_cortex_a8";
1071 cpu_pmu
->map_event
= armv7_a8_map_event
;
1072 return armv7_probe_num_events(cpu_pmu
);
1075 static int armv7_a9_pmu_init(struct arm_pmu
*cpu_pmu
)
1077 armv7pmu_init(cpu_pmu
);
1078 cpu_pmu
->name
= "armv7_cortex_a9";
1079 cpu_pmu
->map_event
= armv7_a9_map_event
;
1080 return armv7_probe_num_events(cpu_pmu
);
1083 static int armv7_a5_pmu_init(struct arm_pmu
*cpu_pmu
)
1085 armv7pmu_init(cpu_pmu
);
1086 cpu_pmu
->name
= "armv7_cortex_a5";
1087 cpu_pmu
->map_event
= armv7_a5_map_event
;
1088 return armv7_probe_num_events(cpu_pmu
);
1091 static int armv7_a15_pmu_init(struct arm_pmu
*cpu_pmu
)
1093 armv7pmu_init(cpu_pmu
);
1094 cpu_pmu
->name
= "armv7_cortex_a15";
1095 cpu_pmu
->map_event
= armv7_a15_map_event
;
1096 cpu_pmu
->set_event_filter
= armv7pmu_set_event_filter
;
1097 return armv7_probe_num_events(cpu_pmu
);
1100 static int armv7_a7_pmu_init(struct arm_pmu
*cpu_pmu
)
1102 armv7pmu_init(cpu_pmu
);
1103 cpu_pmu
->name
= "armv7_cortex_a7";
1104 cpu_pmu
->map_event
= armv7_a7_map_event
;
1105 cpu_pmu
->set_event_filter
= armv7pmu_set_event_filter
;
1106 return armv7_probe_num_events(cpu_pmu
);
1109 static int armv7_a12_pmu_init(struct arm_pmu
*cpu_pmu
)
1111 armv7pmu_init(cpu_pmu
);
1112 cpu_pmu
->name
= "armv7_cortex_a12";
1113 cpu_pmu
->map_event
= armv7_a12_map_event
;
1114 cpu_pmu
->set_event_filter
= armv7pmu_set_event_filter
;
1115 return armv7_probe_num_events(cpu_pmu
);
1118 static int armv7_a17_pmu_init(struct arm_pmu
*cpu_pmu
)
1120 int ret
= armv7_a12_pmu_init(cpu_pmu
);
1121 cpu_pmu
->name
= "armv7_cortex_a17";
1126 * Krait Performance Monitor Region Event Selection Register (PMRESRn)
1129 * +--------------------------------+
1130 * PMRESR0 | EN | CC | CC | CC | CC | N = 1, R = 0
1131 * +--------------------------------+
1132 * PMRESR1 | EN | CC | CC | CC | CC | N = 1, R = 1
1133 * +--------------------------------+
1134 * PMRESR2 | EN | CC | CC | CC | CC | N = 1, R = 2
1135 * +--------------------------------+
1136 * VPMRESR0 | EN | CC | CC | CC | CC | N = 2, R = ?
1137 * +--------------------------------+
1138 * EN | G=3 | G=2 | G=1 | G=0
1142 * hwc->config_base = 0xNRCCG
1144 * N = prefix, 1 for Krait CPU (PMRESRn), 2 for Venum VFP (VPMRESR)
1145 * R = region register
1146 * CC = class of events the group G is choosing from
1147 * G = group or particular event
1149 * Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2
1151 * A region (R) corresponds to a piece of the CPU (execution unit, instruction
1152 * unit, etc.) while the event code (CC) corresponds to a particular class of
1153 * events (interrupts for example). An event code is broken down into
1154 * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for
1158 #define KRAIT_EVENT (1 << 16)
1159 #define VENUM_EVENT (2 << 16)
1160 #define KRAIT_EVENT_MASK (KRAIT_EVENT | VENUM_EVENT)
1161 #define PMRESRn_EN BIT(31)
1163 #define EVENT_REGION(event) (((event) >> 12) & 0xf) /* R */
1164 #define EVENT_GROUP(event) ((event) & 0xf) /* G */
1165 #define EVENT_CODE(event) (((event) >> 4) & 0xff) /* CC */
1166 #define EVENT_VENUM(event) (!!(event & VENUM_EVENT)) /* N=2 */
1167 #define EVENT_CPU(event) (!!(event & KRAIT_EVENT)) /* N=1 */
1169 static u32
krait_read_pmresrn(int n
)
1175 asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val
));
1178 asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val
));
1181 asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val
));
1184 BUG(); /* Should be validated in krait_pmu_get_event_idx() */
1190 static void krait_write_pmresrn(int n
, u32 val
)
1194 asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val
));
1197 asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val
));
1200 asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val
));
1203 BUG(); /* Should be validated in krait_pmu_get_event_idx() */
1207 static u32
venum_read_pmresr(void)
1210 asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val
));
1214 static void venum_write_pmresr(u32 val
)
1216 asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val
));
1219 static void venum_pre_pmresr(u32
*venum_orig_val
, u32
*fp_orig_val
)
1224 BUG_ON(preemptible());
1225 /* CPACR Enable CP10 and CP11 access */
1226 *venum_orig_val
= get_copro_access();
1227 venum_new_val
= *venum_orig_val
| CPACC_SVC(10) | CPACC_SVC(11);
1228 set_copro_access(venum_new_val
);
1231 *fp_orig_val
= fmrx(FPEXC
);
1232 fp_new_val
= *fp_orig_val
| FPEXC_EN
;
1233 fmxr(FPEXC
, fp_new_val
);
1236 static void venum_post_pmresr(u32 venum_orig_val
, u32 fp_orig_val
)
1238 BUG_ON(preemptible());
1240 fmxr(FPEXC
, fp_orig_val
);
1243 set_copro_access(venum_orig_val
);
1246 static u32
krait_get_pmresrn_event(unsigned int region
)
1248 static const u32 pmresrn_table
[] = { KRAIT_PMRESR0_GROUP0
,
1249 KRAIT_PMRESR1_GROUP0
,
1250 KRAIT_PMRESR2_GROUP0
};
1251 return pmresrn_table
[region
];
1254 static void krait_evt_setup(int idx
, u32 config_base
)
1259 unsigned int region
= EVENT_REGION(config_base
);
1260 unsigned int group
= EVENT_GROUP(config_base
);
1261 unsigned int code
= EVENT_CODE(config_base
);
1262 unsigned int group_shift
;
1263 bool venum_event
= EVENT_VENUM(config_base
);
1265 group_shift
= group
* 8;
1266 mask
= 0xff << group_shift
;
1268 /* Configure evtsel for the region and group */
1270 val
= KRAIT_VPMRESR0_GROUP0
;
1272 val
= krait_get_pmresrn_event(region
);
1274 /* Mix in mode-exclusion bits */
1275 val
|= config_base
& (ARMV7_EXCLUDE_USER
| ARMV7_EXCLUDE_PL1
);
1276 armv7_pmnc_write_evtsel(idx
, val
);
1279 venum_pre_pmresr(&vval
, &fval
);
1280 val
= venum_read_pmresr();
1282 val
|= code
<< group_shift
;
1284 venum_write_pmresr(val
);
1285 venum_post_pmresr(vval
, fval
);
1287 val
= krait_read_pmresrn(region
);
1289 val
|= code
<< group_shift
;
1291 krait_write_pmresrn(region
, val
);
1295 static u32
clear_pmresrn_group(u32 val
, int group
)
1300 group_shift
= group
* 8;
1301 mask
= 0xff << group_shift
;
1304 /* Don't clear enable bit if entire region isn't disabled */
1305 if (val
& ~PMRESRn_EN
)
1306 return val
|= PMRESRn_EN
;
1311 static void krait_clearpmu(u32 config_base
)
1315 unsigned int region
= EVENT_REGION(config_base
);
1316 unsigned int group
= EVENT_GROUP(config_base
);
1317 bool venum_event
= EVENT_VENUM(config_base
);
1320 venum_pre_pmresr(&vval
, &fval
);
1321 val
= venum_read_pmresr();
1322 val
= clear_pmresrn_group(val
, group
);
1323 venum_write_pmresr(val
);
1324 venum_post_pmresr(vval
, fval
);
1326 val
= krait_read_pmresrn(region
);
1327 val
= clear_pmresrn_group(val
, group
);
1328 krait_write_pmresrn(region
, val
);
1332 static void krait_pmu_disable_event(struct perf_event
*event
)
1334 unsigned long flags
;
1335 struct hw_perf_event
*hwc
= &event
->hw
;
1337 struct arm_pmu
*cpu_pmu
= to_arm_pmu(event
->pmu
);
1338 struct pmu_hw_events
*events
= this_cpu_ptr(cpu_pmu
->hw_events
);
1340 /* Disable counter and interrupt */
1341 raw_spin_lock_irqsave(&events
->pmu_lock
, flags
);
1343 /* Disable counter */
1344 armv7_pmnc_disable_counter(idx
);
1347 * Clear pmresr code (if destined for PMNx counters)
1349 if (hwc
->config_base
& KRAIT_EVENT_MASK
)
1350 krait_clearpmu(hwc
->config_base
);
1352 /* Disable interrupt for this counter */
1353 armv7_pmnc_disable_intens(idx
);
1355 raw_spin_unlock_irqrestore(&events
->pmu_lock
, flags
);
1358 static void krait_pmu_enable_event(struct perf_event
*event
)
1360 unsigned long flags
;
1361 struct hw_perf_event
*hwc
= &event
->hw
;
1363 struct arm_pmu
*cpu_pmu
= to_arm_pmu(event
->pmu
);
1364 struct pmu_hw_events
*events
= this_cpu_ptr(cpu_pmu
->hw_events
);
1367 * Enable counter and interrupt, and set the counter to count
1368 * the event that we're interested in.
1370 raw_spin_lock_irqsave(&events
->pmu_lock
, flags
);
1372 /* Disable counter */
1373 armv7_pmnc_disable_counter(idx
);
1376 * Set event (if destined for PMNx counters)
1377 * We set the event for the cycle counter because we
1378 * have the ability to perform event filtering.
1380 if (hwc
->config_base
& KRAIT_EVENT_MASK
)
1381 krait_evt_setup(idx
, hwc
->config_base
);
1383 armv7_pmnc_write_evtsel(idx
, hwc
->config_base
);
1385 /* Enable interrupt for this counter */
1386 armv7_pmnc_enable_intens(idx
);
1388 /* Enable counter */
1389 armv7_pmnc_enable_counter(idx
);
1391 raw_spin_unlock_irqrestore(&events
->pmu_lock
, flags
);
1394 static void krait_pmu_reset(void *info
)
1397 struct arm_pmu
*cpu_pmu
= info
;
1398 u32 idx
, nb_cnt
= cpu_pmu
->num_events
;
1400 armv7pmu_reset(info
);
1402 /* Clear all pmresrs */
1403 krait_write_pmresrn(0, 0);
1404 krait_write_pmresrn(1, 0);
1405 krait_write_pmresrn(2, 0);
1407 venum_pre_pmresr(&vval
, &fval
);
1408 venum_write_pmresr(0);
1409 venum_post_pmresr(vval
, fval
);
1411 /* Reset PMxEVNCTCR to sane default */
1412 for (idx
= ARMV7_IDX_CYCLE_COUNTER
; idx
< nb_cnt
; ++idx
) {
1413 armv7_pmnc_select_counter(idx
);
1414 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0));
1419 static int krait_event_to_bit(struct perf_event
*event
, unsigned int region
,
1423 struct hw_perf_event
*hwc
= &event
->hw
;
1424 struct arm_pmu
*cpu_pmu
= to_arm_pmu(event
->pmu
);
1426 if (hwc
->config_base
& VENUM_EVENT
)
1427 bit
= KRAIT_VPMRESR0_GROUP0
;
1429 bit
= krait_get_pmresrn_event(region
);
1430 bit
-= krait_get_pmresrn_event(0);
1433 * Lower bits are reserved for use by the counters (see
1434 * armv7pmu_get_event_idx() for more info)
1436 bit
+= ARMV7_IDX_COUNTER_LAST(cpu_pmu
) + 1;
1442 * We check for column exclusion constraints here.
1443 * Two events cant use the same group within a pmresr register.
1445 static int krait_pmu_get_event_idx(struct pmu_hw_events
*cpuc
,
1446 struct perf_event
*event
)
1450 struct hw_perf_event
*hwc
= &event
->hw
;
1451 unsigned int region
= EVENT_REGION(hwc
->config_base
);
1452 unsigned int code
= EVENT_CODE(hwc
->config_base
);
1453 unsigned int group
= EVENT_GROUP(hwc
->config_base
);
1454 bool venum_event
= EVENT_VENUM(hwc
->config_base
);
1455 bool krait_event
= EVENT_CPU(hwc
->config_base
);
1457 if (venum_event
|| krait_event
) {
1458 /* Ignore invalid events */
1459 if (group
> 3 || region
> 2)
1461 if (venum_event
&& (code
& 0xe0))
1464 bit
= krait_event_to_bit(event
, region
, group
);
1465 if (test_and_set_bit(bit
, cpuc
->used_mask
))
1469 idx
= armv7pmu_get_event_idx(cpuc
, event
);
1470 if (idx
< 0 && bit
>= 0)
1471 clear_bit(bit
, cpuc
->used_mask
);
1476 static void krait_pmu_clear_event_idx(struct pmu_hw_events
*cpuc
,
1477 struct perf_event
*event
)
1480 struct hw_perf_event
*hwc
= &event
->hw
;
1481 unsigned int region
= EVENT_REGION(hwc
->config_base
);
1482 unsigned int group
= EVENT_GROUP(hwc
->config_base
);
1483 bool venum_event
= EVENT_VENUM(hwc
->config_base
);
1484 bool krait_event
= EVENT_CPU(hwc
->config_base
);
1486 if (venum_event
|| krait_event
) {
1487 bit
= krait_event_to_bit(event
, region
, group
);
1488 clear_bit(bit
, cpuc
->used_mask
);
1492 static int krait_pmu_init(struct arm_pmu
*cpu_pmu
)
1494 armv7pmu_init(cpu_pmu
);
1495 cpu_pmu
->name
= "armv7_krait";
1496 /* Some early versions of Krait don't support PC write events */
1497 if (of_property_read_bool(cpu_pmu
->plat_device
->dev
.of_node
,
1498 "qcom,no-pc-write"))
1499 cpu_pmu
->map_event
= krait_map_event_no_branch
;
1501 cpu_pmu
->map_event
= krait_map_event
;
1502 cpu_pmu
->set_event_filter
= armv7pmu_set_event_filter
;
1503 cpu_pmu
->reset
= krait_pmu_reset
;
1504 cpu_pmu
->enable
= krait_pmu_enable_event
;
1505 cpu_pmu
->disable
= krait_pmu_disable_event
;
1506 cpu_pmu
->get_event_idx
= krait_pmu_get_event_idx
;
1507 cpu_pmu
->clear_event_idx
= krait_pmu_clear_event_idx
;
1508 return armv7_probe_num_events(cpu_pmu
);
1512 * Scorpion Local Performance Monitor Register (LPMn)
1515 * +--------------------------------+
1516 * LPM0 | EN | CC | CC | CC | CC | N = 1, R = 0
1517 * +--------------------------------+
1518 * LPM1 | EN | CC | CC | CC | CC | N = 1, R = 1
1519 * +--------------------------------+
1520 * LPM2 | EN | CC | CC | CC | CC | N = 1, R = 2
1521 * +--------------------------------+
1522 * L2LPM | EN | CC | CC | CC | CC | N = 1, R = 3
1523 * +--------------------------------+
1524 * VLPM | EN | CC | CC | CC | CC | N = 2, R = ?
1525 * +--------------------------------+
1526 * EN | G=3 | G=2 | G=1 | G=0
1531 * hwc->config_base = 0xNRCCG
1533 * N = prefix, 1 for Scorpion CPU (LPMn/L2LPM), 2 for Venum VFP (VLPM)
1534 * R = region register
1535 * CC = class of events the group G is choosing from
1536 * G = group or particular event
1538 * Example: 0x12021 is a Scorpion CPU event in LPM2's group 1 with code 2
1540 * A region (R) corresponds to a piece of the CPU (execution unit, instruction
1541 * unit, etc.) while the event code (CC) corresponds to a particular class of
1542 * events (interrupts for example). An event code is broken down into
1543 * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for
1547 static u32
scorpion_read_pmresrn(int n
)
1553 asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val
));
1556 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val
));
1559 asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val
));
1562 asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val
));
1565 BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */
1571 static void scorpion_write_pmresrn(int n
, u32 val
)
1575 asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val
));
1578 asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val
));
1581 asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val
));
1584 asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val
));
1587 BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */
1591 static u32
scorpion_get_pmresrn_event(unsigned int region
)
1593 static const u32 pmresrn_table
[] = { SCORPION_LPM0_GROUP0
,
1594 SCORPION_LPM1_GROUP0
,
1595 SCORPION_LPM2_GROUP0
,
1596 SCORPION_L2LPM_GROUP0
};
1597 return pmresrn_table
[region
];
1600 static void scorpion_evt_setup(int idx
, u32 config_base
)
1605 unsigned int region
= EVENT_REGION(config_base
);
1606 unsigned int group
= EVENT_GROUP(config_base
);
1607 unsigned int code
= EVENT_CODE(config_base
);
1608 unsigned int group_shift
;
1609 bool venum_event
= EVENT_VENUM(config_base
);
1611 group_shift
= group
* 8;
1612 mask
= 0xff << group_shift
;
1614 /* Configure evtsel for the region and group */
1616 val
= SCORPION_VLPM_GROUP0
;
1618 val
= scorpion_get_pmresrn_event(region
);
1620 /* Mix in mode-exclusion bits */
1621 val
|= config_base
& (ARMV7_EXCLUDE_USER
| ARMV7_EXCLUDE_PL1
);
1622 armv7_pmnc_write_evtsel(idx
, val
);
1624 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0));
1627 venum_pre_pmresr(&vval
, &fval
);
1628 val
= venum_read_pmresr();
1630 val
|= code
<< group_shift
;
1632 venum_write_pmresr(val
);
1633 venum_post_pmresr(vval
, fval
);
1635 val
= scorpion_read_pmresrn(region
);
1637 val
|= code
<< group_shift
;
1639 scorpion_write_pmresrn(region
, val
);
1643 static void scorpion_clearpmu(u32 config_base
)
1647 unsigned int region
= EVENT_REGION(config_base
);
1648 unsigned int group
= EVENT_GROUP(config_base
);
1649 bool venum_event
= EVENT_VENUM(config_base
);
1652 venum_pre_pmresr(&vval
, &fval
);
1653 val
= venum_read_pmresr();
1654 val
= clear_pmresrn_group(val
, group
);
1655 venum_write_pmresr(val
);
1656 venum_post_pmresr(vval
, fval
);
1658 val
= scorpion_read_pmresrn(region
);
1659 val
= clear_pmresrn_group(val
, group
);
1660 scorpion_write_pmresrn(region
, val
);
1664 static void scorpion_pmu_disable_event(struct perf_event
*event
)
1666 unsigned long flags
;
1667 struct hw_perf_event
*hwc
= &event
->hw
;
1669 struct arm_pmu
*cpu_pmu
= to_arm_pmu(event
->pmu
);
1670 struct pmu_hw_events
*events
= this_cpu_ptr(cpu_pmu
->hw_events
);
1672 /* Disable counter and interrupt */
1673 raw_spin_lock_irqsave(&events
->pmu_lock
, flags
);
1675 /* Disable counter */
1676 armv7_pmnc_disable_counter(idx
);
1679 * Clear pmresr code (if destined for PMNx counters)
1681 if (hwc
->config_base
& KRAIT_EVENT_MASK
)
1682 scorpion_clearpmu(hwc
->config_base
);
1684 /* Disable interrupt for this counter */
1685 armv7_pmnc_disable_intens(idx
);
1687 raw_spin_unlock_irqrestore(&events
->pmu_lock
, flags
);
1690 static void scorpion_pmu_enable_event(struct perf_event
*event
)
1692 unsigned long flags
;
1693 struct hw_perf_event
*hwc
= &event
->hw
;
1695 struct arm_pmu
*cpu_pmu
= to_arm_pmu(event
->pmu
);
1696 struct pmu_hw_events
*events
= this_cpu_ptr(cpu_pmu
->hw_events
);
1699 * Enable counter and interrupt, and set the counter to count
1700 * the event that we're interested in.
1702 raw_spin_lock_irqsave(&events
->pmu_lock
, flags
);
1704 /* Disable counter */
1705 armv7_pmnc_disable_counter(idx
);
1708 * Set event (if destined for PMNx counters)
1709 * We don't set the event for the cycle counter because we
1710 * don't have the ability to perform event filtering.
1712 if (hwc
->config_base
& KRAIT_EVENT_MASK
)
1713 scorpion_evt_setup(idx
, hwc
->config_base
);
1714 else if (idx
!= ARMV7_IDX_CYCLE_COUNTER
)
1715 armv7_pmnc_write_evtsel(idx
, hwc
->config_base
);
1717 /* Enable interrupt for this counter */
1718 armv7_pmnc_enable_intens(idx
);
1720 /* Enable counter */
1721 armv7_pmnc_enable_counter(idx
);
1723 raw_spin_unlock_irqrestore(&events
->pmu_lock
, flags
);
1726 static void scorpion_pmu_reset(void *info
)
1729 struct arm_pmu
*cpu_pmu
= info
;
1730 u32 idx
, nb_cnt
= cpu_pmu
->num_events
;
1732 armv7pmu_reset(info
);
1734 /* Clear all pmresrs */
1735 scorpion_write_pmresrn(0, 0);
1736 scorpion_write_pmresrn(1, 0);
1737 scorpion_write_pmresrn(2, 0);
1738 scorpion_write_pmresrn(3, 0);
1740 venum_pre_pmresr(&vval
, &fval
);
1741 venum_write_pmresr(0);
1742 venum_post_pmresr(vval
, fval
);
1744 /* Reset PMxEVNCTCR to sane default */
1745 for (idx
= ARMV7_IDX_CYCLE_COUNTER
; idx
< nb_cnt
; ++idx
) {
1746 armv7_pmnc_select_counter(idx
);
1747 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0));
1751 static int scorpion_event_to_bit(struct perf_event
*event
, unsigned int region
,
1755 struct hw_perf_event
*hwc
= &event
->hw
;
1756 struct arm_pmu
*cpu_pmu
= to_arm_pmu(event
->pmu
);
1758 if (hwc
->config_base
& VENUM_EVENT
)
1759 bit
= SCORPION_VLPM_GROUP0
;
1761 bit
= scorpion_get_pmresrn_event(region
);
1762 bit
-= scorpion_get_pmresrn_event(0);
1765 * Lower bits are reserved for use by the counters (see
1766 * armv7pmu_get_event_idx() for more info)
1768 bit
+= ARMV7_IDX_COUNTER_LAST(cpu_pmu
) + 1;
1774 * We check for column exclusion constraints here.
1775 * Two events cant use the same group within a pmresr register.
1777 static int scorpion_pmu_get_event_idx(struct pmu_hw_events
*cpuc
,
1778 struct perf_event
*event
)
1782 struct hw_perf_event
*hwc
= &event
->hw
;
1783 unsigned int region
= EVENT_REGION(hwc
->config_base
);
1784 unsigned int group
= EVENT_GROUP(hwc
->config_base
);
1785 bool venum_event
= EVENT_VENUM(hwc
->config_base
);
1786 bool scorpion_event
= EVENT_CPU(hwc
->config_base
);
1788 if (venum_event
|| scorpion_event
) {
1789 /* Ignore invalid events */
1790 if (group
> 3 || region
> 3)
1793 bit
= scorpion_event_to_bit(event
, region
, group
);
1794 if (test_and_set_bit(bit
, cpuc
->used_mask
))
1798 idx
= armv7pmu_get_event_idx(cpuc
, event
);
1799 if (idx
< 0 && bit
>= 0)
1800 clear_bit(bit
, cpuc
->used_mask
);
1805 static void scorpion_pmu_clear_event_idx(struct pmu_hw_events
*cpuc
,
1806 struct perf_event
*event
)
1809 struct hw_perf_event
*hwc
= &event
->hw
;
1810 unsigned int region
= EVENT_REGION(hwc
->config_base
);
1811 unsigned int group
= EVENT_GROUP(hwc
->config_base
);
1812 bool venum_event
= EVENT_VENUM(hwc
->config_base
);
1813 bool scorpion_event
= EVENT_CPU(hwc
->config_base
);
1815 if (venum_event
|| scorpion_event
) {
1816 bit
= scorpion_event_to_bit(event
, region
, group
);
1817 clear_bit(bit
, cpuc
->used_mask
);
1821 static int scorpion_pmu_init(struct arm_pmu
*cpu_pmu
)
1823 armv7pmu_init(cpu_pmu
);
1824 cpu_pmu
->name
= "armv7_scorpion";
1825 cpu_pmu
->map_event
= scorpion_map_event
;
1826 cpu_pmu
->reset
= scorpion_pmu_reset
;
1827 cpu_pmu
->enable
= scorpion_pmu_enable_event
;
1828 cpu_pmu
->disable
= scorpion_pmu_disable_event
;
1829 cpu_pmu
->get_event_idx
= scorpion_pmu_get_event_idx
;
1830 cpu_pmu
->clear_event_idx
= scorpion_pmu_clear_event_idx
;
1831 return armv7_probe_num_events(cpu_pmu
);
1834 static int scorpion_mp_pmu_init(struct arm_pmu
*cpu_pmu
)
1836 armv7pmu_init(cpu_pmu
);
1837 cpu_pmu
->name
= "armv7_scorpion_mp";
1838 cpu_pmu
->map_event
= scorpion_map_event
;
1839 cpu_pmu
->reset
= scorpion_pmu_reset
;
1840 cpu_pmu
->enable
= scorpion_pmu_enable_event
;
1841 cpu_pmu
->disable
= scorpion_pmu_disable_event
;
1842 cpu_pmu
->get_event_idx
= scorpion_pmu_get_event_idx
;
1843 cpu_pmu
->clear_event_idx
= scorpion_pmu_clear_event_idx
;
1844 return armv7_probe_num_events(cpu_pmu
);
1847 static const struct of_device_id armv7_pmu_of_device_ids
[] = {
1848 {.compatible
= "arm,cortex-a17-pmu", .data
= armv7_a17_pmu_init
},
1849 {.compatible
= "arm,cortex-a15-pmu", .data
= armv7_a15_pmu_init
},
1850 {.compatible
= "arm,cortex-a12-pmu", .data
= armv7_a12_pmu_init
},
1851 {.compatible
= "arm,cortex-a9-pmu", .data
= armv7_a9_pmu_init
},
1852 {.compatible
= "arm,cortex-a8-pmu", .data
= armv7_a8_pmu_init
},
1853 {.compatible
= "arm,cortex-a7-pmu", .data
= armv7_a7_pmu_init
},
1854 {.compatible
= "arm,cortex-a5-pmu", .data
= armv7_a5_pmu_init
},
1855 {.compatible
= "qcom,krait-pmu", .data
= krait_pmu_init
},
1856 {.compatible
= "qcom,scorpion-pmu", .data
= scorpion_pmu_init
},
1857 {.compatible
= "qcom,scorpion-mp-pmu", .data
= scorpion_mp_pmu_init
},
1861 static const struct pmu_probe_info armv7_pmu_probe_table
[] = {
1862 ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A8
, armv7_a8_pmu_init
),
1863 ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A9
, armv7_a9_pmu_init
),
1864 { /* sentinel value */ }
1868 static int armv7_pmu_device_probe(struct platform_device
*pdev
)
1870 return arm_pmu_device_probe(pdev
, armv7_pmu_of_device_ids
,
1871 armv7_pmu_probe_table
);
1874 static struct platform_driver armv7_pmu_driver
= {
1876 .name
= "armv7-pmu",
1877 .of_match_table
= armv7_pmu_of_device_ids
,
1879 .probe
= armv7_pmu_device_probe
,
1882 static int __init
register_armv7_pmu_driver(void)
1884 return platform_driver_register(&armv7_pmu_driver
);
1886 device_initcall(register_armv7_pmu_driver
);
1887 #endif /* CONFIG_CPU_V7 */