2 * linux/arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/efi.h>
11 #include <linux/export.h>
12 #include <linux/kernel.h>
13 #include <linux/stddef.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/utsname.h>
17 #include <linux/initrd.h>
18 #include <linux/console.h>
19 #include <linux/bootmem.h>
20 #include <linux/seq_file.h>
21 #include <linux/screen_info.h>
22 #include <linux/of_iommu.h>
23 #include <linux/of_platform.h>
24 #include <linux/init.h>
25 #include <linux/kexec.h>
26 #include <linux/of_fdt.h>
27 #include <linux/cpu.h>
28 #include <linux/interrupt.h>
29 #include <linux/smp.h>
30 #include <linux/proc_fs.h>
31 #include <linux/memblock.h>
32 #include <linux/bug.h>
33 #include <linux/compiler.h>
34 #include <linux/sort.h>
35 #include <linux/psci.h>
37 #include <asm/unified.h>
40 #include <asm/cputype.h>
43 #include <asm/early_ioremap.h>
44 #include <asm/fixmap.h>
45 #include <asm/procinfo.h>
47 #include <asm/sections.h>
48 #include <asm/setup.h>
49 #include <asm/smp_plat.h>
50 #include <asm/mach-types.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cachetype.h>
53 #include <asm/tlbflush.h>
54 #include <asm/xen/hypervisor.h>
57 #include <asm/mach/arch.h>
58 #include <asm/mach/irq.h>
59 #include <asm/mach/time.h>
60 #include <asm/system_info.h>
61 #include <asm/system_misc.h>
62 #include <asm/traps.h>
63 #include <asm/unwind.h>
64 #include <asm/memblock.h>
70 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
73 static int __init
fpe_setup(char *line
)
75 memcpy(fpe_type
, line
, 8);
79 __setup("fpe=", fpe_setup
);
82 extern void init_default_cache_policy(unsigned long);
83 extern void paging_init(const struct machine_desc
*desc
);
84 extern void early_paging_init(const struct machine_desc
*);
85 extern void sanity_check_meminfo(void);
86 extern enum reboot_mode reboot_mode
;
87 extern void setup_dma_zone(const struct machine_desc
*desc
);
89 unsigned int processor_id
;
90 EXPORT_SYMBOL(processor_id
);
91 unsigned int __machine_arch_type __read_mostly
;
92 EXPORT_SYMBOL(__machine_arch_type
);
93 unsigned int cacheid __read_mostly
;
94 EXPORT_SYMBOL(cacheid
);
96 unsigned int __atags_pointer __initdata
;
98 unsigned int system_rev
;
99 EXPORT_SYMBOL(system_rev
);
101 const char *system_serial
;
102 EXPORT_SYMBOL(system_serial
);
104 unsigned int system_serial_low
;
105 EXPORT_SYMBOL(system_serial_low
);
107 unsigned int system_serial_high
;
108 EXPORT_SYMBOL(system_serial_high
);
110 unsigned int elf_hwcap __read_mostly
;
111 EXPORT_SYMBOL(elf_hwcap
);
113 unsigned int elf_hwcap2 __read_mostly
;
114 EXPORT_SYMBOL(elf_hwcap2
);
118 struct processor processor __read_mostly
;
121 struct cpu_tlb_fns cpu_tlb __read_mostly
;
124 struct cpu_user_fns cpu_user __read_mostly
;
127 struct cpu_cache_fns cpu_cache __read_mostly
;
129 #ifdef CONFIG_OUTER_CACHE
130 struct outer_cache_fns outer_cache __read_mostly
;
131 EXPORT_SYMBOL(outer_cache
);
135 * Cached cpu_architecture() result for use by assembler code.
136 * C code should use the cpu_architecture() function instead of accessing this
139 int __cpu_architecture __read_mostly
= CPU_ARCH_UNKNOWN
;
146 } ____cacheline_aligned
;
148 #ifndef CONFIG_CPU_V7M
149 static struct stack stacks
[NR_CPUS
];
152 char elf_platform
[ELF_PLATFORM_SIZE
];
153 EXPORT_SYMBOL(elf_platform
);
155 static const char *cpu_name
;
156 static const char *machine_name
;
157 static char __initdata cmd_line
[COMMAND_LINE_SIZE
];
158 const struct machine_desc
*machine_desc __initdata
;
160 static union { char c
[4]; unsigned long l
; } endian_test __initdata
= { { 'l', '?', '?', 'b' } };
161 #define ENDIANNESS ((char)endian_test.l)
163 DEFINE_PER_CPU(struct cpuinfo_arm
, cpu_data
);
166 * Standard memory resources
168 static struct resource mem_res
[] = {
173 .flags
= IORESOURCE_MEM
176 .name
= "Kernel code",
179 .flags
= IORESOURCE_SYSTEM_RAM
182 .name
= "Kernel data",
185 .flags
= IORESOURCE_SYSTEM_RAM
189 #define video_ram mem_res[0]
190 #define kernel_code mem_res[1]
191 #define kernel_data mem_res[2]
193 static struct resource io_res
[] = {
198 .flags
= IORESOURCE_IO
| IORESOURCE_BUSY
204 .flags
= IORESOURCE_IO
| IORESOURCE_BUSY
210 .flags
= IORESOURCE_IO
| IORESOURCE_BUSY
214 #define lp0 io_res[0]
215 #define lp1 io_res[1]
216 #define lp2 io_res[2]
218 static const char *proc_arch
[] = {
238 #ifdef CONFIG_CPU_V7M
239 static int __get_cpu_architecture(void)
241 return CPU_ARCH_ARMv7M
;
244 static int __get_cpu_architecture(void)
248 if ((read_cpuid_id() & 0x0008f000) == 0) {
249 cpu_arch
= CPU_ARCH_UNKNOWN
;
250 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
251 cpu_arch
= (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T
: CPU_ARCH_ARMv3
;
252 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
253 cpu_arch
= (read_cpuid_id() >> 16) & 7;
255 cpu_arch
+= CPU_ARCH_ARMv3
;
256 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
257 /* Revised CPUID format. Read the Memory Model Feature
258 * Register 0 and check for VMSAv7 or PMSAv7 */
259 unsigned int mmfr0
= read_cpuid_ext(CPUID_EXT_MMFR0
);
260 if ((mmfr0
& 0x0000000f) >= 0x00000003 ||
261 (mmfr0
& 0x000000f0) >= 0x00000030)
262 cpu_arch
= CPU_ARCH_ARMv7
;
263 else if ((mmfr0
& 0x0000000f) == 0x00000002 ||
264 (mmfr0
& 0x000000f0) == 0x00000020)
265 cpu_arch
= CPU_ARCH_ARMv6
;
267 cpu_arch
= CPU_ARCH_UNKNOWN
;
269 cpu_arch
= CPU_ARCH_UNKNOWN
;
275 int __pure
cpu_architecture(void)
277 BUG_ON(__cpu_architecture
== CPU_ARCH_UNKNOWN
);
279 return __cpu_architecture
;
282 static int cpu_has_aliasing_icache(unsigned int arch
)
285 unsigned int id_reg
, num_sets
, line_size
;
287 /* PIPT caches never alias. */
288 if (icache_is_pipt())
291 /* arch specifies the register format */
294 asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
295 : /* No output operands */
298 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
300 line_size
= 4 << ((id_reg
& 0x7) + 2);
301 num_sets
= ((id_reg
>> 13) & 0x7fff) + 1;
302 aliasing_icache
= (line_size
* num_sets
) > PAGE_SIZE
;
305 aliasing_icache
= read_cpuid_cachetype() & (1 << 11);
308 /* I-cache aliases will be handled by D-cache aliasing code */
312 return aliasing_icache
;
315 static void __init
cacheid_init(void)
317 unsigned int arch
= cpu_architecture();
319 if (arch
== CPU_ARCH_ARMv7M
) {
321 } else if (arch
>= CPU_ARCH_ARMv6
) {
322 unsigned int cachetype
= read_cpuid_cachetype();
323 if ((cachetype
& (7 << 29)) == 4 << 29) {
324 /* ARMv7 register format */
325 arch
= CPU_ARCH_ARMv7
;
326 cacheid
= CACHEID_VIPT_NONALIASING
;
327 switch (cachetype
& (3 << 14)) {
329 cacheid
|= CACHEID_ASID_TAGGED
;
332 cacheid
|= CACHEID_PIPT
;
336 arch
= CPU_ARCH_ARMv6
;
337 if (cachetype
& (1 << 23))
338 cacheid
= CACHEID_VIPT_ALIASING
;
340 cacheid
= CACHEID_VIPT_NONALIASING
;
342 if (cpu_has_aliasing_icache(arch
))
343 cacheid
|= CACHEID_VIPT_I_ALIASING
;
345 cacheid
= CACHEID_VIVT
;
348 pr_info("CPU: %s data cache, %s instruction cache\n",
349 cache_is_vivt() ? "VIVT" :
350 cache_is_vipt_aliasing() ? "VIPT aliasing" :
351 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
352 cache_is_vivt() ? "VIVT" :
353 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
354 icache_is_vipt_aliasing() ? "VIPT aliasing" :
355 icache_is_pipt() ? "PIPT" :
356 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
360 * These functions re-use the assembly code in head.S, which
361 * already provide the required functionality.
363 extern struct proc_info_list
*lookup_processor_type(unsigned int);
365 void __init
early_print(const char *str
, ...)
367 extern void printascii(const char *);
372 vsnprintf(buf
, sizeof(buf
), str
, ap
);
375 #ifdef CONFIG_DEBUG_LL
381 #ifdef CONFIG_ARM_PATCH_IDIV
383 static inline u32 __attribute_const__
sdiv_instruction(void)
385 if (IS_ENABLED(CONFIG_THUMB2_KERNEL
)) {
386 /* "sdiv r0, r0, r1" */
387 u32 insn
= __opcode_thumb32_compose(0xfb90, 0xf0f1);
388 return __opcode_to_mem_thumb32(insn
);
391 /* "sdiv r0, r0, r1" */
392 return __opcode_to_mem_arm(0xe710f110);
395 static inline u32 __attribute_const__
udiv_instruction(void)
397 if (IS_ENABLED(CONFIG_THUMB2_KERNEL
)) {
398 /* "udiv r0, r0, r1" */
399 u32 insn
= __opcode_thumb32_compose(0xfbb0, 0xf0f1);
400 return __opcode_to_mem_thumb32(insn
);
403 /* "udiv r0, r0, r1" */
404 return __opcode_to_mem_arm(0xe730f110);
407 static inline u32 __attribute_const__
bx_lr_instruction(void)
409 if (IS_ENABLED(CONFIG_THUMB2_KERNEL
)) {
411 u32 insn
= __opcode_thumb32_compose(0x4770, 0x46c0);
412 return __opcode_to_mem_thumb32(insn
);
416 return __opcode_to_mem_arm(0xe12fff1e);
419 static void __init
patch_aeabi_idiv(void)
421 extern void __aeabi_uidiv(void);
422 extern void __aeabi_idiv(void);
426 mask
= IS_ENABLED(CONFIG_THUMB2_KERNEL
) ? HWCAP_IDIVT
: HWCAP_IDIVA
;
427 if (!(elf_hwcap
& mask
))
430 pr_info("CPU: div instructions available: patching division code\n");
432 fn_addr
= ((uintptr_t)&__aeabi_uidiv
) & ~1;
433 asm ("" : "+g" (fn_addr
));
434 ((u32
*)fn_addr
)[0] = udiv_instruction();
435 ((u32
*)fn_addr
)[1] = bx_lr_instruction();
436 flush_icache_range(fn_addr
, fn_addr
+ 8);
438 fn_addr
= ((uintptr_t)&__aeabi_idiv
) & ~1;
439 asm ("" : "+g" (fn_addr
));
440 ((u32
*)fn_addr
)[0] = sdiv_instruction();
441 ((u32
*)fn_addr
)[1] = bx_lr_instruction();
442 flush_icache_range(fn_addr
, fn_addr
+ 8);
446 static inline void patch_aeabi_idiv(void) { }
449 static void __init
cpuid_init_hwcaps(void)
454 if (cpu_architecture() < CPU_ARCH_ARMv7
)
457 block
= cpuid_feature_extract(CPUID_EXT_ISAR0
, 24);
459 elf_hwcap
|= HWCAP_IDIVA
;
461 elf_hwcap
|= HWCAP_IDIVT
;
463 /* LPAE implies atomic ldrd/strd instructions */
464 block
= cpuid_feature_extract(CPUID_EXT_MMFR0
, 0);
466 elf_hwcap
|= HWCAP_LPAE
;
468 /* check for supported v8 Crypto instructions */
469 isar5
= read_cpuid_ext(CPUID_EXT_ISAR5
);
471 block
= cpuid_feature_extract_field(isar5
, 4);
473 elf_hwcap2
|= HWCAP2_PMULL
;
475 elf_hwcap2
|= HWCAP2_AES
;
477 block
= cpuid_feature_extract_field(isar5
, 8);
479 elf_hwcap2
|= HWCAP2_SHA1
;
481 block
= cpuid_feature_extract_field(isar5
, 12);
483 elf_hwcap2
|= HWCAP2_SHA2
;
485 block
= cpuid_feature_extract_field(isar5
, 16);
487 elf_hwcap2
|= HWCAP2_CRC32
;
490 static void __init
elf_hwcap_fixup(void)
492 unsigned id
= read_cpuid_id();
495 * HWCAP_TLS is available only on 1136 r1p0 and later,
496 * see also kuser_get_tls_init.
498 if (read_cpuid_part() == ARM_CPU_PART_ARM1136
&&
499 ((id
>> 20) & 3) == 0) {
500 elf_hwcap
&= ~HWCAP_TLS
;
504 /* Verify if CPUID scheme is implemented */
505 if ((id
& 0x000f0000) != 0x000f0000)
509 * If the CPU supports LDREX/STREX and LDREXB/STREXB,
510 * avoid advertising SWP; it may not be atomic with
511 * multiprocessing cores.
513 if (cpuid_feature_extract(CPUID_EXT_ISAR3
, 12) > 1 ||
514 (cpuid_feature_extract(CPUID_EXT_ISAR3
, 12) == 1 &&
515 cpuid_feature_extract(CPUID_EXT_ISAR4
, 20) >= 3))
516 elf_hwcap
&= ~HWCAP_SWP
;
520 * cpu_init - initialise one CPU.
522 * cpu_init sets up the per-CPU stacks.
524 void notrace
cpu_init(void)
526 #ifndef CONFIG_CPU_V7M
527 unsigned int cpu
= smp_processor_id();
528 struct stack
*stk
= &stacks
[cpu
];
530 if (cpu
>= NR_CPUS
) {
531 pr_crit("CPU%u: bad primary CPU number\n", cpu
);
536 * This only works on resume and secondary cores. For booting on the
537 * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
539 set_my_cpu_offset(per_cpu_offset(cpu
));
544 * Define the placement constraint for the inline asm directive below.
545 * In Thumb-2, msr with an immediate value is not allowed.
547 #ifdef CONFIG_THUMB2_KERNEL
554 * setup stacks for re-entrant exception handlers
558 "add r14, %0, %2\n\t"
561 "add r14, %0, %4\n\t"
564 "add r14, %0, %6\n\t"
567 "add r14, %0, %8\n\t"
572 PLC (PSR_F_BIT
| PSR_I_BIT
| IRQ_MODE
),
573 "I" (offsetof(struct stack
, irq
[0])),
574 PLC (PSR_F_BIT
| PSR_I_BIT
| ABT_MODE
),
575 "I" (offsetof(struct stack
, abt
[0])),
576 PLC (PSR_F_BIT
| PSR_I_BIT
| UND_MODE
),
577 "I" (offsetof(struct stack
, und
[0])),
578 PLC (PSR_F_BIT
| PSR_I_BIT
| FIQ_MODE
),
579 "I" (offsetof(struct stack
, fiq
[0])),
580 PLC (PSR_F_BIT
| PSR_I_BIT
| SVC_MODE
)
585 u32 __cpu_logical_map
[NR_CPUS
] = { [0 ... NR_CPUS
-1] = MPIDR_INVALID
};
587 void __init
smp_setup_processor_id(void)
590 u32 mpidr
= is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK
: 0;
591 u32 cpu
= MPIDR_AFFINITY_LEVEL(mpidr
, 0);
593 cpu_logical_map(0) = cpu
;
594 for (i
= 1; i
< nr_cpu_ids
; ++i
)
595 cpu_logical_map(i
) = i
== cpu
? 0 : i
;
598 * clear __my_cpu_offset on boot CPU to avoid hang caused by
599 * using percpu variable early, for example, lockdep will
600 * access percpu variable inside lock_release
602 set_my_cpu_offset(0);
604 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr
);
607 struct mpidr_hash mpidr_hash
;
610 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
611 * level in order to build a linear index from an
612 * MPIDR value. Resulting algorithm is a collision
613 * free hash carried out through shifting and ORing
615 static void __init
smp_build_mpidr_hash(void)
618 u32 fs
[3], bits
[3], ls
, mask
= 0;
620 * Pre-scan the list of MPIDRS and filter out bits that do
621 * not contribute to affinity levels, ie they never toggle.
623 for_each_possible_cpu(i
)
624 mask
|= (cpu_logical_map(i
) ^ cpu_logical_map(0));
625 pr_debug("mask of set bits 0x%x\n", mask
);
627 * Find and stash the last and first bit set at all affinity levels to
628 * check how many bits are required to represent them.
630 for (i
= 0; i
< 3; i
++) {
631 affinity
= MPIDR_AFFINITY_LEVEL(mask
, i
);
633 * Find the MSB bit and LSB bits position
634 * to determine how many bits are required
635 * to express the affinity level.
638 fs
[i
] = affinity
? ffs(affinity
) - 1 : 0;
639 bits
[i
] = ls
- fs
[i
];
642 * An index can be created from the MPIDR by isolating the
643 * significant bits at each affinity level and by shifting
644 * them in order to compress the 24 bits values space to a
645 * compressed set of values. This is equivalent to hashing
646 * the MPIDR through shifting and ORing. It is a collision free
647 * hash though not minimal since some levels might contain a number
648 * of CPUs that is not an exact power of 2 and their bit
649 * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
651 mpidr_hash
.shift_aff
[0] = fs
[0];
652 mpidr_hash
.shift_aff
[1] = MPIDR_LEVEL_BITS
+ fs
[1] - bits
[0];
653 mpidr_hash
.shift_aff
[2] = 2*MPIDR_LEVEL_BITS
+ fs
[2] -
655 mpidr_hash
.mask
= mask
;
656 mpidr_hash
.bits
= bits
[2] + bits
[1] + bits
[0];
657 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
658 mpidr_hash
.shift_aff
[0],
659 mpidr_hash
.shift_aff
[1],
660 mpidr_hash
.shift_aff
[2],
664 * 4x is an arbitrary value used to warn on a hash table much bigger
665 * than expected on most systems.
667 if (mpidr_hash_size() > 4 * num_possible_cpus())
668 pr_warn("Large number of MPIDR hash buckets detected\n");
669 sync_cache_w(&mpidr_hash
);
673 static void __init
setup_processor(void)
675 struct proc_info_list
*list
;
678 * locate processor in the list of supported processor
679 * types. The linker builds this table for us from the
680 * entries in arch/arm/mm/proc-*.S
682 list
= lookup_processor_type(read_cpuid_id());
684 pr_err("CPU configuration botched (ID %08x), unable to continue.\n",
689 cpu_name
= list
->cpu_name
;
690 __cpu_architecture
= __get_cpu_architecture();
693 processor
= *list
->proc
;
696 cpu_tlb
= *list
->tlb
;
699 cpu_user
= *list
->user
;
702 cpu_cache
= *list
->cache
;
705 pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
706 cpu_name
, read_cpuid_id(), read_cpuid_id() & 15,
707 proc_arch
[cpu_architecture()], get_cr());
709 snprintf(init_utsname()->machine
, __NEW_UTS_LEN
+ 1, "%s%c",
710 list
->arch_name
, ENDIANNESS
);
711 snprintf(elf_platform
, ELF_PLATFORM_SIZE
, "%s%c",
712 list
->elf_name
, ENDIANNESS
);
713 elf_hwcap
= list
->elf_hwcap
;
718 #ifndef CONFIG_ARM_THUMB
719 elf_hwcap
&= ~(HWCAP_THUMB
| HWCAP_IDIVT
);
722 init_default_cache_policy(list
->__cpu_mm_mmu_flags
);
724 erratum_a15_798181_init();
732 void __init
dump_machine_table(void)
734 const struct machine_desc
*p
;
736 early_print("Available machine support:\n\nID (hex)\tNAME\n");
737 for_each_machine_desc(p
)
738 early_print("%08x\t%s\n", p
->nr
, p
->name
);
740 early_print("\nPlease check your kernel config and/or bootloader.\n");
743 /* can't use cpu_relax() here as it may require MMU setup */;
746 int __init
arm_add_memory(u64 start
, u64 size
)
751 * Ensure that start/size are aligned to a page boundary.
752 * Size is rounded down, start is rounded up.
754 aligned_start
= PAGE_ALIGN(start
);
755 if (aligned_start
> start
+ size
)
758 size
-= aligned_start
- start
;
760 #ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
761 if (aligned_start
> ULONG_MAX
) {
762 pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
767 if (aligned_start
+ size
> ULONG_MAX
) {
768 pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
771 * To ensure bank->start + bank->size is representable in
772 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
773 * This means we lose a page after masking.
775 size
= ULONG_MAX
- aligned_start
;
779 if (aligned_start
< PHYS_OFFSET
) {
780 if (aligned_start
+ size
<= PHYS_OFFSET
) {
781 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
782 aligned_start
, aligned_start
+ size
);
786 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
787 aligned_start
, (u64
)PHYS_OFFSET
);
789 size
-= PHYS_OFFSET
- aligned_start
;
790 aligned_start
= PHYS_OFFSET
;
793 start
= aligned_start
;
794 size
= size
& ~(phys_addr_t
)(PAGE_SIZE
- 1);
797 * Check whether this memory region has non-zero size or
798 * invalid node number.
803 memblock_add(start
, size
);
808 * Pick out the memory size. We look for mem=size@start,
809 * where start and size are "size[KkMm]"
812 static int __init
early_mem(char *p
)
814 static int usermem __initdata
= 0;
820 * If the user specifies memory size, we
821 * blow away any automatically generated
826 memblock_remove(memblock_start_of_DRAM(),
827 memblock_end_of_DRAM() - memblock_start_of_DRAM());
831 size
= memparse(p
, &endp
);
833 start
= memparse(endp
+ 1, NULL
);
835 arm_add_memory(start
, size
);
839 early_param("mem", early_mem
);
841 static void __init
request_standard_resources(const struct machine_desc
*mdesc
)
843 struct memblock_region
*region
;
844 struct resource
*res
;
846 kernel_code
.start
= virt_to_phys(_text
);
847 kernel_code
.end
= virt_to_phys(_etext
- 1);
848 kernel_data
.start
= virt_to_phys(_sdata
);
849 kernel_data
.end
= virt_to_phys(_end
- 1);
851 for_each_memblock(memory
, region
) {
852 res
= memblock_virt_alloc(sizeof(*res
), 0);
853 res
->name
= "System RAM";
854 res
->start
= __pfn_to_phys(memblock_region_memory_base_pfn(region
));
855 res
->end
= __pfn_to_phys(memblock_region_memory_end_pfn(region
)) - 1;
856 res
->flags
= IORESOURCE_SYSTEM_RAM
| IORESOURCE_BUSY
;
858 request_resource(&iomem_resource
, res
);
860 if (kernel_code
.start
>= res
->start
&&
861 kernel_code
.end
<= res
->end
)
862 request_resource(res
, &kernel_code
);
863 if (kernel_data
.start
>= res
->start
&&
864 kernel_data
.end
<= res
->end
)
865 request_resource(res
, &kernel_data
);
868 if (mdesc
->video_start
) {
869 video_ram
.start
= mdesc
->video_start
;
870 video_ram
.end
= mdesc
->video_end
;
871 request_resource(&iomem_resource
, &video_ram
);
875 * Some machines don't have the possibility of ever
876 * possessing lp0, lp1 or lp2
878 if (mdesc
->reserve_lp0
)
879 request_resource(&ioport_resource
, &lp0
);
880 if (mdesc
->reserve_lp1
)
881 request_resource(&ioport_resource
, &lp1
);
882 if (mdesc
->reserve_lp2
)
883 request_resource(&ioport_resource
, &lp2
);
886 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) || \
888 struct screen_info screen_info
= {
889 .orig_video_lines
= 30,
890 .orig_video_cols
= 80,
891 .orig_video_mode
= 0,
892 .orig_video_ega_bx
= 0,
893 .orig_video_isVGA
= 1,
894 .orig_video_points
= 8
898 static int __init
customize_machine(void)
901 * customizes platform devices, or adds new ones
902 * On DT based machines, we fall back to populating the
903 * machine from the device tree, if no callback is provided,
904 * otherwise we would always need an init_machine callback.
907 if (machine_desc
->init_machine
)
908 machine_desc
->init_machine();
911 of_platform_populate(NULL
, of_default_bus_match_table
,
916 arch_initcall(customize_machine
);
918 static int __init
init_machine_late(void)
920 struct device_node
*root
;
923 if (machine_desc
->init_late
)
924 machine_desc
->init_late();
926 root
= of_find_node_by_path("/");
928 ret
= of_property_read_string(root
, "serial-number",
931 system_serial
= NULL
;
935 system_serial
= kasprintf(GFP_KERNEL
, "%08x%08x",
941 late_initcall(init_machine_late
);
945 * The crash region must be aligned to 128MB to avoid
946 * zImage relocating below the reserved region.
948 #define CRASH_ALIGN (128 << 20)
950 static inline unsigned long long get_total_mem(void)
954 total
= max_low_pfn
- min_low_pfn
;
955 return total
<< PAGE_SHIFT
;
959 * reserve_crashkernel() - reserves memory are for crash kernel
961 * This function reserves memory area given in "crashkernel=" kernel command
962 * line parameter. The memory reserved is used by a dump capture kernel when
963 * primary kernel is crashing.
965 static void __init
reserve_crashkernel(void)
967 unsigned long long crash_size
, crash_base
;
968 unsigned long long total_mem
;
971 total_mem
= get_total_mem();
972 ret
= parse_crashkernel(boot_command_line
, total_mem
,
973 &crash_size
, &crash_base
);
977 if (crash_base
<= 0) {
978 unsigned long long crash_max
= idmap_to_phys((u32
)~0);
979 crash_base
= memblock_find_in_range(CRASH_ALIGN
, crash_max
,
980 crash_size
, CRASH_ALIGN
);
982 pr_err("crashkernel reservation failed - No suitable area found.\n");
986 unsigned long long start
;
988 start
= memblock_find_in_range(crash_base
,
989 crash_base
+ crash_size
,
990 crash_size
, SECTION_SIZE
);
991 if (start
!= crash_base
) {
992 pr_err("crashkernel reservation failed - memory is in use.\n");
997 ret
= memblock_reserve(crash_base
, crash_size
);
999 pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
1000 (unsigned long)crash_base
);
1004 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
1005 (unsigned long)(crash_size
>> 20),
1006 (unsigned long)(crash_base
>> 20),
1007 (unsigned long)(total_mem
>> 20));
1009 crashk_res
.start
= crash_base
;
1010 crashk_res
.end
= crash_base
+ crash_size
- 1;
1011 insert_resource(&iomem_resource
, &crashk_res
);
1014 static inline void reserve_crashkernel(void) {}
1015 #endif /* CONFIG_KEXEC */
1017 void __init
hyp_mode_check(void)
1019 #ifdef CONFIG_ARM_VIRT_EXT
1022 if (is_hyp_mode_available()) {
1023 pr_info("CPU: All CPU(s) started in HYP mode.\n");
1024 pr_info("CPU: Virtualization extensions available.\n");
1025 } else if (is_hyp_mode_mismatched()) {
1026 pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
1027 __boot_cpu_mode
& MODE_MASK
);
1028 pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
1030 pr_info("CPU: All CPU(s) started in SVC mode.\n");
1034 void __init
setup_arch(char **cmdline_p
)
1036 const struct machine_desc
*mdesc
;
1039 mdesc
= setup_machine_fdt(__atags_pointer
);
1041 mdesc
= setup_machine_tags(__atags_pointer
, __machine_arch_type
);
1042 machine_desc
= mdesc
;
1043 machine_name
= mdesc
->name
;
1044 dump_stack_set_arch_desc("%s", mdesc
->name
);
1046 if (mdesc
->reboot_mode
!= REBOOT_HARD
)
1047 reboot_mode
= mdesc
->reboot_mode
;
1049 init_mm
.start_code
= (unsigned long) _text
;
1050 init_mm
.end_code
= (unsigned long) _etext
;
1051 init_mm
.end_data
= (unsigned long) _edata
;
1052 init_mm
.brk
= (unsigned long) _end
;
1054 /* populate cmd_line too for later use, preserving boot_command_line */
1055 strlcpy(cmd_line
, boot_command_line
, COMMAND_LINE_SIZE
);
1056 *cmdline_p
= cmd_line
;
1058 early_fixmap_init();
1059 early_ioremap_init();
1061 parse_early_param();
1064 early_paging_init(mdesc
);
1066 setup_dma_zone(mdesc
);
1068 sanity_check_meminfo();
1069 arm_memblock_init(mdesc
);
1071 early_ioremap_reset();
1074 request_standard_resources(mdesc
);
1077 arm_pm_restart
= mdesc
->restart
;
1079 unflatten_device_tree();
1081 arm_dt_init_cpu_maps();
1086 if (!mdesc
->smp_init
|| !mdesc
->smp_init()) {
1087 if (psci_smp_available())
1088 smp_set_ops(&psci_smp_ops
);
1089 else if (mdesc
->smp
)
1090 smp_set_ops(mdesc
->smp
);
1093 smp_build_mpidr_hash();
1100 reserve_crashkernel();
1102 #ifdef CONFIG_MULTI_IRQ_HANDLER
1103 handle_arch_irq
= mdesc
->handle_irq
;
1107 #if defined(CONFIG_VGA_CONSOLE)
1108 conswitchp
= &vga_con
;
1109 #elif defined(CONFIG_DUMMY_CONSOLE)
1110 conswitchp
= &dummy_con
;
1114 if (mdesc
->init_early
)
1115 mdesc
->init_early();
1119 static int __init
topology_init(void)
1123 for_each_possible_cpu(cpu
) {
1124 struct cpuinfo_arm
*cpuinfo
= &per_cpu(cpu_data
, cpu
);
1125 cpuinfo
->cpu
.hotpluggable
= platform_can_hotplug_cpu(cpu
);
1126 register_cpu(&cpuinfo
->cpu
, cpu
);
1131 subsys_initcall(topology_init
);
1133 #ifdef CONFIG_HAVE_PROC_CPU
1134 static int __init
proc_cpu_init(void)
1136 struct proc_dir_entry
*res
;
1138 res
= proc_mkdir("cpu", NULL
);
1143 fs_initcall(proc_cpu_init
);
1146 static const char *hwcap_str
[] = {
1172 static const char *hwcap2_str
[] = {
1181 static int c_show(struct seq_file
*m
, void *v
)
1186 for_each_online_cpu(i
) {
1188 * glibc reads /proc/cpuinfo to determine the number of
1189 * online processors, looking for lines beginning with
1190 * "processor". Give glibc what it expects.
1192 seq_printf(m
, "processor\t: %d\n", i
);
1193 cpuid
= is_smp() ? per_cpu(cpu_data
, i
).cpuid
: read_cpuid_id();
1194 seq_printf(m
, "model name\t: %s rev %d (%s)\n",
1195 cpu_name
, cpuid
& 15, elf_platform
);
1197 #if defined(CONFIG_SMP)
1198 seq_printf(m
, "BogoMIPS\t: %lu.%02lu\n",
1199 per_cpu(cpu_data
, i
).loops_per_jiffy
/ (500000UL/HZ
),
1200 (per_cpu(cpu_data
, i
).loops_per_jiffy
/ (5000UL/HZ
)) % 100);
1202 seq_printf(m
, "BogoMIPS\t: %lu.%02lu\n",
1203 loops_per_jiffy
/ (500000/HZ
),
1204 (loops_per_jiffy
/ (5000/HZ
)) % 100);
1206 /* dump out the processor features */
1207 seq_puts(m
, "Features\t: ");
1209 for (j
= 0; hwcap_str
[j
]; j
++)
1210 if (elf_hwcap
& (1 << j
))
1211 seq_printf(m
, "%s ", hwcap_str
[j
]);
1213 for (j
= 0; hwcap2_str
[j
]; j
++)
1214 if (elf_hwcap2
& (1 << j
))
1215 seq_printf(m
, "%s ", hwcap2_str
[j
]);
1217 seq_printf(m
, "\nCPU implementer\t: 0x%02x\n", cpuid
>> 24);
1218 seq_printf(m
, "CPU architecture: %s\n",
1219 proc_arch
[cpu_architecture()]);
1221 if ((cpuid
& 0x0008f000) == 0x00000000) {
1223 seq_printf(m
, "CPU part\t: %07x\n", cpuid
>> 4);
1225 if ((cpuid
& 0x0008f000) == 0x00007000) {
1227 seq_printf(m
, "CPU variant\t: 0x%02x\n",
1228 (cpuid
>> 16) & 127);
1231 seq_printf(m
, "CPU variant\t: 0x%x\n",
1232 (cpuid
>> 20) & 15);
1234 seq_printf(m
, "CPU part\t: 0x%03x\n",
1235 (cpuid
>> 4) & 0xfff);
1237 seq_printf(m
, "CPU revision\t: %d\n\n", cpuid
& 15);
1240 seq_printf(m
, "Hardware\t: %s\n", machine_name
);
1241 seq_printf(m
, "Revision\t: %04x\n", system_rev
);
1242 seq_printf(m
, "Serial\t\t: %s\n", system_serial
);
1247 static void *c_start(struct seq_file
*m
, loff_t
*pos
)
1249 return *pos
< 1 ? (void *)1 : NULL
;
1252 static void *c_next(struct seq_file
*m
, void *v
, loff_t
*pos
)
1258 static void c_stop(struct seq_file
*m
, void *v
)
1262 const struct seq_operations cpuinfo_op
= {