2 * arch/arm/mach-at91/at91sam9260.c
4 * Copyright (C) 2006 SAN People
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
15 #include <asm/proc-fns.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/system_misc.h>
21 #include <mach/at91_dbgu.h>
22 #include <mach/at91sam9260.h>
23 #include <mach/at91_aic.h>
24 #include <mach/at91_pmc.h>
25 #include <mach/at91_rstc.h>
32 /* --------------------------------------------------------------------
34 * -------------------------------------------------------------------- */
37 * The peripheral clocks.
39 static struct clk pioA_clk
= {
41 .pmc_mask
= 1 << AT91SAM9260_ID_PIOA
,
42 .type
= CLK_TYPE_PERIPHERAL
,
44 static struct clk pioB_clk
= {
46 .pmc_mask
= 1 << AT91SAM9260_ID_PIOB
,
47 .type
= CLK_TYPE_PERIPHERAL
,
49 static struct clk pioC_clk
= {
51 .pmc_mask
= 1 << AT91SAM9260_ID_PIOC
,
52 .type
= CLK_TYPE_PERIPHERAL
,
54 static struct clk adc_clk
= {
56 .pmc_mask
= 1 << AT91SAM9260_ID_ADC
,
57 .type
= CLK_TYPE_PERIPHERAL
,
60 static struct clk adc_op_clk
= {
62 .type
= CLK_TYPE_PERIPHERAL
,
66 static struct clk usart0_clk
= {
68 .pmc_mask
= 1 << AT91SAM9260_ID_US0
,
69 .type
= CLK_TYPE_PERIPHERAL
,
71 static struct clk usart1_clk
= {
73 .pmc_mask
= 1 << AT91SAM9260_ID_US1
,
74 .type
= CLK_TYPE_PERIPHERAL
,
76 static struct clk usart2_clk
= {
78 .pmc_mask
= 1 << AT91SAM9260_ID_US2
,
79 .type
= CLK_TYPE_PERIPHERAL
,
81 static struct clk mmc_clk
= {
83 .pmc_mask
= 1 << AT91SAM9260_ID_MCI
,
84 .type
= CLK_TYPE_PERIPHERAL
,
86 static struct clk udc_clk
= {
88 .pmc_mask
= 1 << AT91SAM9260_ID_UDP
,
89 .type
= CLK_TYPE_PERIPHERAL
,
91 static struct clk twi_clk
= {
93 .pmc_mask
= 1 << AT91SAM9260_ID_TWI
,
94 .type
= CLK_TYPE_PERIPHERAL
,
96 static struct clk spi0_clk
= {
98 .pmc_mask
= 1 << AT91SAM9260_ID_SPI0
,
99 .type
= CLK_TYPE_PERIPHERAL
,
101 static struct clk spi1_clk
= {
103 .pmc_mask
= 1 << AT91SAM9260_ID_SPI1
,
104 .type
= CLK_TYPE_PERIPHERAL
,
106 static struct clk ssc_clk
= {
108 .pmc_mask
= 1 << AT91SAM9260_ID_SSC
,
109 .type
= CLK_TYPE_PERIPHERAL
,
111 static struct clk tc0_clk
= {
113 .pmc_mask
= 1 << AT91SAM9260_ID_TC0
,
114 .type
= CLK_TYPE_PERIPHERAL
,
116 static struct clk tc1_clk
= {
118 .pmc_mask
= 1 << AT91SAM9260_ID_TC1
,
119 .type
= CLK_TYPE_PERIPHERAL
,
121 static struct clk tc2_clk
= {
123 .pmc_mask
= 1 << AT91SAM9260_ID_TC2
,
124 .type
= CLK_TYPE_PERIPHERAL
,
126 static struct clk ohci_clk
= {
128 .pmc_mask
= 1 << AT91SAM9260_ID_UHP
,
129 .type
= CLK_TYPE_PERIPHERAL
,
131 static struct clk macb_clk
= {
133 .pmc_mask
= 1 << AT91SAM9260_ID_EMAC
,
134 .type
= CLK_TYPE_PERIPHERAL
,
136 static struct clk isi_clk
= {
138 .pmc_mask
= 1 << AT91SAM9260_ID_ISI
,
139 .type
= CLK_TYPE_PERIPHERAL
,
141 static struct clk usart3_clk
= {
142 .name
= "usart3_clk",
143 .pmc_mask
= 1 << AT91SAM9260_ID_US3
,
144 .type
= CLK_TYPE_PERIPHERAL
,
146 static struct clk usart4_clk
= {
147 .name
= "usart4_clk",
148 .pmc_mask
= 1 << AT91SAM9260_ID_US4
,
149 .type
= CLK_TYPE_PERIPHERAL
,
151 static struct clk usart5_clk
= {
152 .name
= "usart5_clk",
153 .pmc_mask
= 1 << AT91SAM9260_ID_US5
,
154 .type
= CLK_TYPE_PERIPHERAL
,
156 static struct clk tc3_clk
= {
158 .pmc_mask
= 1 << AT91SAM9260_ID_TC3
,
159 .type
= CLK_TYPE_PERIPHERAL
,
161 static struct clk tc4_clk
= {
163 .pmc_mask
= 1 << AT91SAM9260_ID_TC4
,
164 .type
= CLK_TYPE_PERIPHERAL
,
166 static struct clk tc5_clk
= {
168 .pmc_mask
= 1 << AT91SAM9260_ID_TC5
,
169 .type
= CLK_TYPE_PERIPHERAL
,
172 static struct clk
*periph_clocks
[] __initdata
= {
202 static struct clk_lookup periph_clocks_lookups
[] = {
203 /* One additional fake clock for macb_hclk */
204 CLKDEV_CON_ID("hclk", &macb_clk
),
205 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk
),
206 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk
),
207 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk
),
208 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk
),
209 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk
),
210 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk
),
211 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk
),
212 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk
),
213 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk
),
214 /* more usart lookup table for DT entries */
215 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck
),
216 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk
),
217 CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk
),
218 CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk
),
219 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk
),
220 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk
),
221 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk
),
222 /* more tc lookup table for DT entries */
223 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk
),
224 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk
),
225 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk
),
226 CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk
),
227 CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk
),
228 CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk
),
229 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk
),
230 /* fake hclk clock */
231 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk
),
232 CLKDEV_CON_ID("pioA", &pioA_clk
),
233 CLKDEV_CON_ID("pioB", &pioB_clk
),
234 CLKDEV_CON_ID("pioC", &pioC_clk
),
237 static struct clk_lookup usart_clocks_lookups
[] = {
238 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck
),
239 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk
),
240 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk
),
241 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk
),
242 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk
),
243 CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk
),
244 CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk
),
248 * The two programmable clocks.
249 * You must configure pin multiplexing to bring these signals out.
251 static struct clk pck0
= {
253 .pmc_mask
= AT91_PMC_PCK0
,
254 .type
= CLK_TYPE_PROGRAMMABLE
,
257 static struct clk pck1
= {
259 .pmc_mask
= AT91_PMC_PCK1
,
260 .type
= CLK_TYPE_PROGRAMMABLE
,
264 static void __init
at91sam9260_register_clocks(void)
268 for (i
= 0; i
< ARRAY_SIZE(periph_clocks
); i
++)
269 clk_register(periph_clocks
[i
]);
271 clkdev_add_table(periph_clocks_lookups
,
272 ARRAY_SIZE(periph_clocks_lookups
));
273 clkdev_add_table(usart_clocks_lookups
,
274 ARRAY_SIZE(usart_clocks_lookups
));
280 /* --------------------------------------------------------------------
282 * -------------------------------------------------------------------- */
284 static struct at91_gpio_bank at91sam9260_gpio
[] __initdata
= {
286 .id
= AT91SAM9260_ID_PIOA
,
287 .regbase
= AT91SAM9260_BASE_PIOA
,
289 .id
= AT91SAM9260_ID_PIOB
,
290 .regbase
= AT91SAM9260_BASE_PIOB
,
292 .id
= AT91SAM9260_ID_PIOC
,
293 .regbase
= AT91SAM9260_BASE_PIOC
,
297 /* --------------------------------------------------------------------
298 * AT91SAM9260 processor initialization
299 * -------------------------------------------------------------------- */
301 static void __init
at91sam9xe_map_io(void)
303 unsigned long sram_size
;
305 switch (at91_soc_initdata
.cidr
& AT91_CIDR_SRAMSIZ
) {
306 case AT91_CIDR_SRAMSIZ_32K
:
307 sram_size
= 2 * SZ_16K
;
309 case AT91_CIDR_SRAMSIZ_16K
:
314 at91_init_sram(0, AT91SAM9XE_SRAM_BASE
, sram_size
);
317 static void __init
at91sam9260_map_io(void)
319 if (cpu_is_at91sam9xe())
321 else if (cpu_is_at91sam9g20())
322 at91_init_sram(0, AT91SAM9G20_SRAM_BASE
, AT91SAM9G20_SRAM_SIZE
);
324 at91_init_sram(0, AT91SAM9260_SRAM_BASE
, AT91SAM9260_SRAM_SIZE
);
327 static void __init
at91sam9260_ioremap_registers(void)
329 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC
);
330 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC
);
331 at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC
, 512);
332 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT
);
333 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC
);
334 at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX
);
337 static void __init
at91sam9260_initialize(void)
339 arm_pm_idle
= at91sam9_idle
;
340 arm_pm_restart
= at91sam9_alt_restart
;
341 at91_extern_irq
= (1 << AT91SAM9260_ID_IRQ0
) | (1 << AT91SAM9260_ID_IRQ1
)
342 | (1 << AT91SAM9260_ID_IRQ2
);
344 /* Register GPIO subsystem */
345 at91_gpio_init(at91sam9260_gpio
, 3);
348 /* --------------------------------------------------------------------
349 * Interrupt initialization
350 * -------------------------------------------------------------------- */
353 * The default interrupt priority levels (0 = lowest, 7 = highest).
355 static unsigned int at91sam9260_default_irq_priority
[NR_AIC_IRQS
] __initdata
= {
356 7, /* Advanced Interrupt Controller */
357 7, /* System Peripherals */
358 1, /* Parallel IO Controller A */
359 1, /* Parallel IO Controller B */
360 1, /* Parallel IO Controller C */
361 0, /* Analog-to-Digital Converter */
365 0, /* Multimedia Card Interface */
366 2, /* USB Device Port */
367 6, /* Two-Wire Interface */
368 5, /* Serial Peripheral Interface 0 */
369 5, /* Serial Peripheral Interface 1 */
370 5, /* Serial Synchronous Controller */
373 0, /* Timer Counter 0 */
374 0, /* Timer Counter 1 */
375 0, /* Timer Counter 2 */
376 2, /* USB Host port */
378 0, /* Image Sensor Interface */
382 0, /* Timer Counter 3 */
383 0, /* Timer Counter 4 */
384 0, /* Timer Counter 5 */
385 0, /* Advanced Interrupt Controller */
386 0, /* Advanced Interrupt Controller */
387 0, /* Advanced Interrupt Controller */
390 struct at91_init_soc __initdata at91sam9260_soc
= {
391 .map_io
= at91sam9260_map_io
,
392 .default_irq_priority
= at91sam9260_default_irq_priority
,
393 .ioremap_registers
= at91sam9260_ioremap_registers
,
394 .register_clocks
= at91sam9260_register_clocks
,
395 .init
= at91sam9260_initialize
,