2 * arch/arm/mach-at91/at91sam9260.c
4 * Copyright (C) 2006 SAN People
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
15 #include <asm/proc-fns.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
20 #include <mach/at91_dbgu.h>
21 #include <mach/at91sam9260.h>
22 #include <mach/at91_pmc.h>
23 #include <mach/at91_rstc.h>
30 /* --------------------------------------------------------------------
32 * -------------------------------------------------------------------- */
35 * The peripheral clocks.
37 static struct clk pioA_clk
= {
39 .pmc_mask
= 1 << AT91SAM9260_ID_PIOA
,
40 .type
= CLK_TYPE_PERIPHERAL
,
42 static struct clk pioB_clk
= {
44 .pmc_mask
= 1 << AT91SAM9260_ID_PIOB
,
45 .type
= CLK_TYPE_PERIPHERAL
,
47 static struct clk pioC_clk
= {
49 .pmc_mask
= 1 << AT91SAM9260_ID_PIOC
,
50 .type
= CLK_TYPE_PERIPHERAL
,
52 static struct clk adc_clk
= {
54 .pmc_mask
= 1 << AT91SAM9260_ID_ADC
,
55 .type
= CLK_TYPE_PERIPHERAL
,
57 static struct clk usart0_clk
= {
59 .pmc_mask
= 1 << AT91SAM9260_ID_US0
,
60 .type
= CLK_TYPE_PERIPHERAL
,
62 static struct clk usart1_clk
= {
64 .pmc_mask
= 1 << AT91SAM9260_ID_US1
,
65 .type
= CLK_TYPE_PERIPHERAL
,
67 static struct clk usart2_clk
= {
69 .pmc_mask
= 1 << AT91SAM9260_ID_US2
,
70 .type
= CLK_TYPE_PERIPHERAL
,
72 static struct clk mmc_clk
= {
74 .pmc_mask
= 1 << AT91SAM9260_ID_MCI
,
75 .type
= CLK_TYPE_PERIPHERAL
,
77 static struct clk udc_clk
= {
79 .pmc_mask
= 1 << AT91SAM9260_ID_UDP
,
80 .type
= CLK_TYPE_PERIPHERAL
,
82 static struct clk twi_clk
= {
84 .pmc_mask
= 1 << AT91SAM9260_ID_TWI
,
85 .type
= CLK_TYPE_PERIPHERAL
,
87 static struct clk spi0_clk
= {
89 .pmc_mask
= 1 << AT91SAM9260_ID_SPI0
,
90 .type
= CLK_TYPE_PERIPHERAL
,
92 static struct clk spi1_clk
= {
94 .pmc_mask
= 1 << AT91SAM9260_ID_SPI1
,
95 .type
= CLK_TYPE_PERIPHERAL
,
97 static struct clk ssc_clk
= {
99 .pmc_mask
= 1 << AT91SAM9260_ID_SSC
,
100 .type
= CLK_TYPE_PERIPHERAL
,
102 static struct clk tc0_clk
= {
104 .pmc_mask
= 1 << AT91SAM9260_ID_TC0
,
105 .type
= CLK_TYPE_PERIPHERAL
,
107 static struct clk tc1_clk
= {
109 .pmc_mask
= 1 << AT91SAM9260_ID_TC1
,
110 .type
= CLK_TYPE_PERIPHERAL
,
112 static struct clk tc2_clk
= {
114 .pmc_mask
= 1 << AT91SAM9260_ID_TC2
,
115 .type
= CLK_TYPE_PERIPHERAL
,
117 static struct clk ohci_clk
= {
119 .pmc_mask
= 1 << AT91SAM9260_ID_UHP
,
120 .type
= CLK_TYPE_PERIPHERAL
,
122 static struct clk macb_clk
= {
124 .pmc_mask
= 1 << AT91SAM9260_ID_EMAC
,
125 .type
= CLK_TYPE_PERIPHERAL
,
127 static struct clk isi_clk
= {
129 .pmc_mask
= 1 << AT91SAM9260_ID_ISI
,
130 .type
= CLK_TYPE_PERIPHERAL
,
132 static struct clk usart3_clk
= {
133 .name
= "usart3_clk",
134 .pmc_mask
= 1 << AT91SAM9260_ID_US3
,
135 .type
= CLK_TYPE_PERIPHERAL
,
137 static struct clk usart4_clk
= {
138 .name
= "usart4_clk",
139 .pmc_mask
= 1 << AT91SAM9260_ID_US4
,
140 .type
= CLK_TYPE_PERIPHERAL
,
142 static struct clk usart5_clk
= {
143 .name
= "usart5_clk",
144 .pmc_mask
= 1 << AT91SAM9260_ID_US5
,
145 .type
= CLK_TYPE_PERIPHERAL
,
147 static struct clk tc3_clk
= {
149 .pmc_mask
= 1 << AT91SAM9260_ID_TC3
,
150 .type
= CLK_TYPE_PERIPHERAL
,
152 static struct clk tc4_clk
= {
154 .pmc_mask
= 1 << AT91SAM9260_ID_TC4
,
155 .type
= CLK_TYPE_PERIPHERAL
,
157 static struct clk tc5_clk
= {
159 .pmc_mask
= 1 << AT91SAM9260_ID_TC5
,
160 .type
= CLK_TYPE_PERIPHERAL
,
163 static struct clk
*periph_clocks
[] __initdata
= {
192 static struct clk_lookup periph_clocks_lookups
[] = {
193 /* One additional fake clock for macb_hclk */
194 CLKDEV_CON_ID("hclk", &macb_clk
),
195 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk
),
196 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk
),
197 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk
),
198 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk
),
199 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk
),
200 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk
),
201 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk
),
202 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk
),
203 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk
),
204 /* more usart lookup table for DT entries */
205 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck
),
206 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk
),
207 CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk
),
208 CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk
),
209 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk
),
210 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk
),
211 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk
),
212 /* fake hclk clock */
213 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk
),
214 CLKDEV_CON_ID("pioA", &pioA_clk
),
215 CLKDEV_CON_ID("pioB", &pioB_clk
),
216 CLKDEV_CON_ID("pioC", &pioC_clk
),
219 static struct clk_lookup usart_clocks_lookups
[] = {
220 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck
),
221 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk
),
222 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk
),
223 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk
),
224 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk
),
225 CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk
),
226 CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk
),
230 * The two programmable clocks.
231 * You must configure pin multiplexing to bring these signals out.
233 static struct clk pck0
= {
235 .pmc_mask
= AT91_PMC_PCK0
,
236 .type
= CLK_TYPE_PROGRAMMABLE
,
239 static struct clk pck1
= {
241 .pmc_mask
= AT91_PMC_PCK1
,
242 .type
= CLK_TYPE_PROGRAMMABLE
,
246 static void __init
at91sam9260_register_clocks(void)
250 for (i
= 0; i
< ARRAY_SIZE(periph_clocks
); i
++)
251 clk_register(periph_clocks
[i
]);
253 clkdev_add_table(periph_clocks_lookups
,
254 ARRAY_SIZE(periph_clocks_lookups
));
255 clkdev_add_table(usart_clocks_lookups
,
256 ARRAY_SIZE(usart_clocks_lookups
));
262 static struct clk_lookup console_clock_lookup
;
264 void __init
at91sam9260_set_console_clock(int id
)
266 if (id
>= ARRAY_SIZE(usart_clocks_lookups
))
269 console_clock_lookup
.con_id
= "usart";
270 console_clock_lookup
.clk
= usart_clocks_lookups
[id
].clk
;
271 clkdev_add(&console_clock_lookup
);
274 /* --------------------------------------------------------------------
276 * -------------------------------------------------------------------- */
278 static struct at91_gpio_bank at91sam9260_gpio
[] __initdata
= {
280 .id
= AT91SAM9260_ID_PIOA
,
281 .regbase
= AT91SAM9260_BASE_PIOA
,
283 .id
= AT91SAM9260_ID_PIOB
,
284 .regbase
= AT91SAM9260_BASE_PIOB
,
286 .id
= AT91SAM9260_ID_PIOC
,
287 .regbase
= AT91SAM9260_BASE_PIOC
,
291 /* --------------------------------------------------------------------
292 * AT91SAM9260 processor initialization
293 * -------------------------------------------------------------------- */
295 static void __init
at91sam9xe_map_io(void)
297 unsigned long sram_size
;
299 switch (at91_soc_initdata
.cidr
& AT91_CIDR_SRAMSIZ
) {
300 case AT91_CIDR_SRAMSIZ_32K
:
301 sram_size
= 2 * SZ_16K
;
303 case AT91_CIDR_SRAMSIZ_16K
:
308 at91_init_sram(0, AT91SAM9XE_SRAM_BASE
, sram_size
);
311 static void __init
at91sam9260_map_io(void)
313 if (cpu_is_at91sam9xe())
315 else if (cpu_is_at91sam9g20())
316 at91_init_sram(0, AT91SAM9G20_SRAM_BASE
, AT91SAM9G20_SRAM_SIZE
);
318 at91_init_sram(0, AT91SAM9260_SRAM_BASE
, AT91SAM9260_SRAM_SIZE
);
321 static void __init
at91sam9260_ioremap_registers(void)
323 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC
);
324 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC
);
325 at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC
, 512);
326 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT
);
327 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC
);
328 at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX
);
331 static void __init
at91sam9260_initialize(void)
333 arm_pm_idle
= at91sam9_idle
;
334 arm_pm_restart
= at91sam9_alt_restart
;
335 at91_extern_irq
= (1 << AT91SAM9260_ID_IRQ0
) | (1 << AT91SAM9260_ID_IRQ1
)
336 | (1 << AT91SAM9260_ID_IRQ2
);
338 /* Register GPIO subsystem */
339 at91_gpio_init(at91sam9260_gpio
, 3);
342 /* --------------------------------------------------------------------
343 * Interrupt initialization
344 * -------------------------------------------------------------------- */
347 * The default interrupt priority levels (0 = lowest, 7 = highest).
349 static unsigned int at91sam9260_default_irq_priority
[NR_AIC_IRQS
] __initdata
= {
350 7, /* Advanced Interrupt Controller */
351 7, /* System Peripherals */
352 1, /* Parallel IO Controller A */
353 1, /* Parallel IO Controller B */
354 1, /* Parallel IO Controller C */
355 0, /* Analog-to-Digital Converter */
359 0, /* Multimedia Card Interface */
360 2, /* USB Device Port */
361 6, /* Two-Wire Interface */
362 5, /* Serial Peripheral Interface 0 */
363 5, /* Serial Peripheral Interface 1 */
364 5, /* Serial Synchronous Controller */
367 0, /* Timer Counter 0 */
368 0, /* Timer Counter 1 */
369 0, /* Timer Counter 2 */
370 2, /* USB Host port */
372 0, /* Image Sensor Interface */
376 0, /* Timer Counter 3 */
377 0, /* Timer Counter 4 */
378 0, /* Timer Counter 5 */
379 0, /* Advanced Interrupt Controller */
380 0, /* Advanced Interrupt Controller */
381 0, /* Advanced Interrupt Controller */
384 struct at91_init_soc __initdata at91sam9260_soc
= {
385 .map_io
= at91sam9260_map_io
,
386 .default_irq_priority
= at91sam9260_default_irq_priority
,
387 .ioremap_registers
= at91sam9260_ioremap_registers
,
388 .register_clocks
= at91sam9260_register_clocks
,
389 .init
= at91sam9260_initialize
,