arch/arm/mach-at91/at91sam9261.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9261.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/proc-fns.h>
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <mach/cpu.h>
  20 #include <mach/at91sam9261.h>
  21 #include <mach/at91_pmc.h>
  22 #include <mach/at91_rstc.h>
  23
  24 #include "soc.h"
  25 #include "generic.h"
  26 #include "clock.h"
  27 #include "sam9_smc.h"
  28
  29 /* --------------------------------------------------------------------
  30  *  Clocks
  31  * -------------------------------------------------------------------- */
  32
  33 /*
  34  * The peripheral clocks.
  35  */
  36 static struct clk pioA_clk = {
  37         .name           = "pioA_clk",
  38         .pmc_mask       = 1 << AT91SAM9261_ID_PIOA,
  39         .type           = CLK_TYPE_PERIPHERAL,
  40 };
  41 static struct clk pioB_clk = {
  42         .name           = "pioB_clk",
  43         .pmc_mask       = 1 << AT91SAM9261_ID_PIOB,
  44         .type           = CLK_TYPE_PERIPHERAL,
  45 };
  46 static struct clk pioC_clk = {
  47         .name           = "pioC_clk",
  48         .pmc_mask       = 1 << AT91SAM9261_ID_PIOC,
  49         .type           = CLK_TYPE_PERIPHERAL,
  50 };
  51 static struct clk usart0_clk = {
  52         .name           = "usart0_clk",
  53         .pmc_mask       = 1 << AT91SAM9261_ID_US0,
  54         .type           = CLK_TYPE_PERIPHERAL,
  55 };
  56 static struct clk usart1_clk = {
  57         .name           = "usart1_clk",
  58         .pmc_mask       = 1 << AT91SAM9261_ID_US1,
  59         .type           = CLK_TYPE_PERIPHERAL,
  60 };
  61 static struct clk usart2_clk = {
  62         .name           = "usart2_clk",
  63         .pmc_mask       = 1 << AT91SAM9261_ID_US2,
  64         .type           = CLK_TYPE_PERIPHERAL,
  65 };
  66 static struct clk mmc_clk = {
  67         .name           = "mci_clk",
  68         .pmc_mask       = 1 << AT91SAM9261_ID_MCI,
  69         .type           = CLK_TYPE_PERIPHERAL,
  70 };
  71 static struct clk udc_clk = {
  72         .name           = "udc_clk",
  73         .pmc_mask       = 1 << AT91SAM9261_ID_UDP,
  74         .type           = CLK_TYPE_PERIPHERAL,
  75 };
  76 static struct clk twi_clk = {
  77         .name           = "twi_clk",
  78         .pmc_mask       = 1 << AT91SAM9261_ID_TWI,
  79         .type           = CLK_TYPE_PERIPHERAL,
  80 };
  81 static struct clk spi0_clk = {
  82         .name           = "spi0_clk",
  83         .pmc_mask       = 1 << AT91SAM9261_ID_SPI0,
  84         .type           = CLK_TYPE_PERIPHERAL,
  85 };
  86 static struct clk spi1_clk = {
  87         .name           = "spi1_clk",
  88         .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
  89         .type           = CLK_TYPE_PERIPHERAL,
  90 };
  91 static struct clk ssc0_clk = {
  92         .name           = "ssc0_clk",
  93         .pmc_mask       = 1 << AT91SAM9261_ID_SSC0,
  94         .type           = CLK_TYPE_PERIPHERAL,
  95 };
  96 static struct clk ssc1_clk = {
  97         .name           = "ssc1_clk",
  98         .pmc_mask       = 1 << AT91SAM9261_ID_SSC1,
  99         .type           = CLK_TYPE_PERIPHERAL,
 100 };
 101 static struct clk ssc2_clk = {
 102         .name           = "ssc2_clk",
 103         .pmc_mask       = 1 << AT91SAM9261_ID_SSC2,
 104         .type           = CLK_TYPE_PERIPHERAL,
 105 };
 106 static struct clk tc0_clk = {
 107         .name           = "tc0_clk",
 108         .pmc_mask       = 1 << AT91SAM9261_ID_TC0,
 109         .type           = CLK_TYPE_PERIPHERAL,
 110 };
 111 static struct clk tc1_clk = {
 112         .name           = "tc1_clk",
 113         .pmc_mask       = 1 << AT91SAM9261_ID_TC1,
 114         .type           = CLK_TYPE_PERIPHERAL,
 115 };
 116 static struct clk tc2_clk = {
 117         .name           = "tc2_clk",
 118         .pmc_mask       = 1 << AT91SAM9261_ID_TC2,
 119         .type           = CLK_TYPE_PERIPHERAL,
 120 };
 121 static struct clk ohci_clk = {
 122         .name           = "ohci_clk",
 123         .pmc_mask       = 1 << AT91SAM9261_ID_UHP,
 124         .type           = CLK_TYPE_PERIPHERAL,
 125 };
 126 static struct clk lcdc_clk = {
 127         .name           = "lcdc_clk",
 128         .pmc_mask       = 1 << AT91SAM9261_ID_LCDC,
 129         .type           = CLK_TYPE_PERIPHERAL,
 130 };
 131
 132 /* HClocks */
 133 static struct clk hck0 = {
 134         .name           = "hck0",
 135         .pmc_mask       = AT91_PMC_HCK0,
 136         .type           = CLK_TYPE_SYSTEM,
 137         .id             = 0,
 138 };
 139 static struct clk hck1 = {
 140         .name           = "hck1",
 141         .pmc_mask       = AT91_PMC_HCK1,
 142         .type           = CLK_TYPE_SYSTEM,
 143         .id             = 1,
 144 };
 145
 146 static struct clk *periph_clocks[] __initdata = {
 147         &pioA_clk,
 148         &pioB_clk,
 149         &pioC_clk,
 150         &usart0_clk,
 151         &usart1_clk,
 152         &usart2_clk,
 153         &mmc_clk,
 154         &udc_clk,
 155         &twi_clk,
 156         &spi0_clk,
 157         &spi1_clk,
 158         &ssc0_clk,
 159         &ssc1_clk,
 160         &ssc2_clk,
 161         &tc0_clk,
 162         &tc1_clk,
 163         &tc2_clk,
 164         &ohci_clk,
 165         &lcdc_clk,
 166         // irq0 .. irq2
 167 };
 168
 169 static struct clk_lookup periph_clocks_lookups[] = {
 170         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 171         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 172         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 173         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 174         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 175         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 176         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 177         CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
 178         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
 179         CLKDEV_CON_ID("pioA", &pioA_clk),
 180         CLKDEV_CON_ID("pioB", &pioB_clk),
 181         CLKDEV_CON_ID("pioC", &pioC_clk),
 182 };
 183
 184 static struct clk_lookup usart_clocks_lookups[] = {
 185         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 186         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 187         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 188         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 189 };
 190
 191 /*
 192  * The four programmable clocks.
 193  * You must configure pin multiplexing to bring these signals out.
 194  */
 195 static struct clk pck0 = {
 196         .name           = "pck0",
 197         .pmc_mask       = AT91_PMC_PCK0,
 198         .type           = CLK_TYPE_PROGRAMMABLE,
 199         .id             = 0,
 200 };
 201 static struct clk pck1 = {
 202         .name           = "pck1",
 203         .pmc_mask       = AT91_PMC_PCK1,
 204         .type           = CLK_TYPE_PROGRAMMABLE,
 205         .id             = 1,
 206 };
 207 static struct clk pck2 = {
 208         .name           = "pck2",
 209         .pmc_mask       = AT91_PMC_PCK2,
 210         .type           = CLK_TYPE_PROGRAMMABLE,
 211         .id             = 2,
 212 };
 213 static struct clk pck3 = {
 214         .name           = "pck3",
 215         .pmc_mask       = AT91_PMC_PCK3,
 216         .type           = CLK_TYPE_PROGRAMMABLE,
 217         .id             = 3,
 218 };
 219
 220 static void __init at91sam9261_register_clocks(void)
 221 {
 222         int i;
 223
 224         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 225                 clk_register(periph_clocks[i]);
 226
 227         clkdev_add_table(periph_clocks_lookups,
 228                          ARRAY_SIZE(periph_clocks_lookups));
 229         clkdev_add_table(usart_clocks_lookups,
 230                          ARRAY_SIZE(usart_clocks_lookups));
 231
 232         clk_register(&pck0);
 233         clk_register(&pck1);
 234         clk_register(&pck2);
 235         clk_register(&pck3);
 236
 237         clk_register(&hck0);
 238         clk_register(&hck1);
 239 }
 240
 241 static struct clk_lookup console_clock_lookup;
 242
 243 void __init at91sam9261_set_console_clock(int id)
 244 {
 245         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 246                 return;
 247
 248         console_clock_lookup.con_id = "usart";
 249         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 250         clkdev_add(&console_clock_lookup);
 251 }
 252
 253 /* --------------------------------------------------------------------
 254  *  GPIO
 255  * -------------------------------------------------------------------- */
 256
 257 static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
 258         {
 259                 .id             = AT91SAM9261_ID_PIOA,
 260                 .regbase        = AT91SAM9261_BASE_PIOA,
 261         }, {
 262                 .id             = AT91SAM9261_ID_PIOB,
 263                 .regbase        = AT91SAM9261_BASE_PIOB,
 264         }, {
 265                 .id             = AT91SAM9261_ID_PIOC,
 266                 .regbase        = AT91SAM9261_BASE_PIOC,
 267         }
 268 };
 269
 270 /* --------------------------------------------------------------------
 271  *  AT91SAM9261 processor initialization
 272  * -------------------------------------------------------------------- */
 273
 274 static void __init at91sam9261_map_io(void)
 275 {
 276         if (cpu_is_at91sam9g10())
 277                 at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
 278         else
 279                 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
 280 }
 281
 282 static void __init at91sam9261_ioremap_registers(void)
 283 {
 284         at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
 285         at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
 286         at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
 287         at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
 288         at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
 289         at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
 290 }
 291
 292 static void __init at91sam9261_initialize(void)
 293 {
 294         arm_pm_idle = at91sam9_idle;
 295         arm_pm_restart = at91sam9_alt_restart;
 296         at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
 297                         | (1 << AT91SAM9261_ID_IRQ2);
 298
 299         /* Register GPIO subsystem */
 300         at91_gpio_init(at91sam9261_gpio, 3);
 301 }
 302
 303 /* --------------------------------------------------------------------
 304  *  Interrupt initialization
 305  * -------------------------------------------------------------------- */
 306
 307 /*
 308  * The default interrupt priority levels (0 = lowest, 7 = highest).
 309  */
 310 static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
 311         7,      /* Advanced Interrupt Controller */
 312         7,      /* System Peripherals */
 313         1,      /* Parallel IO Controller A */
 314         1,      /* Parallel IO Controller B */
 315         1,      /* Parallel IO Controller C */
 316         0,
 317         5,      /* USART 0 */
 318         5,      /* USART 1 */
 319         5,      /* USART 2 */
 320         0,      /* Multimedia Card Interface */
 321         2,      /* USB Device Port */
 322         6,      /* Two-Wire Interface */
 323         5,      /* Serial Peripheral Interface 0 */
 324         5,      /* Serial Peripheral Interface 1 */
 325         4,      /* Serial Synchronous Controller 0 */
 326         4,      /* Serial Synchronous Controller 1 */
 327         4,      /* Serial Synchronous Controller 2 */
 328         0,      /* Timer Counter 0 */
 329         0,      /* Timer Counter 1 */
 330         0,      /* Timer Counter 2 */
 331         2,      /* USB Host port */
 332         3,      /* LCD Controller */
 333         0,
 334         0,
 335         0,
 336         0,
 337         0,
 338         0,
 339         0,
 340         0,      /* Advanced Interrupt Controller */
 341         0,      /* Advanced Interrupt Controller */
 342         0,      /* Advanced Interrupt Controller */
 343 };
 344
 345 struct at91_init_soc __initdata at91sam9261_soc = {
 346         .map_io = at91sam9261_map_io,
 347         .default_irq_priority = at91sam9261_default_irq_priority,
 348         .ioremap_registers = at91sam9261_ioremap_registers,
 349         .register_clocks = at91sam9261_register_clocks,
 350         .init = at91sam9261_initialize,
 351 };