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[ARM] 5572/1: at91: Support for at91sam9g45 series: core chip & board support
[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9g45_devices.c
1 /*
2 * On-Chip devices setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
14
15 #include <linux/dma-mapping.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c-gpio.h>
18
19 #include <linux/fb.h>
20 #include <video/atmel_lcdc.h>
21
22 #include <mach/board.h>
23 #include <mach/gpio.h>
24 #include <mach/at91sam9g45.h>
25 #include <mach/at91sam9g45_matrix.h>
26 #include <mach/at91sam9_smc.h>
27
28 #include "generic.h"
29
30
31 /* --------------------------------------------------------------------
32 * USB Host (OHCI)
33 * -------------------------------------------------------------------- */
34
35 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
36 static u64 ohci_dmamask = DMA_BIT_MASK(32);
37 static struct at91_usbh_data usbh_ohci_data;
38
39 static struct resource usbh_ohci_resources[] = {
40 [0] = {
41 .start = AT91SAM9G45_OHCI_BASE,
42 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = AT91SAM9G45_ID_UHPHS,
47 .end = AT91SAM9G45_ID_UHPHS,
48 .flags = IORESOURCE_IRQ,
49 },
50 };
51
52 static struct platform_device at91_usbh_ohci_device = {
53 .name = "at91_ohci",
54 .id = -1,
55 .dev = {
56 .dma_mask = &ohci_dmamask,
57 .coherent_dma_mask = DMA_BIT_MASK(32),
58 .platform_data = &usbh_ohci_data,
59 },
60 .resource = usbh_ohci_resources,
61 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
62 };
63
64 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
65 {
66 int i;
67
68 if (!data)
69 return;
70
71 /* Enable VBus control for UHP ports */
72 for (i = 0; i < data->ports; i++) {
73 if (data->vbus_pin[i])
74 at91_set_gpio_output(data->vbus_pin[i], 0);
75 }
76
77 usbh_ohci_data = *data;
78 platform_device_register(&at91_usbh_ohci_device);
79 }
80 #else
81 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
82 #endif
83
84
85 /* --------------------------------------------------------------------
86 * USB HS Device (Gadget)
87 * -------------------------------------------------------------------- */
88
89 #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
90 static struct resource usba_udc_resources[] = {
91 [0] = {
92 .start = AT91SAM9G45_UDPHS_FIFO,
93 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = AT91SAM9G45_BASE_UDPHS,
98 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
99 .flags = IORESOURCE_MEM,
100 },
101 [2] = {
102 .start = AT91SAM9G45_ID_UDPHS,
103 .end = AT91SAM9G45_ID_UDPHS,
104 .flags = IORESOURCE_IRQ,
105 },
106 };
107
108 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
109 [idx] = { \
110 .name = nam, \
111 .index = idx, \
112 .fifo_size = maxpkt, \
113 .nr_banks = maxbk, \
114 .can_dma = dma, \
115 .can_isoc = isoc, \
116 }
117
118 static struct usba_ep_data usba_udc_ep[] __initdata = {
119 EP("ep0", 0, 64, 1, 0, 0),
120 EP("ep1", 1, 1024, 2, 1, 1),
121 EP("ep2", 2, 1024, 2, 1, 1),
122 EP("ep3", 3, 1024, 3, 1, 0),
123 EP("ep4", 4, 1024, 3, 1, 0),
124 EP("ep5", 5, 1024, 3, 1, 1),
125 EP("ep6", 6, 1024, 3, 1, 1),
126 };
127
128 #undef EP
129
130 /*
131 * pdata doesn't have room for any endpoints, so we need to
132 * append room for the ones we need right after it.
133 */
134 static struct {
135 struct usba_platform_data pdata;
136 struct usba_ep_data ep[7];
137 } usba_udc_data;
138
139 static struct platform_device at91_usba_udc_device = {
140 .name = "atmel_usba_udc",
141 .id = -1,
142 .dev = {
143 .platform_data = &usba_udc_data.pdata,
144 },
145 .resource = usba_udc_resources,
146 .num_resources = ARRAY_SIZE(usba_udc_resources),
147 };
148
149 void __init at91_add_device_usba(struct usba_platform_data *data)
150 {
151 usba_udc_data.pdata.vbus_pin = -EINVAL;
152 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
153 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
154
155 if (data && data->vbus_pin > 0) {
156 at91_set_gpio_input(data->vbus_pin, 0);
157 at91_set_deglitch(data->vbus_pin, 1);
158 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
159 }
160
161 /* Pullup pin is handled internally by USB device peripheral */
162
163 /* Clocks */
164 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
165 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
166
167 platform_device_register(&at91_usba_udc_device);
168 }
169 #else
170 void __init at91_add_device_usba(struct usba_platform_data *data) {}
171 #endif
172
173
174 /* --------------------------------------------------------------------
175 * Ethernet
176 * -------------------------------------------------------------------- */
177
178 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
179 static u64 eth_dmamask = DMA_BIT_MASK(32);
180 static struct at91_eth_data eth_data;
181
182 static struct resource eth_resources[] = {
183 [0] = {
184 .start = AT91SAM9G45_BASE_EMAC,
185 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
186 .flags = IORESOURCE_MEM,
187 },
188 [1] = {
189 .start = AT91SAM9G45_ID_EMAC,
190 .end = AT91SAM9G45_ID_EMAC,
191 .flags = IORESOURCE_IRQ,
192 },
193 };
194
195 static struct platform_device at91sam9g45_eth_device = {
196 .name = "macb",
197 .id = -1,
198 .dev = {
199 .dma_mask = &eth_dmamask,
200 .coherent_dma_mask = DMA_BIT_MASK(32),
201 .platform_data = &eth_data,
202 },
203 .resource = eth_resources,
204 .num_resources = ARRAY_SIZE(eth_resources),
205 };
206
207 void __init at91_add_device_eth(struct at91_eth_data *data)
208 {
209 if (!data)
210 return;
211
212 if (data->phy_irq_pin) {
213 at91_set_gpio_input(data->phy_irq_pin, 0);
214 at91_set_deglitch(data->phy_irq_pin, 1);
215 }
216
217 /* Pins used for MII and RMII */
218 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
219 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
220 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
221 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
222 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
223 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
224 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
225 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
226 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
227 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
228
229 if (!data->is_rmii) {
230 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
231 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
232 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
233 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
234 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
235 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
236 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
237 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
238 }
239
240 eth_data = *data;
241 platform_device_register(&at91sam9g45_eth_device);
242 }
243 #else
244 void __init at91_add_device_eth(struct at91_eth_data *data) {}
245 #endif
246
247
248 /* --------------------------------------------------------------------
249 * NAND / SmartMedia
250 * -------------------------------------------------------------------- */
251
252 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
253 static struct atmel_nand_data nand_data;
254
255 #define NAND_BASE AT91_CHIPSELECT_3
256
257 static struct resource nand_resources[] = {
258 [0] = {
259 .start = NAND_BASE,
260 .end = NAND_BASE + SZ_256M - 1,
261 .flags = IORESOURCE_MEM,
262 },
263 [1] = {
264 .start = AT91_BASE_SYS + AT91_ECC,
265 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
266 .flags = IORESOURCE_MEM,
267 }
268 };
269
270 static struct platform_device at91sam9g45_nand_device = {
271 .name = "atmel_nand",
272 .id = -1,
273 .dev = {
274 .platform_data = &nand_data,
275 },
276 .resource = nand_resources,
277 .num_resources = ARRAY_SIZE(nand_resources),
278 };
279
280 void __init at91_add_device_nand(struct atmel_nand_data *data)
281 {
282 unsigned long csa;
283
284 if (!data)
285 return;
286
287 csa = at91_sys_read(AT91_MATRIX_EBICSA);
288 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
289
290 /* enable pin */
291 if (data->enable_pin)
292 at91_set_gpio_output(data->enable_pin, 1);
293
294 /* ready/busy pin */
295 if (data->rdy_pin)
296 at91_set_gpio_input(data->rdy_pin, 1);
297
298 /* card detect pin */
299 if (data->det_pin)
300 at91_set_gpio_input(data->det_pin, 1);
301
302 nand_data = *data;
303 platform_device_register(&at91sam9g45_nand_device);
304 }
305 #else
306 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
307 #endif
308
309
310 /* --------------------------------------------------------------------
311 * TWI (i2c)
312 * -------------------------------------------------------------------- */
313
314 /*
315 * Prefer the GPIO code since the TWI controller isn't robust
316 * (gets overruns and underruns under load) and can only issue
317 * repeated STARTs in one scenario (the driver doesn't yet handle them).
318 */
319 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
320 static struct i2c_gpio_platform_data pdata_i2c0 = {
321 .sda_pin = AT91_PIN_PA20,
322 .sda_is_open_drain = 1,
323 .scl_pin = AT91_PIN_PA21,
324 .scl_is_open_drain = 1,
325 .udelay = 2, /* ~100 kHz */
326 };
327
328 static struct platform_device at91sam9g45_twi0_device = {
329 .name = "i2c-gpio",
330 .id = 0,
331 .dev.platform_data = &pdata_i2c0,
332 };
333
334 static struct i2c_gpio_platform_data pdata_i2c1 = {
335 .sda_pin = AT91_PIN_PB10,
336 .sda_is_open_drain = 1,
337 .scl_pin = AT91_PIN_PB11,
338 .scl_is_open_drain = 1,
339 .udelay = 2, /* ~100 kHz */
340 };
341
342 static struct platform_device at91sam9g45_twi1_device = {
343 .name = "i2c-gpio",
344 .id = 1,
345 .dev.platform_data = &pdata_i2c1,
346 };
347
348 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
349 {
350 i2c_register_board_info(i2c_id, devices, nr_devices);
351
352 if (i2c_id == 0) {
353 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
354 at91_set_multi_drive(AT91_PIN_PA20, 1);
355
356 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
357 at91_set_multi_drive(AT91_PIN_PA21, 1);
358
359 platform_device_register(&at91sam9g45_twi0_device);
360 } else {
361 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
362 at91_set_multi_drive(AT91_PIN_PB10, 1);
363
364 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
365 at91_set_multi_drive(AT91_PIN_PB11, 1);
366
367 platform_device_register(&at91sam9g45_twi1_device);
368 }
369 }
370
371 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
372 static struct resource twi0_resources[] = {
373 [0] = {
374 .start = AT91SAM9G45_BASE_TWI0,
375 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
376 .flags = IORESOURCE_MEM,
377 },
378 [1] = {
379 .start = AT91SAM9G45_ID_TWI0,
380 .end = AT91SAM9G45_ID_TWI0,
381 .flags = IORESOURCE_IRQ,
382 },
383 };
384
385 static struct platform_device at91sam9g45_twi0_device = {
386 .name = "at91_i2c",
387 .id = 0,
388 .resource = twi0_resources,
389 .num_resources = ARRAY_SIZE(twi0_resources),
390 };
391
392 static struct resource twi1_resources[] = {
393 [0] = {
394 .start = AT91SAM9G45_BASE_TWI1,
395 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
396 .flags = IORESOURCE_MEM,
397 },
398 [1] = {
399 .start = AT91SAM9G45_ID_TWI1,
400 .end = AT91SAM9G45_ID_TWI1,
401 .flags = IORESOURCE_IRQ,
402 },
403 };
404
405 static struct platform_device at91sam9g45_twi1_device = {
406 .name = "at91_i2c",
407 .id = 1,
408 .resource = twi1_resources,
409 .num_resources = ARRAY_SIZE(twi1_resources),
410 };
411
412 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
413 {
414 i2c_register_board_info(i2c_id, devices, nr_devices);
415
416 /* pins used for TWI interface */
417 if (i2c_id == 0) {
418 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
419 at91_set_multi_drive(AT91_PIN_PA20, 1);
420
421 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
422 at91_set_multi_drive(AT91_PIN_PA21, 1);
423
424 platform_device_register(&at91sam9g45_twi0_device);
425 } else {
426 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
427 at91_set_multi_drive(AT91_PIN_PB10, 1);
428
429 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
430 at91_set_multi_drive(AT91_PIN_PB11, 1);
431
432 platform_device_register(&at91sam9g45_twi1_device);
433 }
434 }
435 #else
436 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
437 #endif
438
439
440 /* --------------------------------------------------------------------
441 * SPI
442 * -------------------------------------------------------------------- */
443
444 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
445 static u64 spi_dmamask = DMA_BIT_MASK(32);
446
447 static struct resource spi0_resources[] = {
448 [0] = {
449 .start = AT91SAM9G45_BASE_SPI0,
450 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
451 .flags = IORESOURCE_MEM,
452 },
453 [1] = {
454 .start = AT91SAM9G45_ID_SPI0,
455 .end = AT91SAM9G45_ID_SPI0,
456 .flags = IORESOURCE_IRQ,
457 },
458 };
459
460 static struct platform_device at91sam9g45_spi0_device = {
461 .name = "atmel_spi",
462 .id = 0,
463 .dev = {
464 .dma_mask = &spi_dmamask,
465 .coherent_dma_mask = DMA_BIT_MASK(32),
466 },
467 .resource = spi0_resources,
468 .num_resources = ARRAY_SIZE(spi0_resources),
469 };
470
471 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
472
473 static struct resource spi1_resources[] = {
474 [0] = {
475 .start = AT91SAM9G45_BASE_SPI1,
476 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
477 .flags = IORESOURCE_MEM,
478 },
479 [1] = {
480 .start = AT91SAM9G45_ID_SPI1,
481 .end = AT91SAM9G45_ID_SPI1,
482 .flags = IORESOURCE_IRQ,
483 },
484 };
485
486 static struct platform_device at91sam9g45_spi1_device = {
487 .name = "atmel_spi",
488 .id = 1,
489 .dev = {
490 .dma_mask = &spi_dmamask,
491 .coherent_dma_mask = DMA_BIT_MASK(32),
492 },
493 .resource = spi1_resources,
494 .num_resources = ARRAY_SIZE(spi1_resources),
495 };
496
497 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
498
499 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
500 {
501 int i;
502 unsigned long cs_pin;
503 short enable_spi0 = 0;
504 short enable_spi1 = 0;
505
506 /* Choose SPI chip-selects */
507 for (i = 0; i < nr_devices; i++) {
508 if (devices[i].controller_data)
509 cs_pin = (unsigned long) devices[i].controller_data;
510 else if (devices[i].bus_num == 0)
511 cs_pin = spi0_standard_cs[devices[i].chip_select];
512 else
513 cs_pin = spi1_standard_cs[devices[i].chip_select];
514
515 if (devices[i].bus_num == 0)
516 enable_spi0 = 1;
517 else
518 enable_spi1 = 1;
519
520 /* enable chip-select pin */
521 at91_set_gpio_output(cs_pin, 1);
522
523 /* pass chip-select pin to driver */
524 devices[i].controller_data = (void *) cs_pin;
525 }
526
527 spi_register_board_info(devices, nr_devices);
528
529 /* Configure SPI bus(es) */
530 if (enable_spi0) {
531 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
532 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
533 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
534
535 at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk");
536 platform_device_register(&at91sam9g45_spi0_device);
537 }
538 if (enable_spi1) {
539 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
540 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
541 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
542
543 at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk");
544 platform_device_register(&at91sam9g45_spi1_device);
545 }
546 }
547 #else
548 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
549 #endif
550
551
552 /* --------------------------------------------------------------------
553 * LCD Controller
554 * -------------------------------------------------------------------- */
555
556 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
557 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
558 static struct atmel_lcdfb_info lcdc_data;
559
560 static struct resource lcdc_resources[] = {
561 [0] = {
562 .start = AT91SAM9G45_LCDC_BASE,
563 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
564 .flags = IORESOURCE_MEM,
565 },
566 [1] = {
567 .start = AT91SAM9G45_ID_LCDC,
568 .end = AT91SAM9G45_ID_LCDC,
569 .flags = IORESOURCE_IRQ,
570 },
571 };
572
573 static struct platform_device at91_lcdc_device = {
574 .name = "atmel_lcdfb",
575 .id = 0,
576 .dev = {
577 .dma_mask = &lcdc_dmamask,
578 .coherent_dma_mask = DMA_BIT_MASK(32),
579 .platform_data = &lcdc_data,
580 },
581 .resource = lcdc_resources,
582 .num_resources = ARRAY_SIZE(lcdc_resources),
583 };
584
585 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
586 {
587 if (!data)
588 return;
589
590 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
591
592 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
593 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
594 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
595 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
596 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
597 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
598 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
599 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
600 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
601 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
602 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
603 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
604 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
605 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
606 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
607 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
608 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
609 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
610 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
611 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
612 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
613 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
614 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
615 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
616 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
617 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
618 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
619 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
620 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
621
622 lcdc_data = *data;
623 platform_device_register(&at91_lcdc_device);
624 }
625 #else
626 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
627 #endif
628
629
630 /* --------------------------------------------------------------------
631 * Timer/Counter block
632 * -------------------------------------------------------------------- */
633
634 #ifdef CONFIG_ATMEL_TCLIB
635 static struct resource tcb0_resources[] = {
636 [0] = {
637 .start = AT91SAM9G45_BASE_TCB0,
638 .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
639 .flags = IORESOURCE_MEM,
640 },
641 [1] = {
642 .start = AT91SAM9G45_ID_TCB,
643 .end = AT91SAM9G45_ID_TCB,
644 .flags = IORESOURCE_IRQ,
645 },
646 };
647
648 static struct platform_device at91sam9g45_tcb0_device = {
649 .name = "atmel_tcb",
650 .id = 0,
651 .resource = tcb0_resources,
652 .num_resources = ARRAY_SIZE(tcb0_resources),
653 };
654
655 /* TCB1 begins with TC3 */
656 static struct resource tcb1_resources[] = {
657 [0] = {
658 .start = AT91SAM9G45_BASE_TCB1,
659 .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
660 .flags = IORESOURCE_MEM,
661 },
662 [1] = {
663 .start = AT91SAM9G45_ID_TCB,
664 .end = AT91SAM9G45_ID_TCB,
665 .flags = IORESOURCE_IRQ,
666 },
667 };
668
669 static struct platform_device at91sam9g45_tcb1_device = {
670 .name = "atmel_tcb",
671 .id = 1,
672 .resource = tcb1_resources,
673 .num_resources = ARRAY_SIZE(tcb1_resources),
674 };
675
676 static void __init at91_add_device_tc(void)
677 {
678 /* this chip has one clock and irq for all six TC channels */
679 at91_clock_associate("tcb_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
680 platform_device_register(&at91sam9g45_tcb0_device);
681 at91_clock_associate("tcb_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
682 platform_device_register(&at91sam9g45_tcb1_device);
683 }
684 #else
685 static void __init at91_add_device_tc(void) { }
686 #endif
687
688
689 /* --------------------------------------------------------------------
690 * RTC
691 * -------------------------------------------------------------------- */
692
693 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
694 static struct platform_device at91sam9g45_rtc_device = {
695 .name = "at91_rtc",
696 .id = -1,
697 .num_resources = 0,
698 };
699
700 static void __init at91_add_device_rtc(void)
701 {
702 platform_device_register(&at91sam9g45_rtc_device);
703 }
704 #else
705 static void __init at91_add_device_rtc(void) {}
706 #endif
707
708
709 /* --------------------------------------------------------------------
710 * RTT
711 * -------------------------------------------------------------------- */
712
713 static struct resource rtt_resources[] = {
714 {
715 .start = AT91_BASE_SYS + AT91_RTT,
716 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
717 .flags = IORESOURCE_MEM,
718 }
719 };
720
721 static struct platform_device at91sam9g45_rtt_device = {
722 .name = "at91_rtt",
723 .id = 0,
724 .resource = rtt_resources,
725 .num_resources = ARRAY_SIZE(rtt_resources),
726 };
727
728 static void __init at91_add_device_rtt(void)
729 {
730 platform_device_register(&at91sam9g45_rtt_device);
731 }
732
733
734 /* --------------------------------------------------------------------
735 * Watchdog
736 * -------------------------------------------------------------------- */
737
738 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
739 static struct platform_device at91sam9g45_wdt_device = {
740 .name = "at91_wdt",
741 .id = -1,
742 .num_resources = 0,
743 };
744
745 static void __init at91_add_device_watchdog(void)
746 {
747 platform_device_register(&at91sam9g45_wdt_device);
748 }
749 #else
750 static void __init at91_add_device_watchdog(void) {}
751 #endif
752
753
754 /* --------------------------------------------------------------------
755 * PWM
756 * --------------------------------------------------------------------*/
757
758 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
759 static u32 pwm_mask;
760
761 static struct resource pwm_resources[] = {
762 [0] = {
763 .start = AT91SAM9G45_BASE_PWMC,
764 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
765 .flags = IORESOURCE_MEM,
766 },
767 [1] = {
768 .start = AT91SAM9G45_ID_PWMC,
769 .end = AT91SAM9G45_ID_PWMC,
770 .flags = IORESOURCE_IRQ,
771 },
772 };
773
774 static struct platform_device at91sam9g45_pwm0_device = {
775 .name = "atmel_pwm",
776 .id = -1,
777 .dev = {
778 .platform_data = &pwm_mask,
779 },
780 .resource = pwm_resources,
781 .num_resources = ARRAY_SIZE(pwm_resources),
782 };
783
784 void __init at91_add_device_pwm(u32 mask)
785 {
786 if (mask & (1 << AT91_PWM0))
787 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
788
789 if (mask & (1 << AT91_PWM1))
790 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
791
792 if (mask & (1 << AT91_PWM2))
793 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
794
795 if (mask & (1 << AT91_PWM3))
796 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
797
798 pwm_mask = mask;
799
800 platform_device_register(&at91sam9g45_pwm0_device);
801 }
802 #else
803 void __init at91_add_device_pwm(u32 mask) {}
804 #endif
805
806
807 /* --------------------------------------------------------------------
808 * SSC -- Synchronous Serial Controller
809 * -------------------------------------------------------------------- */
810
811 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
812 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
813
814 static struct resource ssc0_resources[] = {
815 [0] = {
816 .start = AT91SAM9G45_BASE_SSC0,
817 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
818 .flags = IORESOURCE_MEM,
819 },
820 [1] = {
821 .start = AT91SAM9G45_ID_SSC0,
822 .end = AT91SAM9G45_ID_SSC0,
823 .flags = IORESOURCE_IRQ,
824 },
825 };
826
827 static struct platform_device at91sam9g45_ssc0_device = {
828 .name = "ssc",
829 .id = 0,
830 .dev = {
831 .dma_mask = &ssc0_dmamask,
832 .coherent_dma_mask = DMA_BIT_MASK(32),
833 },
834 .resource = ssc0_resources,
835 .num_resources = ARRAY_SIZE(ssc0_resources),
836 };
837
838 static inline void configure_ssc0_pins(unsigned pins)
839 {
840 if (pins & ATMEL_SSC_TF)
841 at91_set_A_periph(AT91_PIN_PD1, 1);
842 if (pins & ATMEL_SSC_TK)
843 at91_set_A_periph(AT91_PIN_PD0, 1);
844 if (pins & ATMEL_SSC_TD)
845 at91_set_A_periph(AT91_PIN_PD2, 1);
846 if (pins & ATMEL_SSC_RD)
847 at91_set_A_periph(AT91_PIN_PD3, 1);
848 if (pins & ATMEL_SSC_RK)
849 at91_set_A_periph(AT91_PIN_PD4, 1);
850 if (pins & ATMEL_SSC_RF)
851 at91_set_A_periph(AT91_PIN_PD5, 1);
852 }
853
854 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
855
856 static struct resource ssc1_resources[] = {
857 [0] = {
858 .start = AT91SAM9G45_BASE_SSC1,
859 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
860 .flags = IORESOURCE_MEM,
861 },
862 [1] = {
863 .start = AT91SAM9G45_ID_SSC1,
864 .end = AT91SAM9G45_ID_SSC1,
865 .flags = IORESOURCE_IRQ,
866 },
867 };
868
869 static struct platform_device at91sam9g45_ssc1_device = {
870 .name = "ssc",
871 .id = 1,
872 .dev = {
873 .dma_mask = &ssc1_dmamask,
874 .coherent_dma_mask = DMA_BIT_MASK(32),
875 },
876 .resource = ssc1_resources,
877 .num_resources = ARRAY_SIZE(ssc1_resources),
878 };
879
880 static inline void configure_ssc1_pins(unsigned pins)
881 {
882 if (pins & ATMEL_SSC_TF)
883 at91_set_A_periph(AT91_PIN_PD14, 1);
884 if (pins & ATMEL_SSC_TK)
885 at91_set_A_periph(AT91_PIN_PD12, 1);
886 if (pins & ATMEL_SSC_TD)
887 at91_set_A_periph(AT91_PIN_PD10, 1);
888 if (pins & ATMEL_SSC_RD)
889 at91_set_A_periph(AT91_PIN_PD11, 1);
890 if (pins & ATMEL_SSC_RK)
891 at91_set_A_periph(AT91_PIN_PD13, 1);
892 if (pins & ATMEL_SSC_RF)
893 at91_set_A_periph(AT91_PIN_PD15, 1);
894 }
895
896 /*
897 * SSC controllers are accessed through library code, instead of any
898 * kind of all-singing/all-dancing driver. For example one could be
899 * used by a particular I2S audio codec's driver, while another one
900 * on the same system might be used by a custom data capture driver.
901 */
902 void __init at91_add_device_ssc(unsigned id, unsigned pins)
903 {
904 struct platform_device *pdev;
905
906 /*
907 * NOTE: caller is responsible for passing information matching
908 * "pins" to whatever will be using each particular controller.
909 */
910 switch (id) {
911 case AT91SAM9G45_ID_SSC0:
912 pdev = &at91sam9g45_ssc0_device;
913 configure_ssc0_pins(pins);
914 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
915 break;
916 case AT91SAM9G45_ID_SSC1:
917 pdev = &at91sam9g45_ssc1_device;
918 configure_ssc1_pins(pins);
919 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
920 break;
921 default:
922 return;
923 }
924
925 platform_device_register(pdev);
926 }
927
928 #else
929 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
930 #endif
931
932
933 /* --------------------------------------------------------------------
934 * UART
935 * -------------------------------------------------------------------- */
936
937 #if defined(CONFIG_SERIAL_ATMEL)
938 static struct resource dbgu_resources[] = {
939 [0] = {
940 .start = AT91_VA_BASE_SYS + AT91_DBGU,
941 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
942 .flags = IORESOURCE_MEM,
943 },
944 [1] = {
945 .start = AT91_ID_SYS,
946 .end = AT91_ID_SYS,
947 .flags = IORESOURCE_IRQ,
948 },
949 };
950
951 static struct atmel_uart_data dbgu_data = {
952 .use_dma_tx = 0,
953 .use_dma_rx = 0,
954 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
955 };
956
957 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
958
959 static struct platform_device at91sam9g45_dbgu_device = {
960 .name = "atmel_usart",
961 .id = 0,
962 .dev = {
963 .dma_mask = &dbgu_dmamask,
964 .coherent_dma_mask = DMA_BIT_MASK(32),
965 .platform_data = &dbgu_data,
966 },
967 .resource = dbgu_resources,
968 .num_resources = ARRAY_SIZE(dbgu_resources),
969 };
970
971 static inline void configure_dbgu_pins(void)
972 {
973 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
974 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
975 }
976
977 static struct resource uart0_resources[] = {
978 [0] = {
979 .start = AT91SAM9G45_BASE_US0,
980 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
981 .flags = IORESOURCE_MEM,
982 },
983 [1] = {
984 .start = AT91SAM9G45_ID_US0,
985 .end = AT91SAM9G45_ID_US0,
986 .flags = IORESOURCE_IRQ,
987 },
988 };
989
990 static struct atmel_uart_data uart0_data = {
991 .use_dma_tx = 1,
992 .use_dma_rx = 1,
993 };
994
995 static u64 uart0_dmamask = DMA_BIT_MASK(32);
996
997 static struct platform_device at91sam9g45_uart0_device = {
998 .name = "atmel_usart",
999 .id = 1,
1000 .dev = {
1001 .dma_mask = &uart0_dmamask,
1002 .coherent_dma_mask = DMA_BIT_MASK(32),
1003 .platform_data = &uart0_data,
1004 },
1005 .resource = uart0_resources,
1006 .num_resources = ARRAY_SIZE(uart0_resources),
1007 };
1008
1009 static inline void configure_usart0_pins(unsigned pins)
1010 {
1011 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1012 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1013
1014 if (pins & ATMEL_UART_RTS)
1015 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1016 if (pins & ATMEL_UART_CTS)
1017 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1018 }
1019
1020 static struct resource uart1_resources[] = {
1021 [0] = {
1022 .start = AT91SAM9G45_BASE_US1,
1023 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1024 .flags = IORESOURCE_MEM,
1025 },
1026 [1] = {
1027 .start = AT91SAM9G45_ID_US1,
1028 .end = AT91SAM9G45_ID_US1,
1029 .flags = IORESOURCE_IRQ,
1030 },
1031 };
1032
1033 static struct atmel_uart_data uart1_data = {
1034 .use_dma_tx = 1,
1035 .use_dma_rx = 1,
1036 };
1037
1038 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1039
1040 static struct platform_device at91sam9g45_uart1_device = {
1041 .name = "atmel_usart",
1042 .id = 2,
1043 .dev = {
1044 .dma_mask = &uart1_dmamask,
1045 .coherent_dma_mask = DMA_BIT_MASK(32),
1046 .platform_data = &uart1_data,
1047 },
1048 .resource = uart1_resources,
1049 .num_resources = ARRAY_SIZE(uart1_resources),
1050 };
1051
1052 static inline void configure_usart1_pins(unsigned pins)
1053 {
1054 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1055 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1056
1057 if (pins & ATMEL_UART_RTS)
1058 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1059 if (pins & ATMEL_UART_CTS)
1060 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1061 }
1062
1063 static struct resource uart2_resources[] = {
1064 [0] = {
1065 .start = AT91SAM9G45_BASE_US2,
1066 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1067 .flags = IORESOURCE_MEM,
1068 },
1069 [1] = {
1070 .start = AT91SAM9G45_ID_US2,
1071 .end = AT91SAM9G45_ID_US2,
1072 .flags = IORESOURCE_IRQ,
1073 },
1074 };
1075
1076 static struct atmel_uart_data uart2_data = {
1077 .use_dma_tx = 1,
1078 .use_dma_rx = 1,
1079 };
1080
1081 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1082
1083 static struct platform_device at91sam9g45_uart2_device = {
1084 .name = "atmel_usart",
1085 .id = 3,
1086 .dev = {
1087 .dma_mask = &uart2_dmamask,
1088 .coherent_dma_mask = DMA_BIT_MASK(32),
1089 .platform_data = &uart2_data,
1090 },
1091 .resource = uart2_resources,
1092 .num_resources = ARRAY_SIZE(uart2_resources),
1093 };
1094
1095 static inline void configure_usart2_pins(unsigned pins)
1096 {
1097 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1098 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1099
1100 if (pins & ATMEL_UART_RTS)
1101 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1102 if (pins & ATMEL_UART_CTS)
1103 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1104 }
1105
1106 static struct resource uart3_resources[] = {
1107 [0] = {
1108 .start = AT91SAM9G45_BASE_US3,
1109 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1110 .flags = IORESOURCE_MEM,
1111 },
1112 [1] = {
1113 .start = AT91SAM9G45_ID_US3,
1114 .end = AT91SAM9G45_ID_US3,
1115 .flags = IORESOURCE_IRQ,
1116 },
1117 };
1118
1119 static struct atmel_uart_data uart3_data = {
1120 .use_dma_tx = 1,
1121 .use_dma_rx = 1,
1122 };
1123
1124 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1125
1126 static struct platform_device at91sam9g45_uart3_device = {
1127 .name = "atmel_usart",
1128 .id = 4,
1129 .dev = {
1130 .dma_mask = &uart3_dmamask,
1131 .coherent_dma_mask = DMA_BIT_MASK(32),
1132 .platform_data = &uart3_data,
1133 },
1134 .resource = uart3_resources,
1135 .num_resources = ARRAY_SIZE(uart3_resources),
1136 };
1137
1138 static inline void configure_usart3_pins(unsigned pins)
1139 {
1140 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1141 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1142
1143 if (pins & ATMEL_UART_RTS)
1144 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1145 if (pins & ATMEL_UART_CTS)
1146 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1147 }
1148
1149 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1150 struct platform_device *atmel_default_console_device; /* the serial console device */
1151
1152 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1153 {
1154 struct platform_device *pdev;
1155
1156 switch (id) {
1157 case 0: /* DBGU */
1158 pdev = &at91sam9g45_dbgu_device;
1159 configure_dbgu_pins();
1160 at91_clock_associate("mck", &pdev->dev, "usart");
1161 break;
1162 case AT91SAM9G45_ID_US0:
1163 pdev = &at91sam9g45_uart0_device;
1164 configure_usart0_pins(pins);
1165 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1166 break;
1167 case AT91SAM9G45_ID_US1:
1168 pdev = &at91sam9g45_uart1_device;
1169 configure_usart1_pins(pins);
1170 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1171 break;
1172 case AT91SAM9G45_ID_US2:
1173 pdev = &at91sam9g45_uart2_device;
1174 configure_usart2_pins(pins);
1175 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1176 break;
1177 case AT91SAM9G45_ID_US3:
1178 pdev = &at91sam9g45_uart3_device;
1179 configure_usart3_pins(pins);
1180 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1181 break;
1182 default:
1183 return;
1184 }
1185 pdev->id = portnr; /* update to mapped ID */
1186
1187 if (portnr < ATMEL_MAX_UART)
1188 at91_uarts[portnr] = pdev;
1189 }
1190
1191 void __init at91_set_serial_console(unsigned portnr)
1192 {
1193 if (portnr < ATMEL_MAX_UART)
1194 atmel_default_console_device = at91_uarts[portnr];
1195 }
1196
1197 void __init at91_add_device_serial(void)
1198 {
1199 int i;
1200
1201 for (i = 0; i < ATMEL_MAX_UART; i++) {
1202 if (at91_uarts[i])
1203 platform_device_register(at91_uarts[i]);
1204 }
1205
1206 if (!atmel_default_console_device)
1207 printk(KERN_INFO "AT91: No default serial console defined.\n");
1208 }
1209 #else
1210 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1211 void __init at91_set_serial_console(unsigned portnr) {}
1212 void __init at91_add_device_serial(void) {}
1213 #endif
1214
1215
1216 /* -------------------------------------------------------------------- */
1217 /*
1218 * These devices are always present and don't need any board-specific
1219 * setup.
1220 */
1221 static int __init at91_add_standard_devices(void)
1222 {
1223 at91_add_device_rtc();
1224 at91_add_device_rtt();
1225 at91_add_device_watchdog();
1226 at91_add_device_tc();
1227 return 0;
1228 }
1229
1230 arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
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