arch/arm/mach-at91/at91sam9n12.c

   1 /*
   2  * SoC specific setup code for the AT91SAM9N12
   3  *
   4  * Copyright (C) 2012 Atmel Corporation.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/clk/at91_pmc.h>
  12
  13 #include <asm/irq.h>
  14 #include <asm/mach/arch.h>
  15 #include <asm/mach/map.h>
  16 #include <mach/at91sam9n12.h>
  17 #include <mach/cpu.h>
  18
  19 #include "board.h"
  20 #include "soc.h"
  21 #include "generic.h"
  22 #include "sam9_smc.h"
  23
  24 #if defined(CONFIG_OLD_CLK_AT91)
  25 #include "clock.h"
  26 /* --------------------------------------------------------------------
  27  *  Clocks
  28  * -------------------------------------------------------------------- */
  29
  30 /*
  31  * The peripheral clocks.
  32  */
  33 static struct clk pioAB_clk = {
  34         .name           = "pioAB_clk",
  35         .pmc_mask       = 1 << AT91SAM9N12_ID_PIOAB,
  36         .type           = CLK_TYPE_PERIPHERAL,
  37 };
  38 static struct clk pioCD_clk = {
  39         .name           = "pioCD_clk",
  40         .pmc_mask       = 1 << AT91SAM9N12_ID_PIOCD,
  41         .type           = CLK_TYPE_PERIPHERAL,
  42 };
  43 static struct clk usart0_clk = {
  44         .name           = "usart0_clk",
  45         .pmc_mask       = 1 << AT91SAM9N12_ID_USART0,
  46         .type           = CLK_TYPE_PERIPHERAL,
  47 };
  48 static struct clk usart1_clk = {
  49         .name           = "usart1_clk",
  50         .pmc_mask       = 1 << AT91SAM9N12_ID_USART1,
  51         .type           = CLK_TYPE_PERIPHERAL,
  52 };
  53 static struct clk usart2_clk = {
  54         .name           = "usart2_clk",
  55         .pmc_mask       = 1 << AT91SAM9N12_ID_USART2,
  56         .type           = CLK_TYPE_PERIPHERAL,
  57 };
  58 static struct clk usart3_clk = {
  59         .name           = "usart3_clk",
  60         .pmc_mask       = 1 << AT91SAM9N12_ID_USART3,
  61         .type           = CLK_TYPE_PERIPHERAL,
  62 };
  63 static struct clk twi0_clk = {
  64         .name           = "twi0_clk",
  65         .pmc_mask       = 1 << AT91SAM9N12_ID_TWI0,
  66         .type           = CLK_TYPE_PERIPHERAL,
  67 };
  68 static struct clk twi1_clk = {
  69         .name           = "twi1_clk",
  70         .pmc_mask       = 1 << AT91SAM9N12_ID_TWI1,
  71         .type           = CLK_TYPE_PERIPHERAL,
  72 };
  73 static struct clk mmc_clk = {
  74         .name           = "mci_clk",
  75         .pmc_mask       = 1 << AT91SAM9N12_ID_MCI,
  76         .type           = CLK_TYPE_PERIPHERAL,
  77 };
  78 static struct clk spi0_clk = {
  79         .name           = "spi0_clk",
  80         .pmc_mask       = 1 << AT91SAM9N12_ID_SPI0,
  81         .type           = CLK_TYPE_PERIPHERAL,
  82 };
  83 static struct clk spi1_clk = {
  84         .name           = "spi1_clk",
  85         .pmc_mask       = 1 << AT91SAM9N12_ID_SPI1,
  86         .type           = CLK_TYPE_PERIPHERAL,
  87 };
  88 static struct clk uart0_clk = {
  89         .name           = "uart0_clk",
  90         .pmc_mask       = 1 << AT91SAM9N12_ID_UART0,
  91         .type           = CLK_TYPE_PERIPHERAL,
  92 };
  93 static struct clk uart1_clk = {
  94         .name           = "uart1_clk",
  95         .pmc_mask       = 1 << AT91SAM9N12_ID_UART1,
  96         .type           = CLK_TYPE_PERIPHERAL,
  97 };
  98 static struct clk tcb_clk = {
  99         .name           = "tcb_clk",
 100         .pmc_mask       = 1 << AT91SAM9N12_ID_TCB,
 101         .type           = CLK_TYPE_PERIPHERAL,
 102 };
 103 static struct clk pwm_clk = {
 104         .name           = "pwm_clk",
 105         .pmc_mask       = 1 << AT91SAM9N12_ID_PWM,
 106         .type           = CLK_TYPE_PERIPHERAL,
 107 };
 108 static struct clk adc_clk = {
 109         .name           = "adc_clk",
 110         .pmc_mask       = 1 << AT91SAM9N12_ID_ADC,
 111         .type   = CLK_TYPE_PERIPHERAL,
 112 };
 113 static struct clk dma_clk = {
 114         .name           = "dma_clk",
 115         .pmc_mask       = 1 << AT91SAM9N12_ID_DMA,
 116         .type   = CLK_TYPE_PERIPHERAL,
 117 };
 118 static struct clk uhp_clk = {
 119         .name           = "uhp",
 120         .pmc_mask       = 1 << AT91SAM9N12_ID_UHP,
 121         .type           = CLK_TYPE_PERIPHERAL,
 122 };
 123 static struct clk udp_clk = {
 124         .name           = "udp_clk",
 125         .pmc_mask       = 1 << AT91SAM9N12_ID_UDP,
 126         .type           = CLK_TYPE_PERIPHERAL,
 127 };
 128 static struct clk lcdc_clk = {
 129         .name           = "lcdc_clk",
 130         .pmc_mask       = 1 << AT91SAM9N12_ID_LCDC,
 131         .type           = CLK_TYPE_PERIPHERAL,
 132 };
 133 static struct clk ssc_clk = {
 134         .name           = "ssc_clk",
 135         .pmc_mask       = 1 << AT91SAM9N12_ID_SSC,
 136         .type           = CLK_TYPE_PERIPHERAL,
 137 };
 138
 139 static struct clk *periph_clocks[] __initdata = {
 140         &pioAB_clk,
 141         &pioCD_clk,
 142         &usart0_clk,
 143         &usart1_clk,
 144         &usart2_clk,
 145         &usart3_clk,
 146         &twi0_clk,
 147         &twi1_clk,
 148         &mmc_clk,
 149         &spi0_clk,
 150         &spi1_clk,
 151         &lcdc_clk,
 152         &uart0_clk,
 153         &uart1_clk,
 154         &tcb_clk,
 155         &pwm_clk,
 156         &adc_clk,
 157         &dma_clk,
 158         &uhp_clk,
 159         &udp_clk,
 160         &ssc_clk,
 161 };
 162
 163 static struct clk_lookup periph_clocks_lookups[] = {
 164         /* lookup table for DT entries */
 165         CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 166         CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
 167         CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
 168         CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
 169         CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
 170         CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
 171         CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
 172         CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk),
 173         CLKDEV_CON_DEV_ID(NULL, "f0010000.ssc", &ssc_clk),
 174         CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
 175         CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
 176         CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
 177         CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
 178         CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
 179         CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
 180         CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
 181         CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
 182         CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
 183         /* additional fake clock for macb_hclk */
 184         CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
 185         CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
 186         CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
 187 };
 188
 189 /*
 190  * The two programmable clocks.
 191  * You must configure pin multiplexing to bring these signals out.
 192  */
 193 static struct clk pck0 = {
 194         .name           = "pck0",
 195         .pmc_mask       = AT91_PMC_PCK0,
 196         .type           = CLK_TYPE_PROGRAMMABLE,
 197         .id             = 0,
 198 };
 199 static struct clk pck1 = {
 200         .name           = "pck1",
 201         .pmc_mask       = AT91_PMC_PCK1,
 202         .type           = CLK_TYPE_PROGRAMMABLE,
 203         .id             = 1,
 204 };
 205
 206 static void __init at91sam9n12_register_clocks(void)
 207 {
 208         int i;
 209
 210         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 211                 clk_register(periph_clocks[i]);
 212         clk_register(&pck0);
 213         clk_register(&pck1);
 214
 215         clkdev_add_table(periph_clocks_lookups,
 216                          ARRAY_SIZE(periph_clocks_lookups));
 217
 218 }
 219 #else
 220 #define at91sam9n12_register_clocks NULL
 221 #endif
 222
 223 /* --------------------------------------------------------------------
 224  *  AT91SAM9N12 processor initialization
 225  * -------------------------------------------------------------------- */
 226
 227 static void __init at91sam9n12_map_io(void)
 228 {
 229         at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
 230 }
 231
 232 static void __init at91sam9n12_initialize(void)
 233 {
 234         at91_sysirq_mask_rtc(AT91SAM9N12_BASE_RTC);
 235 }
 236
 237 AT91_SOC_START(at91sam9n12)
 238         .map_io = at91sam9n12_map_io,
 239         .register_clocks = at91sam9n12_register_clocks,
 240         .init = at91sam9n12_initialize,
 241 AT91_SOC_END