2 * Copyright (C) 2007 Atmel Corporation
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
9 #include <asm/mach/arch.h>
10 #include <asm/mach/map.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/platform_device.h>
14 #include <linux/i2c-gpio.h>
17 #include <video/atmel_lcdc.h>
19 #include <asm/arch/board.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/at91sam9rl.h>
22 #include <asm/arch/at91sam9rl_matrix.h>
23 #include <asm/arch/at91sam9_smc.h>
28 /* --------------------------------------------------------------------
30 * -------------------------------------------------------------------- */
32 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
33 static u64 mmc_dmamask
= DMA_BIT_MASK(32);
34 static struct at91_mmc_data mmc_data
;
36 static struct resource mmc_resources
[] = {
38 .start
= AT91SAM9RL_BASE_MCI
,
39 .end
= AT91SAM9RL_BASE_MCI
+ SZ_16K
- 1,
40 .flags
= IORESOURCE_MEM
,
43 .start
= AT91SAM9RL_ID_MCI
,
44 .end
= AT91SAM9RL_ID_MCI
,
45 .flags
= IORESOURCE_IRQ
,
49 static struct platform_device at91sam9rl_mmc_device
= {
53 .dma_mask
= &mmc_dmamask
,
54 .coherent_dma_mask
= DMA_BIT_MASK(32),
55 .platform_data
= &mmc_data
,
57 .resource
= mmc_resources
,
58 .num_resources
= ARRAY_SIZE(mmc_resources
),
61 void __init
at91_add_device_mmc(short mmc_id
, struct at91_mmc_data
*data
)
68 at91_set_gpio_input(data
->det_pin
, 1);
69 at91_set_deglitch(data
->det_pin
, 1);
72 at91_set_gpio_input(data
->wp_pin
, 1);
74 at91_set_gpio_output(data
->vcc_pin
, 0);
77 at91_set_A_periph(AT91_PIN_PA2
, 0);
80 at91_set_A_periph(AT91_PIN_PA1
, 1);
82 /* DAT0, maybe DAT1..DAT3 */
83 at91_set_A_periph(AT91_PIN_PA0
, 1);
85 at91_set_A_periph(AT91_PIN_PA3
, 1);
86 at91_set_A_periph(AT91_PIN_PA4
, 1);
87 at91_set_A_periph(AT91_PIN_PA5
, 1);
91 platform_device_register(&at91sam9rl_mmc_device
);
94 void __init
at91_add_device_mmc(short mmc_id
, struct at91_mmc_data
*data
) {}
98 /* --------------------------------------------------------------------
100 * -------------------------------------------------------------------- */
102 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
103 static struct at91_nand_data nand_data
;
105 #define NAND_BASE AT91_CHIPSELECT_3
107 static struct resource nand_resources
[] = {
110 .end
= NAND_BASE
+ SZ_256M
- 1,
111 .flags
= IORESOURCE_MEM
,
114 .start
= AT91_BASE_SYS
+ AT91_ECC
,
115 .end
= AT91_BASE_SYS
+ AT91_ECC
+ SZ_512
- 1,
116 .flags
= IORESOURCE_MEM
,
120 static struct platform_device at91_nand_device
= {
124 .platform_data
= &nand_data
,
126 .resource
= nand_resources
,
127 .num_resources
= ARRAY_SIZE(nand_resources
),
130 void __init
at91_add_device_nand(struct at91_nand_data
*data
)
137 csa
= at91_sys_read(AT91_MATRIX_EBICSA
);
138 at91_sys_write(AT91_MATRIX_EBICSA
, csa
| AT91_MATRIX_CS3A_SMC_SMARTMEDIA
);
140 /* set the bus interface characteristics */
141 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
142 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
144 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
145 | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
147 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
149 at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8
| AT91_SMC_READMODE
| AT91_SMC_WRITEMODE
| AT91_SMC_EXNWMODE_DISABLE
| AT91_SMC_TDF_(1));
152 if (data
->enable_pin
)
153 at91_set_gpio_output(data
->enable_pin
, 1);
157 at91_set_gpio_input(data
->rdy_pin
, 1);
159 /* card detect pin */
161 at91_set_gpio_input(data
->det_pin
, 1);
163 at91_set_A_periph(AT91_PIN_PB4
, 0); /* NANDOE */
164 at91_set_A_periph(AT91_PIN_PB5
, 0); /* NANDWE */
167 platform_device_register(&at91_nand_device
);
171 void __init
at91_add_device_nand(struct at91_nand_data
*data
) {}
175 /* --------------------------------------------------------------------
177 * -------------------------------------------------------------------- */
180 * Prefer the GPIO code since the TWI controller isn't robust
181 * (gets overruns and underruns under load) and can only issue
182 * repeated STARTs in one scenario (the driver doesn't yet handle them).
184 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
186 static struct i2c_gpio_platform_data pdata
= {
187 .sda_pin
= AT91_PIN_PA23
,
188 .sda_is_open_drain
= 1,
189 .scl_pin
= AT91_PIN_PA24
,
190 .scl_is_open_drain
= 1,
191 .udelay
= 2, /* ~100 kHz */
194 static struct platform_device at91sam9rl_twi_device
= {
197 .dev
.platform_data
= &pdata
,
200 void __init
at91_add_device_i2c(struct i2c_board_info
*devices
, int nr_devices
)
202 at91_set_GPIO_periph(AT91_PIN_PA23
, 1); /* TWD (SDA) */
203 at91_set_multi_drive(AT91_PIN_PA23
, 1);
205 at91_set_GPIO_periph(AT91_PIN_PA24
, 1); /* TWCK (SCL) */
206 at91_set_multi_drive(AT91_PIN_PA24
, 1);
208 i2c_register_board_info(0, devices
, nr_devices
);
209 platform_device_register(&at91sam9rl_twi_device
);
212 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
214 static struct resource twi_resources
[] = {
216 .start
= AT91SAM9RL_BASE_TWI0
,
217 .end
= AT91SAM9RL_BASE_TWI0
+ SZ_16K
- 1,
218 .flags
= IORESOURCE_MEM
,
221 .start
= AT91SAM9RL_ID_TWI0
,
222 .end
= AT91SAM9RL_ID_TWI0
,
223 .flags
= IORESOURCE_IRQ
,
227 static struct platform_device at91sam9rl_twi_device
= {
230 .resource
= twi_resources
,
231 .num_resources
= ARRAY_SIZE(twi_resources
),
234 void __init
at91_add_device_i2c(struct i2c_board_info
*devices
, int nr_devices
)
236 /* pins used for TWI interface */
237 at91_set_A_periph(AT91_PIN_PA23
, 0); /* TWD */
238 at91_set_multi_drive(AT91_PIN_PA23
, 1);
240 at91_set_A_periph(AT91_PIN_PA24
, 0); /* TWCK */
241 at91_set_multi_drive(AT91_PIN_PA24
, 1);
243 i2c_register_board_info(0, devices
, nr_devices
);
244 platform_device_register(&at91sam9rl_twi_device
);
247 void __init
at91_add_device_i2c(struct i2c_board_info
*devices
, int nr_devices
) {}
251 /* --------------------------------------------------------------------
253 * -------------------------------------------------------------------- */
255 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
256 static u64 spi_dmamask
= DMA_BIT_MASK(32);
258 static struct resource spi_resources
[] = {
260 .start
= AT91SAM9RL_BASE_SPI
,
261 .end
= AT91SAM9RL_BASE_SPI
+ SZ_16K
- 1,
262 .flags
= IORESOURCE_MEM
,
265 .start
= AT91SAM9RL_ID_SPI
,
266 .end
= AT91SAM9RL_ID_SPI
,
267 .flags
= IORESOURCE_IRQ
,
271 static struct platform_device at91sam9rl_spi_device
= {
275 .dma_mask
= &spi_dmamask
,
276 .coherent_dma_mask
= DMA_BIT_MASK(32),
278 .resource
= spi_resources
,
279 .num_resources
= ARRAY_SIZE(spi_resources
),
282 static const unsigned spi_standard_cs
[4] = { AT91_PIN_PA28
, AT91_PIN_PB7
, AT91_PIN_PD8
, AT91_PIN_PD9
};
285 void __init
at91_add_device_spi(struct spi_board_info
*devices
, int nr_devices
)
288 unsigned long cs_pin
;
290 at91_set_A_periph(AT91_PIN_PA25
, 0); /* MISO */
291 at91_set_A_periph(AT91_PIN_PA26
, 0); /* MOSI */
292 at91_set_A_periph(AT91_PIN_PA27
, 0); /* SPCK */
294 /* Enable SPI chip-selects */
295 for (i
= 0; i
< nr_devices
; i
++) {
296 if (devices
[i
].controller_data
)
297 cs_pin
= (unsigned long) devices
[i
].controller_data
;
299 cs_pin
= spi_standard_cs
[devices
[i
].chip_select
];
301 /* enable chip-select pin */
302 at91_set_gpio_output(cs_pin
, 1);
304 /* pass chip-select pin to driver */
305 devices
[i
].controller_data
= (void *) cs_pin
;
308 spi_register_board_info(devices
, nr_devices
);
309 platform_device_register(&at91sam9rl_spi_device
);
312 void __init
at91_add_device_spi(struct spi_board_info
*devices
, int nr_devices
) {}
316 /* --------------------------------------------------------------------
318 * -------------------------------------------------------------------- */
320 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
321 static u64 lcdc_dmamask
= DMA_BIT_MASK(32);
322 static struct atmel_lcdfb_info lcdc_data
;
324 static struct resource lcdc_resources
[] = {
326 .start
= AT91SAM9RL_LCDC_BASE
,
327 .end
= AT91SAM9RL_LCDC_BASE
+ SZ_4K
- 1,
328 .flags
= IORESOURCE_MEM
,
331 .start
= AT91SAM9RL_ID_LCDC
,
332 .end
= AT91SAM9RL_ID_LCDC
,
333 .flags
= IORESOURCE_IRQ
,
335 #if defined(CONFIG_FB_INTSRAM)
337 .start
= AT91SAM9RL_SRAM_BASE
,
338 .end
= AT91SAM9RL_SRAM_BASE
+ AT91SAM9RL_SRAM_SIZE
- 1,
339 .flags
= IORESOURCE_MEM
,
344 static struct platform_device at91_lcdc_device
= {
345 .name
= "atmel_lcdfb",
348 .dma_mask
= &lcdc_dmamask
,
349 .coherent_dma_mask
= DMA_BIT_MASK(32),
350 .platform_data
= &lcdc_data
,
352 .resource
= lcdc_resources
,
353 .num_resources
= ARRAY_SIZE(lcdc_resources
),
356 void __init
at91_add_device_lcdc(struct atmel_lcdfb_info
*data
)
362 at91_set_B_periph(AT91_PIN_PC1
, 0); /* LCDPWR */
363 at91_set_A_periph(AT91_PIN_PC5
, 0); /* LCDHSYNC */
364 at91_set_A_periph(AT91_PIN_PC6
, 0); /* LCDDOTCK */
365 at91_set_A_periph(AT91_PIN_PC7
, 0); /* LCDDEN */
366 at91_set_A_periph(AT91_PIN_PC3
, 0); /* LCDCC */
367 at91_set_B_periph(AT91_PIN_PC9
, 0); /* LCDD3 */
368 at91_set_B_periph(AT91_PIN_PC10
, 0); /* LCDD4 */
369 at91_set_B_periph(AT91_PIN_PC11
, 0); /* LCDD5 */
370 at91_set_B_periph(AT91_PIN_PC12
, 0); /* LCDD6 */
371 at91_set_B_periph(AT91_PIN_PC13
, 0); /* LCDD7 */
372 at91_set_B_periph(AT91_PIN_PC15
, 0); /* LCDD11 */
373 at91_set_B_periph(AT91_PIN_PC16
, 0); /* LCDD12 */
374 at91_set_B_periph(AT91_PIN_PC17
, 0); /* LCDD13 */
375 at91_set_B_periph(AT91_PIN_PC18
, 0); /* LCDD14 */
376 at91_set_B_periph(AT91_PIN_PC19
, 0); /* LCDD15 */
377 at91_set_B_periph(AT91_PIN_PC20
, 0); /* LCDD18 */
378 at91_set_B_periph(AT91_PIN_PC21
, 0); /* LCDD19 */
379 at91_set_B_periph(AT91_PIN_PC22
, 0); /* LCDD20 */
380 at91_set_B_periph(AT91_PIN_PC23
, 0); /* LCDD21 */
381 at91_set_B_periph(AT91_PIN_PC24
, 0); /* LCDD22 */
382 at91_set_B_periph(AT91_PIN_PC25
, 0); /* LCDD23 */
384 #ifdef CONFIG_FB_INTSRAM
387 struct resource
*fb_res
= &lcdc_resources
[2];
388 size_t fb_len
= fb_res
->end
- fb_res
->start
+ 1;
390 fb
= ioremap_writecombine(fb_res
->start
, fb_len
);
392 memset(fb
, 0, fb_len
);
399 platform_device_register(&at91_lcdc_device
);
402 void __init
at91_add_device_lcdc(struct atmel_lcdfb_info
*data
) {}
406 /* --------------------------------------------------------------------
407 * Timer/Counter block
408 * -------------------------------------------------------------------- */
410 #ifdef CONFIG_ATMEL_TCLIB
412 static struct resource tcb_resources
[] = {
414 .start
= AT91SAM9RL_BASE_TCB0
,
415 .end
= AT91SAM9RL_BASE_TCB0
+ SZ_16K
- 1,
416 .flags
= IORESOURCE_MEM
,
419 .start
= AT91SAM9RL_ID_TC0
,
420 .end
= AT91SAM9RL_ID_TC0
,
421 .flags
= IORESOURCE_IRQ
,
424 .start
= AT91SAM9RL_ID_TC1
,
425 .end
= AT91SAM9RL_ID_TC1
,
426 .flags
= IORESOURCE_IRQ
,
429 .start
= AT91SAM9RL_ID_TC2
,
430 .end
= AT91SAM9RL_ID_TC2
,
431 .flags
= IORESOURCE_IRQ
,
435 static struct platform_device at91sam9rl_tcb_device
= {
438 .resource
= tcb_resources
,
439 .num_resources
= ARRAY_SIZE(tcb_resources
),
442 static void __init
at91_add_device_tc(void)
444 /* this chip has a separate clock and irq for each TC channel */
445 at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device
.dev
, "t0_clk");
446 at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device
.dev
, "t1_clk");
447 at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device
.dev
, "t2_clk");
448 platform_device_register(&at91sam9rl_tcb_device
);
451 static void __init
at91_add_device_tc(void) { }
455 /* --------------------------------------------------------------------
457 * -------------------------------------------------------------------- */
459 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
460 static struct platform_device at91sam9rl_rtc_device
= {
466 static void __init
at91_add_device_rtc(void)
468 platform_device_register(&at91sam9rl_rtc_device
);
471 static void __init
at91_add_device_rtc(void) {}
475 /* --------------------------------------------------------------------
477 * -------------------------------------------------------------------- */
479 static struct resource rtt_resources
[] = {
481 .start
= AT91_BASE_SYS
+ AT91_RTT
,
482 .end
= AT91_BASE_SYS
+ AT91_RTT
+ SZ_16
- 1,
483 .flags
= IORESOURCE_MEM
,
487 static struct platform_device at91sam9rl_rtt_device
= {
490 .resource
= rtt_resources
,
491 .num_resources
= ARRAY_SIZE(rtt_resources
),
494 static void __init
at91_add_device_rtt(void)
496 platform_device_register(&at91sam9rl_rtt_device
);
500 /* --------------------------------------------------------------------
502 * -------------------------------------------------------------------- */
504 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
505 static struct platform_device at91sam9rl_wdt_device
= {
511 static void __init
at91_add_device_watchdog(void)
513 platform_device_register(&at91sam9rl_wdt_device
);
516 static void __init
at91_add_device_watchdog(void) {}
520 /* --------------------------------------------------------------------
521 * SSC -- Synchronous Serial Controller
522 * -------------------------------------------------------------------- */
524 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
525 static u64 ssc0_dmamask
= DMA_BIT_MASK(32);
527 static struct resource ssc0_resources
[] = {
529 .start
= AT91SAM9RL_BASE_SSC0
,
530 .end
= AT91SAM9RL_BASE_SSC0
+ SZ_16K
- 1,
531 .flags
= IORESOURCE_MEM
,
534 .start
= AT91SAM9RL_ID_SSC0
,
535 .end
= AT91SAM9RL_ID_SSC0
,
536 .flags
= IORESOURCE_IRQ
,
540 static struct platform_device at91sam9rl_ssc0_device
= {
544 .dma_mask
= &ssc0_dmamask
,
545 .coherent_dma_mask
= DMA_BIT_MASK(32),
547 .resource
= ssc0_resources
,
548 .num_resources
= ARRAY_SIZE(ssc0_resources
),
551 static inline void configure_ssc0_pins(unsigned pins
)
553 if (pins
& ATMEL_SSC_TF
)
554 at91_set_A_periph(AT91_PIN_PC0
, 1);
555 if (pins
& ATMEL_SSC_TK
)
556 at91_set_A_periph(AT91_PIN_PC1
, 1);
557 if (pins
& ATMEL_SSC_TD
)
558 at91_set_A_periph(AT91_PIN_PA15
, 1);
559 if (pins
& ATMEL_SSC_RD
)
560 at91_set_A_periph(AT91_PIN_PA16
, 1);
561 if (pins
& ATMEL_SSC_RK
)
562 at91_set_B_periph(AT91_PIN_PA10
, 1);
563 if (pins
& ATMEL_SSC_RF
)
564 at91_set_B_periph(AT91_PIN_PA22
, 1);
567 static u64 ssc1_dmamask
= DMA_BIT_MASK(32);
569 static struct resource ssc1_resources
[] = {
571 .start
= AT91SAM9RL_BASE_SSC1
,
572 .end
= AT91SAM9RL_BASE_SSC1
+ SZ_16K
- 1,
573 .flags
= IORESOURCE_MEM
,
576 .start
= AT91SAM9RL_ID_SSC1
,
577 .end
= AT91SAM9RL_ID_SSC1
,
578 .flags
= IORESOURCE_IRQ
,
582 static struct platform_device at91sam9rl_ssc1_device
= {
586 .dma_mask
= &ssc1_dmamask
,
587 .coherent_dma_mask
= DMA_BIT_MASK(32),
589 .resource
= ssc1_resources
,
590 .num_resources
= ARRAY_SIZE(ssc1_resources
),
593 static inline void configure_ssc1_pins(unsigned pins
)
595 if (pins
& ATMEL_SSC_TF
)
596 at91_set_B_periph(AT91_PIN_PA29
, 1);
597 if (pins
& ATMEL_SSC_TK
)
598 at91_set_B_periph(AT91_PIN_PA30
, 1);
599 if (pins
& ATMEL_SSC_TD
)
600 at91_set_B_periph(AT91_PIN_PA13
, 1);
601 if (pins
& ATMEL_SSC_RD
)
602 at91_set_B_periph(AT91_PIN_PA14
, 1);
603 if (pins
& ATMEL_SSC_RK
)
604 at91_set_B_periph(AT91_PIN_PA9
, 1);
605 if (pins
& ATMEL_SSC_RF
)
606 at91_set_B_periph(AT91_PIN_PA8
, 1);
610 * SSC controllers are accessed through library code, instead of any
611 * kind of all-singing/all-dancing driver. For example one could be
612 * used by a particular I2S audio codec's driver, while another one
613 * on the same system might be used by a custom data capture driver.
615 void __init
at91_add_device_ssc(unsigned id
, unsigned pins
)
617 struct platform_device
*pdev
;
620 * NOTE: caller is responsible for passing information matching
621 * "pins" to whatever will be using each particular controller.
624 case AT91SAM9RL_ID_SSC0
:
625 pdev
= &at91sam9rl_ssc0_device
;
626 configure_ssc0_pins(pins
);
627 at91_clock_associate("ssc0_clk", &pdev
->dev
, "pclk");
629 case AT91SAM9RL_ID_SSC1
:
630 pdev
= &at91sam9rl_ssc1_device
;
631 configure_ssc1_pins(pins
);
632 at91_clock_associate("ssc1_clk", &pdev
->dev
, "pclk");
638 platform_device_register(pdev
);
642 void __init
at91_add_device_ssc(unsigned id
, unsigned pins
) {}
646 /* --------------------------------------------------------------------
648 * -------------------------------------------------------------------- */
650 #if defined(CONFIG_SERIAL_ATMEL)
651 static struct resource dbgu_resources
[] = {
653 .start
= AT91_VA_BASE_SYS
+ AT91_DBGU
,
654 .end
= AT91_VA_BASE_SYS
+ AT91_DBGU
+ SZ_512
- 1,
655 .flags
= IORESOURCE_MEM
,
658 .start
= AT91_ID_SYS
,
660 .flags
= IORESOURCE_IRQ
,
664 static struct atmel_uart_data dbgu_data
= {
666 .use_dma_rx
= 0, /* DBGU not capable of receive DMA */
667 .regs
= (void __iomem
*)(AT91_VA_BASE_SYS
+ AT91_DBGU
),
670 static u64 dbgu_dmamask
= DMA_BIT_MASK(32);
672 static struct platform_device at91sam9rl_dbgu_device
= {
673 .name
= "atmel_usart",
676 .dma_mask
= &dbgu_dmamask
,
677 .coherent_dma_mask
= DMA_BIT_MASK(32),
678 .platform_data
= &dbgu_data
,
680 .resource
= dbgu_resources
,
681 .num_resources
= ARRAY_SIZE(dbgu_resources
),
684 static inline void configure_dbgu_pins(void)
686 at91_set_A_periph(AT91_PIN_PA21
, 0); /* DRXD */
687 at91_set_A_periph(AT91_PIN_PA22
, 1); /* DTXD */
690 static struct resource uart0_resources
[] = {
692 .start
= AT91SAM9RL_BASE_US0
,
693 .end
= AT91SAM9RL_BASE_US0
+ SZ_16K
- 1,
694 .flags
= IORESOURCE_MEM
,
697 .start
= AT91SAM9RL_ID_US0
,
698 .end
= AT91SAM9RL_ID_US0
,
699 .flags
= IORESOURCE_IRQ
,
703 static struct atmel_uart_data uart0_data
= {
708 static u64 uart0_dmamask
= DMA_BIT_MASK(32);
710 static struct platform_device at91sam9rl_uart0_device
= {
711 .name
= "atmel_usart",
714 .dma_mask
= &uart0_dmamask
,
715 .coherent_dma_mask
= DMA_BIT_MASK(32),
716 .platform_data
= &uart0_data
,
718 .resource
= uart0_resources
,
719 .num_resources
= ARRAY_SIZE(uart0_resources
),
722 static inline void configure_usart0_pins(unsigned pins
)
724 at91_set_A_periph(AT91_PIN_PA6
, 1); /* TXD0 */
725 at91_set_A_periph(AT91_PIN_PA7
, 0); /* RXD0 */
727 if (pins
& ATMEL_UART_RTS
)
728 at91_set_A_periph(AT91_PIN_PA9
, 0); /* RTS0 */
729 if (pins
& ATMEL_UART_CTS
)
730 at91_set_A_periph(AT91_PIN_PA10
, 0); /* CTS0 */
731 if (pins
& ATMEL_UART_DSR
)
732 at91_set_A_periph(AT91_PIN_PD14
, 0); /* DSR0 */
733 if (pins
& ATMEL_UART_DTR
)
734 at91_set_A_periph(AT91_PIN_PD15
, 0); /* DTR0 */
735 if (pins
& ATMEL_UART_DCD
)
736 at91_set_A_periph(AT91_PIN_PD16
, 0); /* DCD0 */
737 if (pins
& ATMEL_UART_RI
)
738 at91_set_A_periph(AT91_PIN_PD17
, 0); /* RI0 */
741 static struct resource uart1_resources
[] = {
743 .start
= AT91SAM9RL_BASE_US1
,
744 .end
= AT91SAM9RL_BASE_US1
+ SZ_16K
- 1,
745 .flags
= IORESOURCE_MEM
,
748 .start
= AT91SAM9RL_ID_US1
,
749 .end
= AT91SAM9RL_ID_US1
,
750 .flags
= IORESOURCE_IRQ
,
754 static struct atmel_uart_data uart1_data
= {
759 static u64 uart1_dmamask
= DMA_BIT_MASK(32);
761 static struct platform_device at91sam9rl_uart1_device
= {
762 .name
= "atmel_usart",
765 .dma_mask
= &uart1_dmamask
,
766 .coherent_dma_mask
= DMA_BIT_MASK(32),
767 .platform_data
= &uart1_data
,
769 .resource
= uart1_resources
,
770 .num_resources
= ARRAY_SIZE(uart1_resources
),
773 static inline void configure_usart1_pins(unsigned pins
)
775 at91_set_A_periph(AT91_PIN_PA11
, 1); /* TXD1 */
776 at91_set_A_periph(AT91_PIN_PA12
, 0); /* RXD1 */
778 if (pins
& ATMEL_UART_RTS
)
779 at91_set_B_periph(AT91_PIN_PA18
, 0); /* RTS1 */
780 if (pins
& ATMEL_UART_CTS
)
781 at91_set_B_periph(AT91_PIN_PA19
, 0); /* CTS1 */
784 static struct resource uart2_resources
[] = {
786 .start
= AT91SAM9RL_BASE_US2
,
787 .end
= AT91SAM9RL_BASE_US2
+ SZ_16K
- 1,
788 .flags
= IORESOURCE_MEM
,
791 .start
= AT91SAM9RL_ID_US2
,
792 .end
= AT91SAM9RL_ID_US2
,
793 .flags
= IORESOURCE_IRQ
,
797 static struct atmel_uart_data uart2_data
= {
802 static u64 uart2_dmamask
= DMA_BIT_MASK(32);
804 static struct platform_device at91sam9rl_uart2_device
= {
805 .name
= "atmel_usart",
808 .dma_mask
= &uart2_dmamask
,
809 .coherent_dma_mask
= DMA_BIT_MASK(32),
810 .platform_data
= &uart2_data
,
812 .resource
= uart2_resources
,
813 .num_resources
= ARRAY_SIZE(uart2_resources
),
816 static inline void configure_usart2_pins(unsigned pins
)
818 at91_set_A_periph(AT91_PIN_PA13
, 1); /* TXD2 */
819 at91_set_A_periph(AT91_PIN_PA14
, 0); /* RXD2 */
821 if (pins
& ATMEL_UART_RTS
)
822 at91_set_A_periph(AT91_PIN_PA29
, 0); /* RTS2 */
823 if (pins
& ATMEL_UART_CTS
)
824 at91_set_A_periph(AT91_PIN_PA30
, 0); /* CTS2 */
827 static struct resource uart3_resources
[] = {
829 .start
= AT91SAM9RL_BASE_US3
,
830 .end
= AT91SAM9RL_BASE_US3
+ SZ_16K
- 1,
831 .flags
= IORESOURCE_MEM
,
834 .start
= AT91SAM9RL_ID_US3
,
835 .end
= AT91SAM9RL_ID_US3
,
836 .flags
= IORESOURCE_IRQ
,
840 static struct atmel_uart_data uart3_data
= {
845 static u64 uart3_dmamask
= DMA_BIT_MASK(32);
847 static struct platform_device at91sam9rl_uart3_device
= {
848 .name
= "atmel_usart",
851 .dma_mask
= &uart3_dmamask
,
852 .coherent_dma_mask
= DMA_BIT_MASK(32),
853 .platform_data
= &uart3_data
,
855 .resource
= uart3_resources
,
856 .num_resources
= ARRAY_SIZE(uart3_resources
),
859 static inline void configure_usart3_pins(unsigned pins
)
861 at91_set_A_periph(AT91_PIN_PB0
, 1); /* TXD3 */
862 at91_set_A_periph(AT91_PIN_PB1
, 0); /* RXD3 */
864 if (pins
& ATMEL_UART_RTS
)
865 at91_set_B_periph(AT91_PIN_PD4
, 0); /* RTS3 */
866 if (pins
& ATMEL_UART_CTS
)
867 at91_set_B_periph(AT91_PIN_PD3
, 0); /* CTS3 */
870 static struct platform_device
*__initdata at91_uarts
[ATMEL_MAX_UART
]; /* the UARTs to use */
871 struct platform_device
*atmel_default_console_device
; /* the serial console device */
873 void __init
at91_register_uart(unsigned id
, unsigned portnr
, unsigned pins
)
875 struct platform_device
*pdev
;
879 pdev
= &at91sam9rl_dbgu_device
;
880 configure_dbgu_pins();
881 at91_clock_associate("mck", &pdev
->dev
, "usart");
883 case AT91SAM9RL_ID_US0
:
884 pdev
= &at91sam9rl_uart0_device
;
885 configure_usart0_pins(pins
);
886 at91_clock_associate("usart0_clk", &pdev
->dev
, "usart");
888 case AT91SAM9RL_ID_US1
:
889 pdev
= &at91sam9rl_uart1_device
;
890 configure_usart1_pins(pins
);
891 at91_clock_associate("usart1_clk", &pdev
->dev
, "usart");
893 case AT91SAM9RL_ID_US2
:
894 pdev
= &at91sam9rl_uart2_device
;
895 configure_usart2_pins(pins
);
896 at91_clock_associate("usart2_clk", &pdev
->dev
, "usart");
898 case AT91SAM9RL_ID_US3
:
899 pdev
= &at91sam9rl_uart3_device
;
900 configure_usart3_pins(pins
);
901 at91_clock_associate("usart3_clk", &pdev
->dev
, "usart");
906 pdev
->id
= portnr
; /* update to mapped ID */
908 if (portnr
< ATMEL_MAX_UART
)
909 at91_uarts
[portnr
] = pdev
;
912 void __init
at91_set_serial_console(unsigned portnr
)
914 if (portnr
< ATMEL_MAX_UART
)
915 atmel_default_console_device
= at91_uarts
[portnr
];
918 void __init
at91_add_device_serial(void)
922 for (i
= 0; i
< ATMEL_MAX_UART
; i
++) {
924 platform_device_register(at91_uarts
[i
]);
927 if (!atmel_default_console_device
)
928 printk(KERN_INFO
"AT91: No default serial console defined.\n");
931 void __init
at91_register_uart(unsigned id
, unsigned portnr
, unsigned pins
) {}
932 void __init
at91_set_serial_console(unsigned portnr
) {}
933 void __init
at91_add_device_serial(void) {}
937 /* -------------------------------------------------------------------- */
940 * These devices are always present and don't need any board-specific
943 static int __init
at91_add_standard_devices(void)
945 at91_add_device_rtc();
946 at91_add_device_rtt();
947 at91_add_device_watchdog();
948 at91_add_device_tc();
952 arch_initcall(at91_add_standard_devices
);