projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branches 'topic/fix/misc' and 'topic/fix/hda' into for-linus
[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9rl_devices.c
1 /*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9 #include <asm/mach/arch.h>
10 #include <asm/mach/map.h>
11
12 #include <linux/dma-mapping.h>
13 #include <linux/platform_device.h>
14 #include <linux/i2c-gpio.h>
15
16 #include <linux/fb.h>
17 #include <video/atmel_lcdc.h>
18
19 #include <mach/board.h>
20 #include <mach/gpio.h>
21 #include <mach/at91sam9rl.h>
22 #include <mach/at91sam9rl_matrix.h>
23 #include <mach/at91sam9_smc.h>
24
25 #include "generic.h"
26
27
28 /* --------------------------------------------------------------------
29 * USB HS Device (Gadget)
30 * -------------------------------------------------------------------- */
31
32 #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
33
34 static struct resource usba_udc_resources[] = {
35 [0] = {
36 .start = AT91SAM9RL_UDPHS_FIFO,
37 .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
38 .flags = IORESOURCE_MEM,
39 },
40 [1] = {
41 .start = AT91SAM9RL_BASE_UDPHS,
42 .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [2] = {
46 .start = AT91SAM9RL_ID_UDPHS,
47 .end = AT91SAM9RL_ID_UDPHS,
48 .flags = IORESOURCE_IRQ,
49 },
50 };
51
52 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
53 [idx] = { \
54 .name = nam, \
55 .index = idx, \
56 .fifo_size = maxpkt, \
57 .nr_banks = maxbk, \
58 .can_dma = dma, \
59 .can_isoc = isoc, \
60 }
61
62 static struct usba_ep_data usba_udc_ep[] __initdata = {
63 EP("ep0", 0, 64, 1, 0, 0),
64 EP("ep1", 1, 1024, 2, 1, 1),
65 EP("ep2", 2, 1024, 2, 1, 1),
66 EP("ep3", 3, 1024, 3, 1, 0),
67 EP("ep4", 4, 1024, 3, 1, 0),
68 EP("ep5", 5, 1024, 3, 1, 1),
69 EP("ep6", 6, 1024, 3, 1, 1),
70 };
71
72 #undef EP
73
74 /*
75 * pdata doesn't have room for any endpoints, so we need to
76 * append room for the ones we need right after it.
77 */
78 static struct {
79 struct usba_platform_data pdata;
80 struct usba_ep_data ep[7];
81 } usba_udc_data;
82
83 static struct platform_device at91_usba_udc_device = {
84 .name = "atmel_usba_udc",
85 .id = -1,
86 .dev = {
87 .platform_data = &usba_udc_data.pdata,
88 },
89 .resource = usba_udc_resources,
90 .num_resources = ARRAY_SIZE(usba_udc_resources),
91 };
92
93 void __init at91_add_device_usba(struct usba_platform_data *data)
94 {
95 /*
96 * Invalid pins are 0 on AT91, but the usba driver is shared
97 * with AVR32, which use negative values instead. Once/if
98 * gpio_is_valid() is ported to AT91, revisit this code.
99 */
100 usba_udc_data.pdata.vbus_pin = -EINVAL;
101 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
102 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
103
104 if (data && data->vbus_pin > 0) {
105 at91_set_gpio_input(data->vbus_pin, 0);
106 at91_set_deglitch(data->vbus_pin, 1);
107 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
108 }
109
110 /* Pullup pin is handled internally by USB device peripheral */
111
112 /* Clocks */
113 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
114 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
115
116 platform_device_register(&at91_usba_udc_device);
117 }
118 #else
119 void __init at91_add_device_usba(struct usba_platform_data *data) {}
120 #endif
121
122
123 /* --------------------------------------------------------------------
124 * MMC / SD
125 * -------------------------------------------------------------------- */
126
127 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
128 static u64 mmc_dmamask = DMA_BIT_MASK(32);
129 static struct at91_mmc_data mmc_data;
130
131 static struct resource mmc_resources[] = {
132 [0] = {
133 .start = AT91SAM9RL_BASE_MCI,
134 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
135 .flags = IORESOURCE_MEM,
136 },
137 [1] = {
138 .start = AT91SAM9RL_ID_MCI,
139 .end = AT91SAM9RL_ID_MCI,
140 .flags = IORESOURCE_IRQ,
141 },
142 };
143
144 static struct platform_device at91sam9rl_mmc_device = {
145 .name = "at91_mci",
146 .id = -1,
147 .dev = {
148 .dma_mask = &mmc_dmamask,
149 .coherent_dma_mask = DMA_BIT_MASK(32),
150 .platform_data = &mmc_data,
151 },
152 .resource = mmc_resources,
153 .num_resources = ARRAY_SIZE(mmc_resources),
154 };
155
156 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
157 {
158 if (!data)
159 return;
160
161 /* input/irq */
162 if (data->det_pin) {
163 at91_set_gpio_input(data->det_pin, 1);
164 at91_set_deglitch(data->det_pin, 1);
165 }
166 if (data->wp_pin)
167 at91_set_gpio_input(data->wp_pin, 1);
168 if (data->vcc_pin)
169 at91_set_gpio_output(data->vcc_pin, 0);
170
171 /* CLK */
172 at91_set_A_periph(AT91_PIN_PA2, 0);
173
174 /* CMD */
175 at91_set_A_periph(AT91_PIN_PA1, 1);
176
177 /* DAT0, maybe DAT1..DAT3 */
178 at91_set_A_periph(AT91_PIN_PA0, 1);
179 if (data->wire4) {
180 at91_set_A_periph(AT91_PIN_PA3, 1);
181 at91_set_A_periph(AT91_PIN_PA4, 1);
182 at91_set_A_periph(AT91_PIN_PA5, 1);
183 }
184
185 mmc_data = *data;
186 platform_device_register(&at91sam9rl_mmc_device);
187 }
188 #else
189 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
190 #endif
191
192
193 /* --------------------------------------------------------------------
194 * NAND / SmartMedia
195 * -------------------------------------------------------------------- */
196
197 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
198 static struct atmel_nand_data nand_data;
199
200 #define NAND_BASE AT91_CHIPSELECT_3
201
202 static struct resource nand_resources[] = {
203 [0] = {
204 .start = NAND_BASE,
205 .end = NAND_BASE + SZ_256M - 1,
206 .flags = IORESOURCE_MEM,
207 },
208 [1] = {
209 .start = AT91_BASE_SYS + AT91_ECC,
210 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
211 .flags = IORESOURCE_MEM,
212 }
213 };
214
215 static struct platform_device atmel_nand_device = {
216 .name = "atmel_nand",
217 .id = -1,
218 .dev = {
219 .platform_data = &nand_data,
220 },
221 .resource = nand_resources,
222 .num_resources = ARRAY_SIZE(nand_resources),
223 };
224
225 void __init at91_add_device_nand(struct atmel_nand_data *data)
226 {
227 unsigned long csa;
228
229 if (!data)
230 return;
231
232 csa = at91_sys_read(AT91_MATRIX_EBICSA);
233 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
234
235 /* set the bus interface characteristics */
236 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
237 | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
238
239 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
240 | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
241
242 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
243
244 at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
245
246 /* enable pin */
247 if (data->enable_pin)
248 at91_set_gpio_output(data->enable_pin, 1);
249
250 /* ready/busy pin */
251 if (data->rdy_pin)
252 at91_set_gpio_input(data->rdy_pin, 1);
253
254 /* card detect pin */
255 if (data->det_pin)
256 at91_set_gpio_input(data->det_pin, 1);
257
258 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
259 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
260
261 nand_data = *data;
262 platform_device_register(&atmel_nand_device);
263 }
264
265 #else
266 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
267 #endif
268
269
270 /* --------------------------------------------------------------------
271 * TWI (i2c)
272 * -------------------------------------------------------------------- */
273
274 /*
275 * Prefer the GPIO code since the TWI controller isn't robust
276 * (gets overruns and underruns under load) and can only issue
277 * repeated STARTs in one scenario (the driver doesn't yet handle them).
278 */
279 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
280
281 static struct i2c_gpio_platform_data pdata = {
282 .sda_pin = AT91_PIN_PA23,
283 .sda_is_open_drain = 1,
284 .scl_pin = AT91_PIN_PA24,
285 .scl_is_open_drain = 1,
286 .udelay = 2, /* ~100 kHz */
287 };
288
289 static struct platform_device at91sam9rl_twi_device = {
290 .name = "i2c-gpio",
291 .id = -1,
292 .dev.platform_data = &pdata,
293 };
294
295 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
296 {
297 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
298 at91_set_multi_drive(AT91_PIN_PA23, 1);
299
300 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
301 at91_set_multi_drive(AT91_PIN_PA24, 1);
302
303 i2c_register_board_info(0, devices, nr_devices);
304 platform_device_register(&at91sam9rl_twi_device);
305 }
306
307 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
308
309 static struct resource twi_resources[] = {
310 [0] = {
311 .start = AT91SAM9RL_BASE_TWI0,
312 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
313 .flags = IORESOURCE_MEM,
314 },
315 [1] = {
316 .start = AT91SAM9RL_ID_TWI0,
317 .end = AT91SAM9RL_ID_TWI0,
318 .flags = IORESOURCE_IRQ,
319 },
320 };
321
322 static struct platform_device at91sam9rl_twi_device = {
323 .name = "at91_i2c",
324 .id = -1,
325 .resource = twi_resources,
326 .num_resources = ARRAY_SIZE(twi_resources),
327 };
328
329 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
330 {
331 /* pins used for TWI interface */
332 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
333 at91_set_multi_drive(AT91_PIN_PA23, 1);
334
335 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
336 at91_set_multi_drive(AT91_PIN_PA24, 1);
337
338 i2c_register_board_info(0, devices, nr_devices);
339 platform_device_register(&at91sam9rl_twi_device);
340 }
341 #else
342 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
343 #endif
344
345
346 /* --------------------------------------------------------------------
347 * SPI
348 * -------------------------------------------------------------------- */
349
350 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
351 static u64 spi_dmamask = DMA_BIT_MASK(32);
352
353 static struct resource spi_resources[] = {
354 [0] = {
355 .start = AT91SAM9RL_BASE_SPI,
356 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
357 .flags = IORESOURCE_MEM,
358 },
359 [1] = {
360 .start = AT91SAM9RL_ID_SPI,
361 .end = AT91SAM9RL_ID_SPI,
362 .flags = IORESOURCE_IRQ,
363 },
364 };
365
366 static struct platform_device at91sam9rl_spi_device = {
367 .name = "atmel_spi",
368 .id = 0,
369 .dev = {
370 .dma_mask = &spi_dmamask,
371 .coherent_dma_mask = DMA_BIT_MASK(32),
372 },
373 .resource = spi_resources,
374 .num_resources = ARRAY_SIZE(spi_resources),
375 };
376
377 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
378
379
380 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
381 {
382 int i;
383 unsigned long cs_pin;
384
385 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
386 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
387 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
388
389 /* Enable SPI chip-selects */
390 for (i = 0; i < nr_devices; i++) {
391 if (devices[i].controller_data)
392 cs_pin = (unsigned long) devices[i].controller_data;
393 else
394 cs_pin = spi_standard_cs[devices[i].chip_select];
395
396 /* enable chip-select pin */
397 at91_set_gpio_output(cs_pin, 1);
398
399 /* pass chip-select pin to driver */
400 devices[i].controller_data = (void *) cs_pin;
401 }
402
403 spi_register_board_info(devices, nr_devices);
404 platform_device_register(&at91sam9rl_spi_device);
405 }
406 #else
407 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
408 #endif
409
410
411 /* --------------------------------------------------------------------
412 * LCD Controller
413 * -------------------------------------------------------------------- */
414
415 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
416 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
417 static struct atmel_lcdfb_info lcdc_data;
418
419 static struct resource lcdc_resources[] = {
420 [0] = {
421 .start = AT91SAM9RL_LCDC_BASE,
422 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
423 .flags = IORESOURCE_MEM,
424 },
425 [1] = {
426 .start = AT91SAM9RL_ID_LCDC,
427 .end = AT91SAM9RL_ID_LCDC,
428 .flags = IORESOURCE_IRQ,
429 },
430 };
431
432 static struct platform_device at91_lcdc_device = {
433 .name = "atmel_lcdfb",
434 .id = 0,
435 .dev = {
436 .dma_mask = &lcdc_dmamask,
437 .coherent_dma_mask = DMA_BIT_MASK(32),
438 .platform_data = &lcdc_data,
439 },
440 .resource = lcdc_resources,
441 .num_resources = ARRAY_SIZE(lcdc_resources),
442 };
443
444 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
445 {
446 if (!data) {
447 return;
448 }
449
450 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
451 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
452 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
453 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
454 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
455 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
456 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
457 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
458 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
459 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
460 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
461 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
462 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
463 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
464 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
465 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
466 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
467 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
468 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
469 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
470 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
471
472 lcdc_data = *data;
473 platform_device_register(&at91_lcdc_device);
474 }
475 #else
476 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
477 #endif
478
479
480 /* --------------------------------------------------------------------
481 * Timer/Counter block
482 * -------------------------------------------------------------------- */
483
484 #ifdef CONFIG_ATMEL_TCLIB
485
486 static struct resource tcb_resources[] = {
487 [0] = {
488 .start = AT91SAM9RL_BASE_TCB0,
489 .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
490 .flags = IORESOURCE_MEM,
491 },
492 [1] = {
493 .start = AT91SAM9RL_ID_TC0,
494 .end = AT91SAM9RL_ID_TC0,
495 .flags = IORESOURCE_IRQ,
496 },
497 [2] = {
498 .start = AT91SAM9RL_ID_TC1,
499 .end = AT91SAM9RL_ID_TC1,
500 .flags = IORESOURCE_IRQ,
501 },
502 [3] = {
503 .start = AT91SAM9RL_ID_TC2,
504 .end = AT91SAM9RL_ID_TC2,
505 .flags = IORESOURCE_IRQ,
506 },
507 };
508
509 static struct platform_device at91sam9rl_tcb_device = {
510 .name = "atmel_tcb",
511 .id = 0,
512 .resource = tcb_resources,
513 .num_resources = ARRAY_SIZE(tcb_resources),
514 };
515
516 static void __init at91_add_device_tc(void)
517 {
518 /* this chip has a separate clock and irq for each TC channel */
519 at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
520 at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
521 at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
522 platform_device_register(&at91sam9rl_tcb_device);
523 }
524 #else
525 static void __init at91_add_device_tc(void) { }
526 #endif
527
528
529 /* --------------------------------------------------------------------
530 * Touchscreen
531 * -------------------------------------------------------------------- */
532
533 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
534 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
535
536 static struct resource tsadcc_resources[] = {
537 [0] = {
538 .start = AT91SAM9RL_BASE_TSC,
539 .end = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
540 .flags = IORESOURCE_MEM,
541 },
542 [1] = {
543 .start = AT91SAM9RL_ID_TSC,
544 .end = AT91SAM9RL_ID_TSC,
545 .flags = IORESOURCE_IRQ,
546 }
547 };
548
549 static struct platform_device at91sam9rl_tsadcc_device = {
550 .name = "atmel_tsadcc",
551 .id = -1,
552 .dev = {
553 .dma_mask = &tsadcc_dmamask,
554 .coherent_dma_mask = DMA_BIT_MASK(32),
555 },
556 .resource = tsadcc_resources,
557 .num_resources = ARRAY_SIZE(tsadcc_resources),
558 };
559
560 void __init at91_add_device_tsadcc(void)
561 {
562 at91_set_A_periph(AT91_PIN_PA17, 0); /* AD0_XR */
563 at91_set_A_periph(AT91_PIN_PA18, 0); /* AD1_XL */
564 at91_set_A_periph(AT91_PIN_PA19, 0); /* AD2_YT */
565 at91_set_A_periph(AT91_PIN_PA20, 0); /* AD3_TB */
566
567 platform_device_register(&at91sam9rl_tsadcc_device);
568 }
569 #else
570 void __init at91_add_device_tsadcc(void) {}
571 #endif
572
573
574 /* --------------------------------------------------------------------
575 * RTC
576 * -------------------------------------------------------------------- */
577
578 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
579 static struct platform_device at91sam9rl_rtc_device = {
580 .name = "at91_rtc",
581 .id = -1,
582 .num_resources = 0,
583 };
584
585 static void __init at91_add_device_rtc(void)
586 {
587 platform_device_register(&at91sam9rl_rtc_device);
588 }
589 #else
590 static void __init at91_add_device_rtc(void) {}
591 #endif
592
593
594 /* --------------------------------------------------------------------
595 * RTT
596 * -------------------------------------------------------------------- */
597
598 static struct resource rtt_resources[] = {
599 {
600 .start = AT91_BASE_SYS + AT91_RTT,
601 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
602 .flags = IORESOURCE_MEM,
603 }
604 };
605
606 static struct platform_device at91sam9rl_rtt_device = {
607 .name = "at91_rtt",
608 .id = 0,
609 .resource = rtt_resources,
610 .num_resources = ARRAY_SIZE(rtt_resources),
611 };
612
613 static void __init at91_add_device_rtt(void)
614 {
615 platform_device_register(&at91sam9rl_rtt_device);
616 }
617
618
619 /* --------------------------------------------------------------------
620 * Watchdog
621 * -------------------------------------------------------------------- */
622
623 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
624 static struct platform_device at91sam9rl_wdt_device = {
625 .name = "at91_wdt",
626 .id = -1,
627 .num_resources = 0,
628 };
629
630 static void __init at91_add_device_watchdog(void)
631 {
632 platform_device_register(&at91sam9rl_wdt_device);
633 }
634 #else
635 static void __init at91_add_device_watchdog(void) {}
636 #endif
637
638
639 /* --------------------------------------------------------------------
640 * PWM
641 * --------------------------------------------------------------------*/
642
643 #if defined(CONFIG_ATMEL_PWM)
644 static u32 pwm_mask;
645
646 static struct resource pwm_resources[] = {
647 [0] = {
648 .start = AT91SAM9RL_BASE_PWMC,
649 .end = AT91SAM9RL_BASE_PWMC + SZ_16K - 1,
650 .flags = IORESOURCE_MEM,
651 },
652 [1] = {
653 .start = AT91SAM9RL_ID_PWMC,
654 .end = AT91SAM9RL_ID_PWMC,
655 .flags = IORESOURCE_IRQ,
656 },
657 };
658
659 static struct platform_device at91sam9rl_pwm0_device = {
660 .name = "atmel_pwm",
661 .id = -1,
662 .dev = {
663 .platform_data = &pwm_mask,
664 },
665 .resource = pwm_resources,
666 .num_resources = ARRAY_SIZE(pwm_resources),
667 };
668
669 void __init at91_add_device_pwm(u32 mask)
670 {
671 if (mask & (1 << AT91_PWM0))
672 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM0 */
673
674 if (mask & (1 << AT91_PWM1))
675 at91_set_B_periph(AT91_PIN_PB9, 1); /* enable PWM1 */
676
677 if (mask & (1 << AT91_PWM2))
678 at91_set_B_periph(AT91_PIN_PD5, 1); /* enable PWM2 */
679
680 if (mask & (1 << AT91_PWM3))
681 at91_set_B_periph(AT91_PIN_PD8, 1); /* enable PWM3 */
682
683 pwm_mask = mask;
684
685 platform_device_register(&at91sam9rl_pwm0_device);
686 }
687 #else
688 void __init at91_add_device_pwm(u32 mask) {}
689 #endif
690
691
692 /* --------------------------------------------------------------------
693 * SSC -- Synchronous Serial Controller
694 * -------------------------------------------------------------------- */
695
696 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
697 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
698
699 static struct resource ssc0_resources[] = {
700 [0] = {
701 .start = AT91SAM9RL_BASE_SSC0,
702 .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
703 .flags = IORESOURCE_MEM,
704 },
705 [1] = {
706 .start = AT91SAM9RL_ID_SSC0,
707 .end = AT91SAM9RL_ID_SSC0,
708 .flags = IORESOURCE_IRQ,
709 },
710 };
711
712 static struct platform_device at91sam9rl_ssc0_device = {
713 .name = "ssc",
714 .id = 0,
715 .dev = {
716 .dma_mask = &ssc0_dmamask,
717 .coherent_dma_mask = DMA_BIT_MASK(32),
718 },
719 .resource = ssc0_resources,
720 .num_resources = ARRAY_SIZE(ssc0_resources),
721 };
722
723 static inline void configure_ssc0_pins(unsigned pins)
724 {
725 if (pins & ATMEL_SSC_TF)
726 at91_set_A_periph(AT91_PIN_PC0, 1);
727 if (pins & ATMEL_SSC_TK)
728 at91_set_A_periph(AT91_PIN_PC1, 1);
729 if (pins & ATMEL_SSC_TD)
730 at91_set_A_periph(AT91_PIN_PA15, 1);
731 if (pins & ATMEL_SSC_RD)
732 at91_set_A_periph(AT91_PIN_PA16, 1);
733 if (pins & ATMEL_SSC_RK)
734 at91_set_B_periph(AT91_PIN_PA10, 1);
735 if (pins & ATMEL_SSC_RF)
736 at91_set_B_periph(AT91_PIN_PA22, 1);
737 }
738
739 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
740
741 static struct resource ssc1_resources[] = {
742 [0] = {
743 .start = AT91SAM9RL_BASE_SSC1,
744 .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
745 .flags = IORESOURCE_MEM,
746 },
747 [1] = {
748 .start = AT91SAM9RL_ID_SSC1,
749 .end = AT91SAM9RL_ID_SSC1,
750 .flags = IORESOURCE_IRQ,
751 },
752 };
753
754 static struct platform_device at91sam9rl_ssc1_device = {
755 .name = "ssc",
756 .id = 1,
757 .dev = {
758 .dma_mask = &ssc1_dmamask,
759 .coherent_dma_mask = DMA_BIT_MASK(32),
760 },
761 .resource = ssc1_resources,
762 .num_resources = ARRAY_SIZE(ssc1_resources),
763 };
764
765 static inline void configure_ssc1_pins(unsigned pins)
766 {
767 if (pins & ATMEL_SSC_TF)
768 at91_set_B_periph(AT91_PIN_PA29, 1);
769 if (pins & ATMEL_SSC_TK)
770 at91_set_B_periph(AT91_PIN_PA30, 1);
771 if (pins & ATMEL_SSC_TD)
772 at91_set_B_periph(AT91_PIN_PA13, 1);
773 if (pins & ATMEL_SSC_RD)
774 at91_set_B_periph(AT91_PIN_PA14, 1);
775 if (pins & ATMEL_SSC_RK)
776 at91_set_B_periph(AT91_PIN_PA9, 1);
777 if (pins & ATMEL_SSC_RF)
778 at91_set_B_periph(AT91_PIN_PA8, 1);
779 }
780
781 /*
782 * SSC controllers are accessed through library code, instead of any
783 * kind of all-singing/all-dancing driver. For example one could be
784 * used by a particular I2S audio codec's driver, while another one
785 * on the same system might be used by a custom data capture driver.
786 */
787 void __init at91_add_device_ssc(unsigned id, unsigned pins)
788 {
789 struct platform_device *pdev;
790
791 /*
792 * NOTE: caller is responsible for passing information matching
793 * "pins" to whatever will be using each particular controller.
794 */
795 switch (id) {
796 case AT91SAM9RL_ID_SSC0:
797 pdev = &at91sam9rl_ssc0_device;
798 configure_ssc0_pins(pins);
799 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
800 break;
801 case AT91SAM9RL_ID_SSC1:
802 pdev = &at91sam9rl_ssc1_device;
803 configure_ssc1_pins(pins);
804 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
805 break;
806 default:
807 return;
808 }
809
810 platform_device_register(pdev);
811 }
812
813 #else
814 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
815 #endif
816
817
818 /* --------------------------------------------------------------------
819 * UART
820 * -------------------------------------------------------------------- */
821
822 #if defined(CONFIG_SERIAL_ATMEL)
823 static struct resource dbgu_resources[] = {
824 [0] = {
825 .start = AT91_VA_BASE_SYS + AT91_DBGU,
826 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
827 .flags = IORESOURCE_MEM,
828 },
829 [1] = {
830 .start = AT91_ID_SYS,
831 .end = AT91_ID_SYS,
832 .flags = IORESOURCE_IRQ,
833 },
834 };
835
836 static struct atmel_uart_data dbgu_data = {
837 .use_dma_tx = 0,
838 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
839 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
840 };
841
842 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
843
844 static struct platform_device at91sam9rl_dbgu_device = {
845 .name = "atmel_usart",
846 .id = 0,
847 .dev = {
848 .dma_mask = &dbgu_dmamask,
849 .coherent_dma_mask = DMA_BIT_MASK(32),
850 .platform_data = &dbgu_data,
851 },
852 .resource = dbgu_resources,
853 .num_resources = ARRAY_SIZE(dbgu_resources),
854 };
855
856 static inline void configure_dbgu_pins(void)
857 {
858 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
859 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
860 }
861
862 static struct resource uart0_resources[] = {
863 [0] = {
864 .start = AT91SAM9RL_BASE_US0,
865 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
866 .flags = IORESOURCE_MEM,
867 },
868 [1] = {
869 .start = AT91SAM9RL_ID_US0,
870 .end = AT91SAM9RL_ID_US0,
871 .flags = IORESOURCE_IRQ,
872 },
873 };
874
875 static struct atmel_uart_data uart0_data = {
876 .use_dma_tx = 1,
877 .use_dma_rx = 1,
878 };
879
880 static u64 uart0_dmamask = DMA_BIT_MASK(32);
881
882 static struct platform_device at91sam9rl_uart0_device = {
883 .name = "atmel_usart",
884 .id = 1,
885 .dev = {
886 .dma_mask = &uart0_dmamask,
887 .coherent_dma_mask = DMA_BIT_MASK(32),
888 .platform_data = &uart0_data,
889 },
890 .resource = uart0_resources,
891 .num_resources = ARRAY_SIZE(uart0_resources),
892 };
893
894 static inline void configure_usart0_pins(unsigned pins)
895 {
896 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
897 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
898
899 if (pins & ATMEL_UART_RTS)
900 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
901 if (pins & ATMEL_UART_CTS)
902 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
903 if (pins & ATMEL_UART_DSR)
904 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */
905 if (pins & ATMEL_UART_DTR)
906 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */
907 if (pins & ATMEL_UART_DCD)
908 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */
909 if (pins & ATMEL_UART_RI)
910 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */
911 }
912
913 static struct resource uart1_resources[] = {
914 [0] = {
915 .start = AT91SAM9RL_BASE_US1,
916 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
917 .flags = IORESOURCE_MEM,
918 },
919 [1] = {
920 .start = AT91SAM9RL_ID_US1,
921 .end = AT91SAM9RL_ID_US1,
922 .flags = IORESOURCE_IRQ,
923 },
924 };
925
926 static struct atmel_uart_data uart1_data = {
927 .use_dma_tx = 1,
928 .use_dma_rx = 1,
929 };
930
931 static u64 uart1_dmamask = DMA_BIT_MASK(32);
932
933 static struct platform_device at91sam9rl_uart1_device = {
934 .name = "atmel_usart",
935 .id = 2,
936 .dev = {
937 .dma_mask = &uart1_dmamask,
938 .coherent_dma_mask = DMA_BIT_MASK(32),
939 .platform_data = &uart1_data,
940 },
941 .resource = uart1_resources,
942 .num_resources = ARRAY_SIZE(uart1_resources),
943 };
944
945 static inline void configure_usart1_pins(unsigned pins)
946 {
947 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
948 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
949
950 if (pins & ATMEL_UART_RTS)
951 at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */
952 if (pins & ATMEL_UART_CTS)
953 at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */
954 }
955
956 static struct resource uart2_resources[] = {
957 [0] = {
958 .start = AT91SAM9RL_BASE_US2,
959 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
960 .flags = IORESOURCE_MEM,
961 },
962 [1] = {
963 .start = AT91SAM9RL_ID_US2,
964 .end = AT91SAM9RL_ID_US2,
965 .flags = IORESOURCE_IRQ,
966 },
967 };
968
969 static struct atmel_uart_data uart2_data = {
970 .use_dma_tx = 1,
971 .use_dma_rx = 1,
972 };
973
974 static u64 uart2_dmamask = DMA_BIT_MASK(32);
975
976 static struct platform_device at91sam9rl_uart2_device = {
977 .name = "atmel_usart",
978 .id = 3,
979 .dev = {
980 .dma_mask = &uart2_dmamask,
981 .coherent_dma_mask = DMA_BIT_MASK(32),
982 .platform_data = &uart2_data,
983 },
984 .resource = uart2_resources,
985 .num_resources = ARRAY_SIZE(uart2_resources),
986 };
987
988 static inline void configure_usart2_pins(unsigned pins)
989 {
990 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
991 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
992
993 if (pins & ATMEL_UART_RTS)
994 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */
995 if (pins & ATMEL_UART_CTS)
996 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */
997 }
998
999 static struct resource uart3_resources[] = {
1000 [0] = {
1001 .start = AT91SAM9RL_BASE_US3,
1002 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
1003 .flags = IORESOURCE_MEM,
1004 },
1005 [1] = {
1006 .start = AT91SAM9RL_ID_US3,
1007 .end = AT91SAM9RL_ID_US3,
1008 .flags = IORESOURCE_IRQ,
1009 },
1010 };
1011
1012 static struct atmel_uart_data uart3_data = {
1013 .use_dma_tx = 1,
1014 .use_dma_rx = 1,
1015 };
1016
1017 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1018
1019 static struct platform_device at91sam9rl_uart3_device = {
1020 .name = "atmel_usart",
1021 .id = 4,
1022 .dev = {
1023 .dma_mask = &uart3_dmamask,
1024 .coherent_dma_mask = DMA_BIT_MASK(32),
1025 .platform_data = &uart3_data,
1026 },
1027 .resource = uart3_resources,
1028 .num_resources = ARRAY_SIZE(uart3_resources),
1029 };
1030
1031 static inline void configure_usart3_pins(unsigned pins)
1032 {
1033 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
1034 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
1035
1036 if (pins & ATMEL_UART_RTS)
1037 at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */
1038 if (pins & ATMEL_UART_CTS)
1039 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
1040 }
1041
1042 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1043 struct platform_device *atmel_default_console_device; /* the serial console device */
1044
1045 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1046 {
1047 struct platform_device *pdev;
1048
1049 switch (id) {
1050 case 0: /* DBGU */
1051 pdev = &at91sam9rl_dbgu_device;
1052 configure_dbgu_pins();
1053 at91_clock_associate("mck", &pdev->dev, "usart");
1054 break;
1055 case AT91SAM9RL_ID_US0:
1056 pdev = &at91sam9rl_uart0_device;
1057 configure_usart0_pins(pins);
1058 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1059 break;
1060 case AT91SAM9RL_ID_US1:
1061 pdev = &at91sam9rl_uart1_device;
1062 configure_usart1_pins(pins);
1063 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1064 break;
1065 case AT91SAM9RL_ID_US2:
1066 pdev = &at91sam9rl_uart2_device;
1067 configure_usart2_pins(pins);
1068 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1069 break;
1070 case AT91SAM9RL_ID_US3:
1071 pdev = &at91sam9rl_uart3_device;
1072 configure_usart3_pins(pins);
1073 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1074 break;
1075 default:
1076 return;
1077 }
1078 pdev->id = portnr; /* update to mapped ID */
1079
1080 if (portnr < ATMEL_MAX_UART)
1081 at91_uarts[portnr] = pdev;
1082 }
1083
1084 void __init at91_set_serial_console(unsigned portnr)
1085 {
1086 if (portnr < ATMEL_MAX_UART)
1087 atmel_default_console_device = at91_uarts[portnr];
1088 }
1089
1090 void __init at91_add_device_serial(void)
1091 {
1092 int i;
1093
1094 for (i = 0; i < ATMEL_MAX_UART; i++) {
1095 if (at91_uarts[i])
1096 platform_device_register(at91_uarts[i]);
1097 }
1098
1099 if (!atmel_default_console_device)
1100 printk(KERN_INFO "AT91: No default serial console defined.\n");
1101 }
1102 #else
1103 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1104 void __init at91_set_serial_console(unsigned portnr) {}
1105 void __init at91_add_device_serial(void) {}
1106 #endif
1107
1108
1109 /* -------------------------------------------------------------------- */
1110
1111 /*
1112 * These devices are always present and don't need any board-specific
1113 * setup.
1114 */
1115 static int __init at91_add_standard_devices(void)
1116 {
1117 at91_add_device_rtc();
1118 at91_add_device_rtt();
1119 at91_add_device_watchdog();
1120 at91_add_device_tc();
1121 return 0;
1122 }
1123
1124 arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
This page took 0.075894 seconds and 6 git commands to generate.