2 * Chip-specific setup code for the AT91SAM9x5 family
4 * Copyright (C) 2010-2012 Atmel Corporation.
6 * Licensed under GPLv2 or later.
9 #include <linux/module.h>
10 #include <linux/dma-mapping.h>
13 #include <asm/mach/arch.h>
14 #include <asm/mach/map.h>
15 #include <mach/at91sam9x5.h>
16 #include <mach/at91_pmc.h>
18 #include <mach/board.h>
25 /* --------------------------------------------------------------------
27 * -------------------------------------------------------------------- */
30 * The peripheral clocks.
32 static struct clk pioAB_clk
= {
34 .pmc_mask
= 1 << AT91SAM9X5_ID_PIOAB
,
35 .type
= CLK_TYPE_PERIPHERAL
,
37 static struct clk pioCD_clk
= {
39 .pmc_mask
= 1 << AT91SAM9X5_ID_PIOCD
,
40 .type
= CLK_TYPE_PERIPHERAL
,
42 static struct clk smd_clk
= {
44 .pmc_mask
= 1 << AT91SAM9X5_ID_SMD
,
45 .type
= CLK_TYPE_PERIPHERAL
,
47 static struct clk usart0_clk
= {
49 .pmc_mask
= 1 << AT91SAM9X5_ID_USART0
,
50 .type
= CLK_TYPE_PERIPHERAL
,
52 static struct clk usart1_clk
= {
54 .pmc_mask
= 1 << AT91SAM9X5_ID_USART1
,
55 .type
= CLK_TYPE_PERIPHERAL
,
57 static struct clk usart2_clk
= {
59 .pmc_mask
= 1 << AT91SAM9X5_ID_USART2
,
60 .type
= CLK_TYPE_PERIPHERAL
,
62 /* USART3 clock - Only for sam9g25/sam9x25 */
63 static struct clk usart3_clk
= {
65 .pmc_mask
= 1 << AT91SAM9X5_ID_USART3
,
66 .type
= CLK_TYPE_PERIPHERAL
,
68 static struct clk twi0_clk
= {
70 .pmc_mask
= 1 << AT91SAM9X5_ID_TWI0
,
71 .type
= CLK_TYPE_PERIPHERAL
,
73 static struct clk twi1_clk
= {
75 .pmc_mask
= 1 << AT91SAM9X5_ID_TWI1
,
76 .type
= CLK_TYPE_PERIPHERAL
,
78 static struct clk twi2_clk
= {
80 .pmc_mask
= 1 << AT91SAM9X5_ID_TWI2
,
81 .type
= CLK_TYPE_PERIPHERAL
,
83 static struct clk mmc0_clk
= {
85 .pmc_mask
= 1 << AT91SAM9X5_ID_MCI0
,
86 .type
= CLK_TYPE_PERIPHERAL
,
88 static struct clk spi0_clk
= {
90 .pmc_mask
= 1 << AT91SAM9X5_ID_SPI0
,
91 .type
= CLK_TYPE_PERIPHERAL
,
93 static struct clk spi1_clk
= {
95 .pmc_mask
= 1 << AT91SAM9X5_ID_SPI1
,
96 .type
= CLK_TYPE_PERIPHERAL
,
98 static struct clk uart0_clk
= {
100 .pmc_mask
= 1 << AT91SAM9X5_ID_UART0
,
101 .type
= CLK_TYPE_PERIPHERAL
,
103 static struct clk uart1_clk
= {
105 .pmc_mask
= 1 << AT91SAM9X5_ID_UART1
,
106 .type
= CLK_TYPE_PERIPHERAL
,
108 static struct clk tcb0_clk
= {
110 .pmc_mask
= 1 << AT91SAM9X5_ID_TCB
,
111 .type
= CLK_TYPE_PERIPHERAL
,
113 static struct clk pwm_clk
= {
115 .pmc_mask
= 1 << AT91SAM9X5_ID_PWM
,
116 .type
= CLK_TYPE_PERIPHERAL
,
118 static struct clk adc_clk
= {
120 .pmc_mask
= 1 << AT91SAM9X5_ID_ADC
,
121 .type
= CLK_TYPE_PERIPHERAL
,
123 static struct clk dma0_clk
= {
125 .pmc_mask
= 1 << AT91SAM9X5_ID_DMA0
,
126 .type
= CLK_TYPE_PERIPHERAL
,
128 static struct clk dma1_clk
= {
130 .pmc_mask
= 1 << AT91SAM9X5_ID_DMA1
,
131 .type
= CLK_TYPE_PERIPHERAL
,
133 static struct clk uhphs_clk
= {
135 .pmc_mask
= 1 << AT91SAM9X5_ID_UHPHS
,
136 .type
= CLK_TYPE_PERIPHERAL
,
138 static struct clk udphs_clk
= {
140 .pmc_mask
= 1 << AT91SAM9X5_ID_UDPHS
,
141 .type
= CLK_TYPE_PERIPHERAL
,
143 /* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
144 static struct clk macb0_clk
= {
146 .pmc_mask
= 1 << AT91SAM9X5_ID_EMAC0
,
147 .type
= CLK_TYPE_PERIPHERAL
,
149 /* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
150 static struct clk lcdc_clk
= {
152 .pmc_mask
= 1 << AT91SAM9X5_ID_LCDC
,
153 .type
= CLK_TYPE_PERIPHERAL
,
155 /* isi clock - Only for sam9g25 */
156 static struct clk isi_clk
= {
158 .pmc_mask
= 1 << AT91SAM9X5_ID_ISI
,
159 .type
= CLK_TYPE_PERIPHERAL
,
161 static struct clk mmc1_clk
= {
163 .pmc_mask
= 1 << AT91SAM9X5_ID_MCI1
,
164 .type
= CLK_TYPE_PERIPHERAL
,
166 /* emac1 clock - Only for sam9x25 */
167 static struct clk macb1_clk
= {
169 .pmc_mask
= 1 << AT91SAM9X5_ID_EMAC1
,
170 .type
= CLK_TYPE_PERIPHERAL
,
172 static struct clk ssc_clk
= {
174 .pmc_mask
= 1 << AT91SAM9X5_ID_SSC
,
175 .type
= CLK_TYPE_PERIPHERAL
,
177 /* can0 clock - Only for sam9x35 */
178 static struct clk can0_clk
= {
180 .pmc_mask
= 1 << AT91SAM9X5_ID_CAN0
,
181 .type
= CLK_TYPE_PERIPHERAL
,
183 /* can1 clock - Only for sam9x35 */
184 static struct clk can1_clk
= {
186 .pmc_mask
= 1 << AT91SAM9X5_ID_CAN1
,
187 .type
= CLK_TYPE_PERIPHERAL
,
190 static struct clk
*periph_clocks
[] __initdata
= {
217 static struct clk_lookup periph_clocks_lookups
[] = {
218 /* lookup table for DT entries */
219 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck
),
220 CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk
),
221 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk
),
222 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk
),
223 CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk
),
224 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk
),
225 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk
),
226 CLKDEV_CON_ID("pioA", &pioAB_clk
),
227 CLKDEV_CON_ID("pioB", &pioAB_clk
),
228 CLKDEV_CON_ID("pioC", &pioCD_clk
),
229 CLKDEV_CON_ID("pioD", &pioCD_clk
),
230 /* additional fake clock for macb_hclk */
231 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk
),
232 CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk
),
236 * The two programmable clocks.
237 * You must configure pin multiplexing to bring these signals out.
239 static struct clk pck0
= {
241 .pmc_mask
= AT91_PMC_PCK0
,
242 .type
= CLK_TYPE_PROGRAMMABLE
,
245 static struct clk pck1
= {
247 .pmc_mask
= AT91_PMC_PCK1
,
248 .type
= CLK_TYPE_PROGRAMMABLE
,
252 static void __init
at91sam9x5_register_clocks(void)
256 for (i
= 0; i
< ARRAY_SIZE(periph_clocks
); i
++)
257 clk_register(periph_clocks
[i
]);
259 clkdev_add_table(periph_clocks_lookups
,
260 ARRAY_SIZE(periph_clocks_lookups
));
262 if (cpu_is_at91sam9g25()
263 || cpu_is_at91sam9x25())
264 clk_register(&usart3_clk
);
266 if (cpu_is_at91sam9g25()
267 || cpu_is_at91sam9x25()
268 || cpu_is_at91sam9g35()
269 || cpu_is_at91sam9x35())
270 clk_register(&macb0_clk
);
272 if (cpu_is_at91sam9g15()
273 || cpu_is_at91sam9g35()
274 || cpu_is_at91sam9x35())
275 clk_register(&lcdc_clk
);
277 if (cpu_is_at91sam9g25())
278 clk_register(&isi_clk
);
280 if (cpu_is_at91sam9x25())
281 clk_register(&macb1_clk
);
283 if (cpu_is_at91sam9x25()
284 || cpu_is_at91sam9x35()) {
285 clk_register(&can0_clk
);
286 clk_register(&can1_clk
);
293 /* --------------------------------------------------------------------
294 * AT91SAM9x5 processor initialization
295 * -------------------------------------------------------------------- */
297 static void __init
at91sam9x5_map_io(void)
299 at91_init_sram(0, AT91SAM9X5_SRAM_BASE
, AT91SAM9X5_SRAM_SIZE
);
302 static void __init
at91sam9x5_ioremap_registers(void)
304 if (of_at91sam926x_pit_init() < 0)
305 panic("Impossible to find PIT\n");
306 at91_ioremap_ramc(0, AT91SAM9X5_BASE_DDRSDRC0
, 512);
309 void __init
at91sam9x5_initialize(void)
311 arm_pm_restart
= at91sam9g45_restart
;
312 at91_extern_irq
= (1 << AT91SAM9X5_ID_IRQ0
);
314 /* Register GPIO subsystem (using DT) */
315 at91_gpio_init(NULL
, 0);
318 /* --------------------------------------------------------------------
319 * AT91SAM9x5 devices (temporary before modification of code)
320 * -------------------------------------------------------------------- */
321 void __init
at91_add_device_nand(struct atmel_nand_data
*data
) {}
323 /* --------------------------------------------------------------------
324 * Interrupt initialization
325 * -------------------------------------------------------------------- */
327 * The default interrupt priority levels (0 = lowest, 7 = highest).
329 static unsigned int at91sam9x5_default_irq_priority
[NR_AIC_IRQS
] __initdata
= {
330 7, /* Advanced Interrupt Controller (FIQ) */
331 7, /* System Peripherals */
332 1, /* Parallel IO Controller A and B */
333 1, /* Parallel IO Controller C and D */
339 6, /* Two-Wire Interface 0 */
340 6, /* Two-Wire Interface 1 */
341 6, /* Two-Wire Interface 2 */
342 0, /* Multimedia Card Interface 0 */
343 5, /* Serial Peripheral Interface 0 */
344 5, /* Serial Peripheral Interface 1 */
347 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
348 0, /* Pulse Width Modulation Controller */
349 0, /* ADC Controller */
350 0, /* DMA Controller 0 */
351 0, /* DMA Controller 1 */
352 2, /* USB Host High Speed port */
353 2, /* USB Device High speed port */
354 3, /* Ethernet MAC 0 */
355 3, /* LDC Controller or Image Sensor Interface */
356 0, /* Multimedia Card Interface 1 */
357 3, /* Ethernet MAC 1 */
358 4, /* Synchronous Serial Interface */
359 4, /* CAN Controller 0 */
360 4, /* CAN Controller 1 */
361 0, /* Advanced Interrupt Controller (IRQ0) */
364 struct at91_init_soc __initdata at91sam9x5_soc
= {
365 .map_io
= at91sam9x5_map_io
,
366 .default_irq_priority
= at91sam9x5_default_irq_priority
,
367 .ioremap_registers
= at91sam9x5_ioremap_registers
,
368 .register_clocks
= at91sam9x5_register_clocks
,
369 .init
= at91sam9x5_initialize
,