arch/arm/mach-at91/clock.c

   1 /*
   2  * linux/arch/arm/mach-at91/clock.c
   3  *
   4  * Copyright (C) 2005 David Brownell
   5  * Copyright (C) 2005 Ivan Kokshaysky
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/fs.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/list.h>
  20 #include <linux/errno.h>
  21 #include <linux/err.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26
  27 #include <mach/hardware.h>
  28 #include <mach/at91_pmc.h>
  29 #include <mach/cpu.h>
  30
  31 #include "clock.h"
  32 #include "generic.h"
  33
  34
  35 /*
  36  * There's a lot more which can be done with clocks, including cpufreq
  37  * integration, slow clock mode support (for system suspend), letting
  38  * PLLB be used at other rates (on boards that don't need USB), etc.
  39  */
  40
  41 #define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
  42 #define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
  43 #define clk_is_peripheral(x)    ((x)->type & CLK_TYPE_PERIPHERAL)
  44 #define clk_is_sys(x)           ((x)->type & CLK_TYPE_SYSTEM)
  45
  46
  47 /*
  48  * Chips have some kind of clocks : group them by functionality
  49  */
  50 #define cpu_has_utmi()          (  cpu_is_at91sam9rl() \
  51                                 || cpu_is_at91sam9g45())
  52
  53 #define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
  54                                 || cpu_is_at91sam9g45())
  55
  56 #define cpu_has_300M_plla()     (cpu_is_at91sam9g10())
  57
  58 #define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
  59                                 || cpu_is_at91sam9g45()))
  60
  61 #define cpu_has_upll()          (cpu_is_at91sam9g45())
  62
  63 /* USB host HS & FS */
  64 #define cpu_has_uhp()           (!cpu_is_at91sam9rl())
  65
  66 /* USB device FS only */
  67 #define cpu_has_udpfs()         (!(cpu_is_at91sam9rl() \
  68                                 || cpu_is_at91sam9g45()))
  69
  70 static LIST_HEAD(clocks);
  71 static DEFINE_SPINLOCK(clk_lock);
  72
  73 static u32 at91_pllb_usb_init;
  74
  75 /*
  76  * Four primary clock sources:  two crystal oscillators (32K, main), and
  77  * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
  78  * 48 MHz (unless no USB function clocks are needed).  The main clock and
  79  * both PLLs are turned off to run in "slow clock mode" (system suspend).
  80  */
  81 static struct clk clk32k = {
  82         .name           = "clk32k",
  83         .rate_hz        = AT91_SLOW_CLOCK,
  84         .users          = 1,            /* always on */
  85         .id             = 0,
  86         .type           = CLK_TYPE_PRIMARY,
  87 };
  88 static struct clk main_clk = {
  89         .name           = "main",
  90         .pmc_mask       = AT91_PMC_MOSCS,       /* in PMC_SR */
  91         .id             = 1,
  92         .type           = CLK_TYPE_PRIMARY,
  93 };
  94 static struct clk plla = {
  95         .name           = "plla",
  96         .parent         = &main_clk,
  97         .pmc_mask       = AT91_PMC_LOCKA,       /* in PMC_SR */
  98         .id             = 2,
  99         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
 100 };
 101
 102 static void pllb_mode(struct clk *clk, int is_on)
 103 {
 104         u32     value;
 105
 106         if (is_on) {
 107                 is_on = AT91_PMC_LOCKB;
 108                 value = at91_pllb_usb_init;
 109         } else
 110                 value = 0;
 111
 112         // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
 113         at91_sys_write(AT91_CKGR_PLLBR, value);
 114
 115         do {
 116                 cpu_relax();
 117         } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
 118 }
 119
 120 static struct clk pllb = {
 121         .name           = "pllb",
 122         .parent         = &main_clk,
 123         .pmc_mask       = AT91_PMC_LOCKB,       /* in PMC_SR */
 124         .mode           = pllb_mode,
 125         .id             = 3,
 126         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
 127 };
 128
 129 static void pmc_sys_mode(struct clk *clk, int is_on)
 130 {
 131         if (is_on)
 132                 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
 133         else
 134                 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
 135 }
 136
 137 static void pmc_uckr_mode(struct clk *clk, int is_on)
 138 {
 139         unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
 140
 141         if (cpu_is_at91sam9g45()) {
 142                 if (is_on)
 143                         uckr |= AT91_PMC_BIASEN;
 144                 else
 145                         uckr &= ~AT91_PMC_BIASEN;
 146         }
 147
 148         if (is_on) {
 149                 is_on = AT91_PMC_LOCKU;
 150                 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
 151         } else
 152                 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
 153
 154         do {
 155                 cpu_relax();
 156         } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
 157 }
 158
 159 /* USB function clocks (PLLB must be 48 MHz) */
 160 static struct clk udpck = {
 161         .name           = "udpck",
 162         .parent         = &pllb,
 163         .mode           = pmc_sys_mode,
 164 };
 165 struct clk utmi_clk = {
 166         .name           = "utmi_clk",
 167         .parent         = &main_clk,
 168         .pmc_mask       = AT91_PMC_UPLLEN,      /* in CKGR_UCKR */
 169         .mode           = pmc_uckr_mode,
 170         .type           = CLK_TYPE_PLL,
 171 };
 172 static struct clk uhpck = {
 173         .name           = "uhpck",
 174         /*.parent               = ... we choose parent at runtime */
 175         .mode           = pmc_sys_mode,
 176 };
 177
 178
 179 /*
 180  * The master clock is divided from the CPU clock (by 1-4).  It's used for
 181  * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
 182  * (e.g baud rate generation).  It's sourced from one of the primary clocks.
 183  */
 184 struct clk mck = {
 185         .name           = "mck",
 186         .pmc_mask       = AT91_PMC_MCKRDY,      /* in PMC_SR */
 187 };
 188
 189 static void pmc_periph_mode(struct clk *clk, int is_on)
 190 {
 191         if (is_on)
 192                 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
 193         else
 194                 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
 195 }
 196
 197 static struct clk __init *at91_css_to_clk(unsigned long css)
 198 {
 199         switch (css) {
 200                 case AT91_PMC_CSS_SLOW:
 201                         return &clk32k;
 202                 case AT91_PMC_CSS_MAIN:
 203                         return &main_clk;
 204                 case AT91_PMC_CSS_PLLA:
 205                         return &plla;
 206                 case AT91_PMC_CSS_PLLB:
 207                         if (cpu_has_upll())
 208                                 /* CSS_PLLB == CSS_UPLL */
 209                                 return &utmi_clk;
 210                         else if (cpu_has_pllb())
 211                                 return &pllb;
 212         }
 213
 214         return NULL;
 215 }
 216
 217 static void __clk_enable(struct clk *clk)
 218 {
 219         if (clk->parent)
 220                 __clk_enable(clk->parent);
 221         if (clk->users++ == 0 && clk->mode)
 222                 clk->mode(clk, 1);
 223 }
 224
 225 int clk_enable(struct clk *clk)
 226 {
 227         unsigned long   flags;
 228
 229         spin_lock_irqsave(&clk_lock, flags);
 230         __clk_enable(clk);
 231         spin_unlock_irqrestore(&clk_lock, flags);
 232         return 0;
 233 }
 234 EXPORT_SYMBOL(clk_enable);
 235
 236 static void __clk_disable(struct clk *clk)
 237 {
 238         BUG_ON(clk->users == 0);
 239         if (--clk->users == 0 && clk->mode)
 240                 clk->mode(clk, 0);
 241         if (clk->parent)
 242                 __clk_disable(clk->parent);
 243 }
 244
 245 void clk_disable(struct clk *clk)
 246 {
 247         unsigned long   flags;
 248
 249         spin_lock_irqsave(&clk_lock, flags);
 250         __clk_disable(clk);
 251         spin_unlock_irqrestore(&clk_lock, flags);
 252 }
 253 EXPORT_SYMBOL(clk_disable);
 254
 255 unsigned long clk_get_rate(struct clk *clk)
 256 {
 257         unsigned long   flags;
 258         unsigned long   rate;
 259
 260         spin_lock_irqsave(&clk_lock, flags);
 261         for (;;) {
 262                 rate = clk->rate_hz;
 263                 if (rate || !clk->parent)
 264                         break;
 265                 clk = clk->parent;
 266         }
 267         spin_unlock_irqrestore(&clk_lock, flags);
 268         return rate;
 269 }
 270 EXPORT_SYMBOL(clk_get_rate);
 271
 272 /*------------------------------------------------------------------------*/
 273
 274 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 275
 276 /*
 277  * For now, only the programmable clocks support reparenting (MCK could
 278  * do this too, with care) or rate changing (the PLLs could do this too,
 279  * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
 280  * a better rate match; we don't.
 281  */
 282
 283 long clk_round_rate(struct clk *clk, unsigned long rate)
 284 {
 285         unsigned long   flags;
 286         unsigned        prescale;
 287         unsigned long   actual;
 288         unsigned long   prev = ULONG_MAX;
 289
 290         if (!clk_is_programmable(clk))
 291                 return -EINVAL;
 292         spin_lock_irqsave(&clk_lock, flags);
 293
 294         actual = clk->parent->rate_hz;
 295         for (prescale = 0; prescale < 7; prescale++) {
 296                 if (actual > rate)
 297                         prev = actual;
 298
 299                 if (actual && actual <= rate) {
 300                         if ((prev - rate) < (rate - actual)) {
 301                                 actual = prev;
 302                                 prescale--;
 303                         }
 304                         break;
 305                 }
 306                 actual >>= 1;
 307         }
 308
 309         spin_unlock_irqrestore(&clk_lock, flags);
 310         return (prescale < 7) ? actual : -ENOENT;
 311 }
 312 EXPORT_SYMBOL(clk_round_rate);
 313
 314 int clk_set_rate(struct clk *clk, unsigned long rate)
 315 {
 316         unsigned long   flags;
 317         unsigned        prescale;
 318         unsigned long   actual;
 319
 320         if (!clk_is_programmable(clk))
 321                 return -EINVAL;
 322         if (clk->users)
 323                 return -EBUSY;
 324         spin_lock_irqsave(&clk_lock, flags);
 325
 326         actual = clk->parent->rate_hz;
 327         for (prescale = 0; prescale < 7; prescale++) {
 328                 if (actual && actual <= rate) {
 329                         u32     pckr;
 330
 331                         pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
 332                         pckr &= AT91_PMC_CSS;   /* clock selection */
 333                         pckr |= prescale << 2;
 334                         at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
 335                         clk->rate_hz = actual;
 336                         break;
 337                 }
 338                 actual >>= 1;
 339         }
 340
 341         spin_unlock_irqrestore(&clk_lock, flags);
 342         return (prescale < 7) ? actual : -ENOENT;
 343 }
 344 EXPORT_SYMBOL(clk_set_rate);
 345
 346 struct clk *clk_get_parent(struct clk *clk)
 347 {
 348         return clk->parent;
 349 }
 350 EXPORT_SYMBOL(clk_get_parent);
 351
 352 int clk_set_parent(struct clk *clk, struct clk *parent)
 353 {
 354         unsigned long   flags;
 355
 356         if (clk->users)
 357                 return -EBUSY;
 358         if (!clk_is_primary(parent) || !clk_is_programmable(clk))
 359                 return -EINVAL;
 360
 361         if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
 362                 return -EINVAL;
 363
 364         spin_lock_irqsave(&clk_lock, flags);
 365
 366         clk->rate_hz = parent->rate_hz;
 367         clk->parent = parent;
 368         at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
 369
 370         spin_unlock_irqrestore(&clk_lock, flags);
 371         return 0;
 372 }
 373 EXPORT_SYMBOL(clk_set_parent);
 374
 375 /* establish PCK0..PCKN parentage and rate */
 376 static void __init init_programmable_clock(struct clk *clk)
 377 {
 378         struct clk      *parent;
 379         u32             pckr;
 380
 381         pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
 382         parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
 383         clk->parent = parent;
 384         clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
 385 }
 386
 387 #endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
 388
 389 /*------------------------------------------------------------------------*/
 390
 391 #ifdef CONFIG_DEBUG_FS
 392
 393 static int at91_clk_show(struct seq_file *s, void *unused)
 394 {
 395         u32             scsr, pcsr, uckr = 0, sr;
 396         struct clk      *clk;
 397
 398         seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
 399         seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
 400         seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
 401         seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
 402         seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
 403         if (cpu_has_pllb())
 404                 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
 405         if (cpu_has_utmi())
 406                 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
 407         seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
 408         if (cpu_has_upll())
 409                 seq_printf(s, "USB  = %8x\n", at91_sys_read(AT91_PMC_USB));
 410         seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
 411
 412         seq_printf(s, "\n");
 413
 414         list_for_each_entry(clk, &clocks, node) {
 415                 char    *state;
 416
 417                 if (clk->mode == pmc_sys_mode)
 418                         state = (scsr & clk->pmc_mask) ? "on" : "off";
 419                 else if (clk->mode == pmc_periph_mode)
 420                         state = (pcsr & clk->pmc_mask) ? "on" : "off";
 421                 else if (clk->mode == pmc_uckr_mode)
 422                         state = (uckr & clk->pmc_mask) ? "on" : "off";
 423                 else if (clk->pmc_mask)
 424                         state = (sr & clk->pmc_mask) ? "on" : "off";
 425                 else if (clk == &clk32k || clk == &main_clk)
 426                         state = "on";
 427                 else
 428                         state = "";
 429
 430                 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
 431                         clk->name, clk->users, state, clk_get_rate(clk),
 432                         clk->parent ? clk->parent->name : "");
 433         }
 434         return 0;
 435 }
 436
 437 static int at91_clk_open(struct inode *inode, struct file *file)
 438 {
 439         return single_open(file, at91_clk_show, NULL);
 440 }
 441
 442 static const struct file_operations at91_clk_operations = {
 443         .open           = at91_clk_open,
 444         .read           = seq_read,
 445         .llseek         = seq_lseek,
 446         .release        = single_release,
 447 };
 448
 449 static int __init at91_clk_debugfs_init(void)
 450 {
 451         /* /sys/kernel/debug/at91_clk */
 452         (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
 453
 454         return 0;
 455 }
 456 postcore_initcall(at91_clk_debugfs_init);
 457
 458 #endif
 459
 460 /*------------------------------------------------------------------------*/
 461
 462 /* Register a new clock */
 463 static void __init at91_clk_add(struct clk *clk)
 464 {
 465         list_add_tail(&clk->node, &clocks);
 466
 467         clk->cl.con_id = clk->name;
 468         clk->cl.clk = clk;
 469         clkdev_add(&clk->cl);
 470 }
 471
 472 int __init clk_register(struct clk *clk)
 473 {
 474         if (clk_is_peripheral(clk)) {
 475                 if (!clk->parent)
 476                         clk->parent = &mck;
 477                 clk->mode = pmc_periph_mode;
 478         }
 479         else if (clk_is_sys(clk)) {
 480                 clk->parent = &mck;
 481                 clk->mode = pmc_sys_mode;
 482         }
 483 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 484         else if (clk_is_programmable(clk)) {
 485                 clk->mode = pmc_sys_mode;
 486                 init_programmable_clock(clk);
 487         }
 488 #endif
 489
 490         at91_clk_add(clk);
 491
 492         return 0;
 493 }
 494
 495 /*------------------------------------------------------------------------*/
 496
 497 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
 498 {
 499         unsigned mul, div;
 500
 501         div = reg & 0xff;
 502         mul = (reg >> 16) & 0x7ff;
 503         if (div && mul) {
 504                 freq /= div;
 505                 freq *= mul + 1;
 506         } else
 507                 freq = 0;
 508
 509         return freq;
 510 }
 511
 512 static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
 513 {
 514         if (pll == &pllb && (reg & AT91_PMC_USB96M))
 515                 return freq / 2;
 516         else
 517                 return freq;
 518 }
 519
 520 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
 521 {
 522         unsigned i, div = 0, mul = 0, diff = 1 << 30;
 523         unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
 524
 525         /* PLL output max 240 MHz (or 180 MHz per errata) */
 526         if (out_freq > 240000000)
 527                 goto fail;
 528
 529         for (i = 1; i < 256; i++) {
 530                 int diff1;
 531                 unsigned input, mul1;
 532
 533                 /*
 534                  * PLL input between 1MHz and 32MHz per spec, but lower
 535                  * frequences seem necessary in some cases so allow 100K.
 536                  * Warning: some newer products need 2MHz min.
 537                  */
 538                 input = main_freq / i;
 539                 if (cpu_is_at91sam9g20() && input < 2000000)
 540                         continue;
 541                 if (input < 100000)
 542                         continue;
 543                 if (input > 32000000)
 544                         continue;
 545
 546                 mul1 = out_freq / input;
 547                 if (cpu_is_at91sam9g20() && mul > 63)
 548                         continue;
 549                 if (mul1 > 2048)
 550                         continue;
 551                 if (mul1 < 2)
 552                         goto fail;
 553
 554                 diff1 = out_freq - input * mul1;
 555                 if (diff1 < 0)
 556                         diff1 = -diff1;
 557                 if (diff > diff1) {
 558                         diff = diff1;
 559                         div = i;
 560                         mul = mul1;
 561                         if (diff == 0)
 562                                 break;
 563                 }
 564         }
 565         if (i == 256 && diff > (out_freq >> 5))
 566                 goto fail;
 567         return ret | ((mul - 1) << 16) | div;
 568 fail:
 569         return 0;
 570 }
 571
 572 static struct clk *const standard_pmc_clocks[] __initdata = {
 573         /* four primary clocks */
 574         &clk32k,
 575         &main_clk,
 576         &plla,
 577
 578         /* MCK */
 579         &mck
 580 };
 581
 582 /* PLLB generated USB full speed clock init */
 583 static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
 584 {
 585         /*
 586          * USB clock init:  choose 48 MHz PLLB value,
 587          * disable 48MHz clock during usb peripheral suspend.
 588          *
 589          * REVISIT:  assumes MCK doesn't derive from PLLB!
 590          */
 591         uhpck.parent = &pllb;
 592
 593         at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
 594         pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
 595         if (cpu_is_at91rm9200()) {
 596                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
 597                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
 598                 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
 599         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
 600                    cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
 601                    cpu_is_at91sam9g10()) {
 602                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
 603                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
 604         }
 605         at91_sys_write(AT91_CKGR_PLLBR, 0);
 606
 607         udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 608         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 609 }
 610
 611 /* UPLL generated USB full speed clock init */
 612 static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
 613 {
 614         /*
 615          * USB clock init: choose 480 MHz from UPLL,
 616          */
 617         unsigned int usbr = AT91_PMC_USBS_UPLL;
 618
 619         /* Setup divider by 10 to reach 48 MHz */
 620         usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
 621
 622         at91_sys_write(AT91_PMC_USB, usbr);
 623
 624         /* Now set uhpck values */
 625         uhpck.parent = &utmi_clk;
 626         uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
 627         uhpck.rate_hz = utmi_clk.rate_hz;
 628         uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 629 }
 630
 631 int __init at91_clock_init(unsigned long main_clock)
 632 {
 633         unsigned tmp, freq, mckr;
 634         int i;
 635         int pll_overclock = false;
 636
 637         /*
 638          * When the bootloader initialized the main oscillator correctly,
 639          * there's no problem using the cycle counter.  But if it didn't,
 640          * or when using oscillator bypass mode, we must be told the speed
 641          * of the main clock.
 642          */
 643         if (!main_clock) {
 644                 do {
 645                         tmp = at91_sys_read(AT91_CKGR_MCFR);
 646                 } while (!(tmp & AT91_PMC_MAINRDY));
 647                 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
 648         }
 649         main_clk.rate_hz = main_clock;
 650
 651         /* report if PLLA is more than mildly overclocked */
 652         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
 653         if (cpu_has_300M_plla()) {
 654                 if (plla.rate_hz > 300000000)
 655                         pll_overclock = true;
 656         } else if (cpu_has_800M_plla()) {
 657                 if (plla.rate_hz > 800000000)
 658                         pll_overclock = true;
 659         } else {
 660                 if (plla.rate_hz > 209000000)
 661                         pll_overclock = true;
 662         }
 663         if (pll_overclock)
 664                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 665
 666         if (cpu_is_at91sam9g45()) {
 667                 mckr = at91_sys_read(AT91_PMC_MCKR);
 668                 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));      /* plla divisor by 2 */
 669         }
 670
 671         if (!cpu_has_pllb() && cpu_has_upll()) {
 672                 /* setup UTMI clock as the fourth primary clock
 673                  * (instead of pllb) */
 674                 utmi_clk.type |= CLK_TYPE_PRIMARY;
 675                 utmi_clk.id = 3;
 676         }
 677
 678
 679         /*
 680          * USB HS clock init
 681          */
 682         if (cpu_has_utmi()) {
 683                 /*
 684                  * multiplier is hard-wired to 40
 685                  * (obtain the USB High Speed 480 MHz when input is 12 MHz)
 686                  */
 687                 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
 688         }
 689
 690         /*
 691          * USB FS clock init
 692          */
 693         if (cpu_has_pllb())
 694                 at91_pllb_usbfs_clock_init(main_clock);
 695         if (cpu_has_upll())
 696                 /* assumes that we choose UPLL for USB and not PLLA */
 697                 at91_upll_usbfs_clock_init(main_clock);
 698
 699         /*
 700          * MCK and CPU derive from one of those primary clocks.
 701          * For now, assume this parentage won't change.
 702          */
 703         mckr = at91_sys_read(AT91_PMC_MCKR);
 704         mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
 705         freq = mck.parent->rate_hz;
 706         freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
 707         if (cpu_is_at91rm9200()) {
 708                 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
 709         } else if (cpu_is_at91sam9g20()) {
 710                 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
 711                         freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
 712                 if (mckr & AT91_PMC_PDIV)
 713                         freq /= 2;              /* processor clock division */
 714         } else if (cpu_is_at91sam9g45()) {
 715                 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
 716                         freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
 717         } else {
 718                 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));              /* mdiv */
 719         }
 720
 721         /* Register the PMC's standard clocks */
 722         for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
 723                 at91_clk_add(standard_pmc_clocks[i]);
 724
 725         if (cpu_has_pllb())
 726                 at91_clk_add(&pllb);
 727
 728         if (cpu_has_uhp())
 729                 at91_clk_add(&uhpck);
 730
 731         if (cpu_has_udpfs())
 732                 at91_clk_add(&udpck);
 733
 734         if (cpu_has_utmi())
 735                 at91_clk_add(&utmi_clk);
 736
 737         /* MCK and CPU clock are "always on" */
 738         clk_enable(&mck);
 739
 740         printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
 741                 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
 742                 (unsigned) main_clock / 1000000,
 743                 ((unsigned) main_clock % 1000000) / 1000);
 744
 745         return 0;
 746 }
 747
 748 /*
 749  * Several unused clocks may be active.  Turn them off.
 750  */
 751 static int __init at91_clock_reset(void)
 752 {
 753         unsigned long pcdr = 0;
 754         unsigned long scdr = 0;
 755         struct clk *clk;
 756
 757         list_for_each_entry(clk, &clocks, node) {
 758                 if (clk->users > 0)
 759                         continue;
 760
 761                 if (clk->mode == pmc_periph_mode)
 762                         pcdr |= clk->pmc_mask;
 763
 764                 if (clk->mode == pmc_sys_mode)
 765                         scdr |= clk->pmc_mask;
 766
 767                 pr_debug("Clocks: disable unused %s\n", clk->name);
 768         }
 769
 770         at91_sys_write(AT91_PMC_PCDR, pcdr);
 771         at91_sys_write(AT91_PMC_SCDR, scdr);
 772
 773         return 0;
 774 }
 775 late_initcall(at91_clock_reset);