2 * linux/arch/arm/mach-at91/clock.c
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
17 #include <linux/debugfs.h>
18 #include <linux/seq_file.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/spinlock.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
26 #include <linux/of_address.h>
28 #include <mach/hardware.h>
29 #include <mach/at91_pmc.h>
32 #include <asm/proc-fns.h>
37 void __iomem
*at91_pmc_base
;
38 EXPORT_SYMBOL_GPL(at91_pmc_base
);
41 * There's a lot more which can be done with clocks, including cpufreq
42 * integration, slow clock mode support (for system suspend), letting
43 * PLLB be used at other rates (on boards that don't need USB), etc.
46 #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
47 #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
48 #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
49 #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
53 * Chips have some kind of clocks : group them by functionality
55 #define cpu_has_utmi() ( cpu_is_at91sam9rl() \
56 || cpu_is_at91sam9g45() \
57 || cpu_is_at91sam9x5())
59 #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
60 || cpu_is_at91sam9g45() \
61 || cpu_is_at91sam9x5() \
62 || cpu_is_at91sam9n12())
64 #define cpu_has_300M_plla() (cpu_is_at91sam9g10())
66 #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
67 || cpu_is_at91sam9g45() \
68 || cpu_is_at91sam9x5() \
69 || cpu_is_at91sam9n12()))
71 #define cpu_has_upll() (cpu_is_at91sam9g45() \
72 || cpu_is_at91sam9x5())
74 /* USB host HS & FS */
75 #define cpu_has_uhp() (!cpu_is_at91sam9rl())
77 /* USB device FS only */
78 #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
79 || cpu_is_at91sam9g45() \
80 || cpu_is_at91sam9x5()))
82 #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
83 || cpu_is_at91sam9x5() \
84 || cpu_is_at91sam9n12())
86 #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
87 || cpu_is_at91sam9x5() \
88 || cpu_is_at91sam9n12())
90 #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
91 || cpu_is_at91sam9n12())
93 static LIST_HEAD(clocks
);
94 static DEFINE_SPINLOCK(clk_lock
);
96 static u32 at91_pllb_usb_init
;
99 * Four primary clock sources: two crystal oscillators (32K, main), and
100 * two PLLs. PLLA usually runs the master clock; and PLLB must run at
101 * 48 MHz (unless no USB function clocks are needed). The main clock and
102 * both PLLs are turned off to run in "slow clock mode" (system suspend).
104 static struct clk clk32k
= {
106 .rate_hz
= AT91_SLOW_CLOCK
,
107 .users
= 1, /* always on */
109 .type
= CLK_TYPE_PRIMARY
,
111 static struct clk main_clk
= {
113 .pmc_mask
= AT91_PMC_MOSCS
, /* in PMC_SR */
115 .type
= CLK_TYPE_PRIMARY
,
117 static struct clk plla
= {
120 .pmc_mask
= AT91_PMC_LOCKA
, /* in PMC_SR */
122 .type
= CLK_TYPE_PRIMARY
| CLK_TYPE_PLL
,
125 static void pllb_mode(struct clk
*clk
, int is_on
)
130 is_on
= AT91_PMC_LOCKB
;
131 value
= at91_pllb_usb_init
;
135 // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
136 at91_pmc_write(AT91_CKGR_PLLBR
, value
);
140 } while ((at91_pmc_read(AT91_PMC_SR
) & AT91_PMC_LOCKB
) != is_on
);
143 static struct clk pllb
= {
146 .pmc_mask
= AT91_PMC_LOCKB
, /* in PMC_SR */
149 .type
= CLK_TYPE_PRIMARY
| CLK_TYPE_PLL
,
152 static void pmc_sys_mode(struct clk
*clk
, int is_on
)
155 at91_pmc_write(AT91_PMC_SCER
, clk
->pmc_mask
);
157 at91_pmc_write(AT91_PMC_SCDR
, clk
->pmc_mask
);
160 static void pmc_uckr_mode(struct clk
*clk
, int is_on
)
162 unsigned int uckr
= at91_pmc_read(AT91_CKGR_UCKR
);
165 is_on
= AT91_PMC_LOCKU
;
166 at91_pmc_write(AT91_CKGR_UCKR
, uckr
| clk
->pmc_mask
);
168 at91_pmc_write(AT91_CKGR_UCKR
, uckr
& ~(clk
->pmc_mask
));
172 } while ((at91_pmc_read(AT91_PMC_SR
) & AT91_PMC_LOCKU
) != is_on
);
175 /* USB function clocks (PLLB must be 48 MHz) */
176 static struct clk udpck
= {
179 .mode
= pmc_sys_mode
,
181 struct clk utmi_clk
= {
184 .pmc_mask
= AT91_PMC_UPLLEN
, /* in CKGR_UCKR */
185 .mode
= pmc_uckr_mode
,
186 .type
= CLK_TYPE_PLL
,
188 static struct clk uhpck
= {
190 /*.parent = ... we choose parent at runtime */
191 .mode
= pmc_sys_mode
,
196 * The master clock is divided from the CPU clock (by 1-4). It's used for
197 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
198 * (e.g baud rate generation). It's sourced from one of the primary clocks.
202 .pmc_mask
= AT91_PMC_MCKRDY
, /* in PMC_SR */
205 static void pmc_periph_mode(struct clk
*clk
, int is_on
)
208 at91_pmc_write(AT91_PMC_PCER
, clk
->pmc_mask
);
210 at91_pmc_write(AT91_PMC_PCDR
, clk
->pmc_mask
);
213 static struct clk __init
*at91_css_to_clk(unsigned long css
)
216 case AT91_PMC_CSS_SLOW
:
218 case AT91_PMC_CSS_MAIN
:
220 case AT91_PMC_CSS_PLLA
:
222 case AT91_PMC_CSS_PLLB
:
224 /* CSS_PLLB == CSS_UPLL */
226 else if (cpu_has_pllb())
229 /* alternate PMC: can use master clock */
230 case AT91_PMC_CSS_MASTER
:
237 static int pmc_prescaler_divider(u32 reg
)
239 if (cpu_has_alt_prescaler()) {
240 return 1 << ((reg
& AT91_PMC_ALT_PRES
) >> PMC_ALT_PRES_OFFSET
);
242 return 1 << ((reg
& AT91_PMC_PRES
) >> PMC_PRES_OFFSET
);
246 static void __clk_enable(struct clk
*clk
)
249 __clk_enable(clk
->parent
);
250 if (clk
->users
++ == 0 && clk
->mode
)
254 int clk_enable(struct clk
*clk
)
258 spin_lock_irqsave(&clk_lock
, flags
);
260 spin_unlock_irqrestore(&clk_lock
, flags
);
263 EXPORT_SYMBOL(clk_enable
);
265 static void __clk_disable(struct clk
*clk
)
267 BUG_ON(clk
->users
== 0);
268 if (--clk
->users
== 0 && clk
->mode
)
271 __clk_disable(clk
->parent
);
274 void clk_disable(struct clk
*clk
)
278 spin_lock_irqsave(&clk_lock
, flags
);
280 spin_unlock_irqrestore(&clk_lock
, flags
);
282 EXPORT_SYMBOL(clk_disable
);
284 unsigned long clk_get_rate(struct clk
*clk
)
289 spin_lock_irqsave(&clk_lock
, flags
);
292 if (rate
|| !clk
->parent
)
296 spin_unlock_irqrestore(&clk_lock
, flags
);
299 EXPORT_SYMBOL(clk_get_rate
);
301 /*------------------------------------------------------------------------*/
303 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
306 * For now, only the programmable clocks support reparenting (MCK could
307 * do this too, with care) or rate changing (the PLLs could do this too,
308 * ditto MCK but that's more for cpufreq). Drivers may reparent to get
309 * a better rate match; we don't.
312 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
316 unsigned long actual
;
317 unsigned long prev
= ULONG_MAX
;
319 if (!clk_is_programmable(clk
))
321 spin_lock_irqsave(&clk_lock
, flags
);
323 actual
= clk
->parent
->rate_hz
;
324 for (prescale
= 0; prescale
< 7; prescale
++) {
328 if (actual
&& actual
<= rate
) {
329 if ((prev
- rate
) < (rate
- actual
)) {
338 spin_unlock_irqrestore(&clk_lock
, flags
);
339 return (prescale
< 7) ? actual
: -ENOENT
;
341 EXPORT_SYMBOL(clk_round_rate
);
343 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
347 unsigned long prescale_offset
, css_mask
;
348 unsigned long actual
;
350 if (!clk_is_programmable(clk
))
355 if (cpu_has_alt_prescaler()) {
356 prescale_offset
= PMC_ALT_PRES_OFFSET
;
357 css_mask
= AT91_PMC_ALT_PCKR_CSS
;
359 prescale_offset
= PMC_PRES_OFFSET
;
360 css_mask
= AT91_PMC_CSS
;
363 spin_lock_irqsave(&clk_lock
, flags
);
365 actual
= clk
->parent
->rate_hz
;
366 for (prescale
= 0; prescale
< 7; prescale
++) {
367 if (actual
&& actual
<= rate
) {
370 pckr
= at91_pmc_read(AT91_PMC_PCKR(clk
->id
));
371 pckr
&= css_mask
; /* keep clock selection */
372 pckr
|= prescale
<< prescale_offset
;
373 at91_pmc_write(AT91_PMC_PCKR(clk
->id
), pckr
);
374 clk
->rate_hz
= actual
;
380 spin_unlock_irqrestore(&clk_lock
, flags
);
381 return (prescale
< 7) ? actual
: -ENOENT
;
383 EXPORT_SYMBOL(clk_set_rate
);
385 struct clk
*clk_get_parent(struct clk
*clk
)
389 EXPORT_SYMBOL(clk_get_parent
);
391 int clk_set_parent(struct clk
*clk
, struct clk
*parent
)
397 if (!clk_is_primary(parent
) || !clk_is_programmable(clk
))
400 if (cpu_is_at91sam9rl() && parent
->id
== AT91_PMC_CSS_PLLB
)
403 spin_lock_irqsave(&clk_lock
, flags
);
405 clk
->rate_hz
= parent
->rate_hz
;
406 clk
->parent
= parent
;
407 at91_pmc_write(AT91_PMC_PCKR(clk
->id
), parent
->id
);
409 spin_unlock_irqrestore(&clk_lock
, flags
);
412 EXPORT_SYMBOL(clk_set_parent
);
414 /* establish PCK0..PCKN parentage and rate */
415 static void __init
init_programmable_clock(struct clk
*clk
)
419 unsigned int css_mask
;
421 if (cpu_has_alt_prescaler())
422 css_mask
= AT91_PMC_ALT_PCKR_CSS
;
424 css_mask
= AT91_PMC_CSS
;
426 pckr
= at91_pmc_read(AT91_PMC_PCKR(clk
->id
));
427 parent
= at91_css_to_clk(pckr
& css_mask
);
428 clk
->parent
= parent
;
429 clk
->rate_hz
= parent
->rate_hz
/ pmc_prescaler_divider(pckr
);
432 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
434 /*------------------------------------------------------------------------*/
436 #ifdef CONFIG_DEBUG_FS
438 static int at91_clk_show(struct seq_file
*s
, void *unused
)
440 u32 scsr
, pcsr
, uckr
= 0, sr
;
443 scsr
= at91_pmc_read(AT91_PMC_SCSR
);
444 pcsr
= at91_pmc_read(AT91_PMC_PCSR
);
445 sr
= at91_pmc_read(AT91_PMC_SR
);
446 seq_printf(s
, "SCSR = %8x\n", scsr
);
447 seq_printf(s
, "PCSR = %8x\n", pcsr
);
448 seq_printf(s
, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR
));
449 seq_printf(s
, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR
));
450 seq_printf(s
, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR
));
452 seq_printf(s
, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR
));
453 if (cpu_has_utmi()) {
454 uckr
= at91_pmc_read(AT91_CKGR_UCKR
);
455 seq_printf(s
, "UCKR = %8x\n", uckr
);
457 seq_printf(s
, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR
));
459 seq_printf(s
, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB
));
460 seq_printf(s
, "SR = %8x\n", sr
);
464 list_for_each_entry(clk
, &clocks
, node
) {
467 if (clk
->mode
== pmc_sys_mode
)
468 state
= (scsr
& clk
->pmc_mask
) ? "on" : "off";
469 else if (clk
->mode
== pmc_periph_mode
)
470 state
= (pcsr
& clk
->pmc_mask
) ? "on" : "off";
471 else if (clk
->mode
== pmc_uckr_mode
)
472 state
= (uckr
& clk
->pmc_mask
) ? "on" : "off";
473 else if (clk
->pmc_mask
)
474 state
= (sr
& clk
->pmc_mask
) ? "on" : "off";
475 else if (clk
== &clk32k
|| clk
== &main_clk
)
480 seq_printf(s
, "%-10s users=%2d %-3s %9ld Hz %s\n",
481 clk
->name
, clk
->users
, state
, clk_get_rate(clk
),
482 clk
->parent
? clk
->parent
->name
: "");
487 static int at91_clk_open(struct inode
*inode
, struct file
*file
)
489 return single_open(file
, at91_clk_show
, NULL
);
492 static const struct file_operations at91_clk_operations
= {
493 .open
= at91_clk_open
,
496 .release
= single_release
,
499 static int __init
at91_clk_debugfs_init(void)
501 /* /sys/kernel/debug/at91_clk */
502 (void) debugfs_create_file("at91_clk", S_IFREG
| S_IRUGO
, NULL
, NULL
, &at91_clk_operations
);
506 postcore_initcall(at91_clk_debugfs_init
);
510 /*------------------------------------------------------------------------*/
512 /* Register a new clock */
513 static void __init
at91_clk_add(struct clk
*clk
)
515 list_add_tail(&clk
->node
, &clocks
);
517 clk
->cl
.con_id
= clk
->name
;
519 clkdev_add(&clk
->cl
);
522 int __init
clk_register(struct clk
*clk
)
524 if (clk_is_peripheral(clk
)) {
527 clk
->mode
= pmc_periph_mode
;
529 else if (clk_is_sys(clk
)) {
531 clk
->mode
= pmc_sys_mode
;
533 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
534 else if (clk_is_programmable(clk
)) {
535 clk
->mode
= pmc_sys_mode
;
536 init_programmable_clock(clk
);
545 /*------------------------------------------------------------------------*/
547 static u32 __init
at91_pll_rate(struct clk
*pll
, u32 freq
, u32 reg
)
552 mul
= (reg
>> 16) & 0x7ff;
562 static u32 __init
at91_usb_rate(struct clk
*pll
, u32 freq
, u32 reg
)
564 if (pll
== &pllb
&& (reg
& AT91_PMC_USB96M
))
570 static unsigned __init
at91_pll_calc(unsigned main_freq
, unsigned out_freq
)
572 unsigned i
, div
= 0, mul
= 0, diff
= 1 << 30;
573 unsigned ret
= (out_freq
> 155000000) ? 0xbe00 : 0x3e00;
575 /* PLL output max 240 MHz (or 180 MHz per errata) */
576 if (out_freq
> 240000000)
579 for (i
= 1; i
< 256; i
++) {
581 unsigned input
, mul1
;
584 * PLL input between 1MHz and 32MHz per spec, but lower
585 * frequences seem necessary in some cases so allow 100K.
586 * Warning: some newer products need 2MHz min.
588 input
= main_freq
/ i
;
589 if (cpu_is_at91sam9g20() && input
< 2000000)
593 if (input
> 32000000)
596 mul1
= out_freq
/ input
;
597 if (cpu_is_at91sam9g20() && mul
> 63)
604 diff1
= out_freq
- input
* mul1
;
615 if (i
== 256 && diff
> (out_freq
>> 5))
617 return ret
| ((mul
- 1) << 16) | div
;
622 static struct clk
*const standard_pmc_clocks
[] __initdata
= {
623 /* four primary clocks */
632 /* PLLB generated USB full speed clock init */
633 static void __init
at91_pllb_usbfs_clock_init(unsigned long main_clock
)
636 * USB clock init: choose 48 MHz PLLB value,
637 * disable 48MHz clock during usb peripheral suspend.
639 * REVISIT: assumes MCK doesn't derive from PLLB!
641 uhpck
.parent
= &pllb
;
643 at91_pllb_usb_init
= at91_pll_calc(main_clock
, 48000000 * 2) | AT91_PMC_USB96M
;
644 pllb
.rate_hz
= at91_pll_rate(&pllb
, main_clock
, at91_pllb_usb_init
);
645 if (cpu_is_at91rm9200()) {
646 uhpck
.pmc_mask
= AT91RM9200_PMC_UHP
;
647 udpck
.pmc_mask
= AT91RM9200_PMC_UDP
;
648 at91_pmc_write(AT91_PMC_SCER
, AT91RM9200_PMC_MCKUDP
);
649 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
650 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
651 cpu_is_at91sam9g10()) {
652 uhpck
.pmc_mask
= AT91SAM926x_PMC_UHP
;
653 udpck
.pmc_mask
= AT91SAM926x_PMC_UDP
;
655 at91_pmc_write(AT91_CKGR_PLLBR
, 0);
657 udpck
.rate_hz
= at91_usb_rate(&pllb
, pllb
.rate_hz
, at91_pllb_usb_init
);
658 uhpck
.rate_hz
= at91_usb_rate(&pllb
, pllb
.rate_hz
, at91_pllb_usb_init
);
661 /* UPLL generated USB full speed clock init */
662 static void __init
at91_upll_usbfs_clock_init(unsigned long main_clock
)
665 * USB clock init: choose 480 MHz from UPLL,
667 unsigned int usbr
= AT91_PMC_USBS_UPLL
;
669 /* Setup divider by 10 to reach 48 MHz */
670 usbr
|= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV
;
672 at91_pmc_write(AT91_PMC_USB
, usbr
);
674 /* Now set uhpck values */
675 uhpck
.parent
= &utmi_clk
;
676 uhpck
.pmc_mask
= AT91SAM926x_PMC_UHP
;
677 uhpck
.rate_hz
= utmi_clk
.rate_hz
;
678 uhpck
.rate_hz
/= 1 + ((at91_pmc_read(AT91_PMC_USB
) & AT91_PMC_OHCIUSBDIV
) >> 8);
681 static int __init
at91_pmc_init(unsigned long main_clock
)
683 unsigned tmp
, freq
, mckr
;
685 int pll_overclock
= false;
688 * When the bootloader initialized the main oscillator correctly,
689 * there's no problem using the cycle counter. But if it didn't,
690 * or when using oscillator bypass mode, we must be told the speed
695 tmp
= at91_pmc_read(AT91_CKGR_MCFR
);
696 } while (!(tmp
& AT91_PMC_MAINRDY
));
697 main_clock
= (tmp
& AT91_PMC_MAINF
) * (AT91_SLOW_CLOCK
/ 16);
699 main_clk
.rate_hz
= main_clock
;
701 /* report if PLLA is more than mildly overclocked */
702 plla
.rate_hz
= at91_pll_rate(&plla
, main_clock
, at91_pmc_read(AT91_CKGR_PLLAR
));
703 if (cpu_has_300M_plla()) {
704 if (plla
.rate_hz
> 300000000)
705 pll_overclock
= true;
706 } else if (cpu_has_800M_plla()) {
707 if (plla
.rate_hz
> 800000000)
708 pll_overclock
= true;
710 if (plla
.rate_hz
> 209000000)
711 pll_overclock
= true;
714 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla
.rate_hz
/ 1000000);
716 if (cpu_has_plladiv2()) {
717 mckr
= at91_pmc_read(AT91_PMC_MCKR
);
718 plla
.rate_hz
/= (1 << ((mckr
& AT91_PMC_PLLADIV2
) >> 12)); /* plla divisor by 2 */
721 if (!cpu_has_pllb() && cpu_has_upll()) {
722 /* setup UTMI clock as the fourth primary clock
723 * (instead of pllb) */
724 utmi_clk
.type
|= CLK_TYPE_PRIMARY
;
732 if (cpu_has_utmi()) {
734 * multiplier is hard-wired to 40
735 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
737 utmi_clk
.rate_hz
= 40 * utmi_clk
.parent
->rate_hz
;
739 /* UTMI bias and PLL are managed at the same time */
741 utmi_clk
.pmc_mask
|= AT91_PMC_BIASEN
;
748 at91_pllb_usbfs_clock_init(main_clock
);
750 /* assumes that we choose UPLL for USB and not PLLA */
751 at91_upll_usbfs_clock_init(main_clock
);
754 * MCK and CPU derive from one of those primary clocks.
755 * For now, assume this parentage won't change.
757 mckr
= at91_pmc_read(AT91_PMC_MCKR
);
758 mck
.parent
= at91_css_to_clk(mckr
& AT91_PMC_CSS
);
759 freq
= mck
.parent
->rate_hz
;
760 freq
/= pmc_prescaler_divider(mckr
); /* prescale */
761 if (cpu_is_at91rm9200()) {
762 mck
.rate_hz
= freq
/ (1 + ((mckr
& AT91_PMC_MDIV
) >> 8)); /* mdiv */
763 } else if (cpu_is_at91sam9g20()) {
764 mck
.rate_hz
= (mckr
& AT91_PMC_MDIV
) ?
765 freq
/ ((mckr
& AT91_PMC_MDIV
) >> 7) : freq
; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
766 if (mckr
& AT91_PMC_PDIV
)
767 freq
/= 2; /* processor clock division */
768 } else if (cpu_has_mdiv3()) {
769 mck
.rate_hz
= (mckr
& AT91_PMC_MDIV
) == AT91SAM9_PMC_MDIV_3
?
770 freq
/ 3 : freq
/ (1 << ((mckr
& AT91_PMC_MDIV
) >> 8)); /* mdiv */
772 mck
.rate_hz
= freq
/ (1 << ((mckr
& AT91_PMC_MDIV
) >> 8)); /* mdiv */
775 if (cpu_has_alt_prescaler()) {
776 /* Programmable clocks can use MCK */
777 mck
.type
|= CLK_TYPE_PRIMARY
;
781 /* Register the PMC's standard clocks */
782 for (i
= 0; i
< ARRAY_SIZE(standard_pmc_clocks
); i
++)
783 at91_clk_add(standard_pmc_clocks
[i
]);
789 at91_clk_add(&uhpck
);
792 at91_clk_add(&udpck
);
795 at91_clk_add(&utmi_clk
);
797 /* MCK and CPU clock are "always on" */
800 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
801 freq
/ 1000000, (unsigned) mck
.rate_hz
/ 1000000,
802 (unsigned) main_clock
/ 1000000,
803 ((unsigned) main_clock
% 1000000) / 1000);
808 #if defined(CONFIG_OF)
809 static struct of_device_id pmc_ids
[] = {
810 { .compatible
= "atmel,at91rm9200-pmc" },
814 static struct of_device_id osc_ids
[] = {
815 { .compatible
= "atmel,osc" },
819 int __init
at91_dt_clock_init(void)
821 struct device_node
*np
;
824 np
= of_find_matching_node(NULL
, pmc_ids
);
826 panic("unable to find compatible pmc node in dtb\n");
828 at91_pmc_base
= of_iomap(np
, 0);
830 panic("unable to map pmc cpu registers\n");
834 /* retrieve the freqency of fixed clocks from device tree */
835 np
= of_find_matching_node(NULL
, osc_ids
);
838 if (!of_property_read_u32(np
, "clock-frequency", &rate
))
844 return at91_pmc_init(main_clock
);
848 int __init
at91_clock_init(unsigned long main_clock
)
850 at91_pmc_base
= ioremap(AT91_PMC
, 256);
852 panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC
);
854 return at91_pmc_init(main_clock
);
858 * Several unused clocks may be active. Turn them off.
860 static int __init
at91_clock_reset(void)
862 unsigned long pcdr
= 0;
863 unsigned long scdr
= 0;
866 list_for_each_entry(clk
, &clocks
, node
) {
870 if (clk
->mode
== pmc_periph_mode
)
871 pcdr
|= clk
->pmc_mask
;
873 if (clk
->mode
== pmc_sys_mode
)
874 scdr
|= clk
->pmc_mask
;
876 pr_debug("Clocks: disable unused %s\n", clk
->name
);
879 at91_pmc_write(AT91_PMC_PCDR
, pcdr
);
880 at91_pmc_write(AT91_PMC_SCDR
, scdr
);
884 late_initcall(at91_clock_reset
);
886 void at91sam9_idle(void)
888 at91_pmc_write(AT91_PMC_SCDR
, AT91_PMC_PCK
);