arch/arm/mach-at91/clock.c

   1 /*
   2  * linux/arch/arm/mach-at91/clock.c
   3  *
   4  * Copyright (C) 2005 David Brownell
   5  * Copyright (C) 2005 Ivan Kokshaysky
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/fs.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/list.h>
  20 #include <linux/errno.h>
  21 #include <linux/err.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26 #include <linux/of_address.h>
  27
  28 #include <mach/hardware.h>
  29 #include <mach/at91_pmc.h>
  30 #include <mach/cpu.h>
  31
  32 #include <asm/proc-fns.h>
  33
  34 #include "clock.h"
  35 #include "generic.h"
  36
  37 void __iomem *at91_pmc_base;
  38 EXPORT_SYMBOL_GPL(at91_pmc_base);
  39
  40 /*
  41  * There's a lot more which can be done with clocks, including cpufreq
  42  * integration, slow clock mode support (for system suspend), letting
  43  * PLLB be used at other rates (on boards that don't need USB), etc.
  44  */
  45
  46 #define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
  47 #define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
  48 #define clk_is_peripheral(x)    ((x)->type & CLK_TYPE_PERIPHERAL)
  49 #define clk_is_sys(x)           ((x)->type & CLK_TYPE_SYSTEM)
  50
  51
  52 /*
  53  * Chips have some kind of clocks : group them by functionality
  54  */
  55 #define cpu_has_utmi()          (  cpu_is_at91sam9rl() \
  56                                 || cpu_is_at91sam9g45() \
  57                                 || cpu_is_at91sam9x5())
  58
  59 #define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
  60                                 || cpu_is_at91sam9g45() \
  61                                 || cpu_is_at91sam9x5() \
  62                                 || cpu_is_at91sam9n12())
  63
  64 #define cpu_has_300M_plla()     (cpu_is_at91sam9g10())
  65
  66 #define cpu_has_240M_plla()     (cpu_is_at91sam9261() \
  67                                 || cpu_is_at91sam9263() \
  68                                 || cpu_is_at91sam9rl())
  69
  70 #define cpu_has_210M_plla()     (cpu_is_at91sam9260())
  71
  72 #define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
  73                                 || cpu_is_at91sam9g45() \
  74                                 || cpu_is_at91sam9x5() \
  75                                 || cpu_is_at91sam9n12()))
  76
  77 #define cpu_has_upll()          (cpu_is_at91sam9g45() \
  78                                 || cpu_is_at91sam9x5())
  79
  80 /* USB host HS & FS */
  81 #define cpu_has_uhp()           (!cpu_is_at91sam9rl())
  82
  83 /* USB device FS only */
  84 #define cpu_has_udpfs()         (!(cpu_is_at91sam9rl() \
  85                                 || cpu_is_at91sam9g45() \
  86                                 || cpu_is_at91sam9x5()))
  87
  88 #define cpu_has_plladiv2()      (cpu_is_at91sam9g45() \
  89                                 || cpu_is_at91sam9x5() \
  90                                 || cpu_is_at91sam9n12())
  91
  92 #define cpu_has_mdiv3()         (cpu_is_at91sam9g45() \
  93                                 || cpu_is_at91sam9x5() \
  94                                 || cpu_is_at91sam9n12())
  95
  96 #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
  97                                 || cpu_is_at91sam9n12())
  98
  99 static LIST_HEAD(clocks);
 100 static DEFINE_SPINLOCK(clk_lock);
 101
 102 static u32 at91_pllb_usb_init;
 103
 104 /*
 105  * Four primary clock sources:  two crystal oscillators (32K, main), and
 106  * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
 107  * 48 MHz (unless no USB function clocks are needed).  The main clock and
 108  * both PLLs are turned off to run in "slow clock mode" (system suspend).
 109  */
 110 static struct clk clk32k = {
 111         .name           = "clk32k",
 112         .rate_hz        = AT91_SLOW_CLOCK,
 113         .users          = 1,            /* always on */
 114         .id             = 0,
 115         .type           = CLK_TYPE_PRIMARY,
 116 };
 117 static struct clk main_clk = {
 118         .name           = "main",
 119         .pmc_mask       = AT91_PMC_MOSCS,       /* in PMC_SR */
 120         .id             = 1,
 121         .type           = CLK_TYPE_PRIMARY,
 122 };
 123 static struct clk plla = {
 124         .name           = "plla",
 125         .parent         = &main_clk,
 126         .pmc_mask       = AT91_PMC_LOCKA,       /* in PMC_SR */
 127         .id             = 2,
 128         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
 129 };
 130
 131 static void pllb_mode(struct clk *clk, int is_on)
 132 {
 133         u32     value;
 134
 135         if (is_on) {
 136                 is_on = AT91_PMC_LOCKB;
 137                 value = at91_pllb_usb_init;
 138         } else
 139                 value = 0;
 140
 141         // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
 142         at91_pmc_write(AT91_CKGR_PLLBR, value);
 143
 144         do {
 145                 cpu_relax();
 146         } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
 147 }
 148
 149 static struct clk pllb = {
 150         .name           = "pllb",
 151         .parent         = &main_clk,
 152         .pmc_mask       = AT91_PMC_LOCKB,       /* in PMC_SR */
 153         .mode           = pllb_mode,
 154         .id             = 3,
 155         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
 156 };
 157
 158 static void pmc_sys_mode(struct clk *clk, int is_on)
 159 {
 160         if (is_on)
 161                 at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
 162         else
 163                 at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
 164 }
 165
 166 static void pmc_uckr_mode(struct clk *clk, int is_on)
 167 {
 168         unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
 169
 170         if (is_on) {
 171                 is_on = AT91_PMC_LOCKU;
 172                 at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
 173         } else
 174                 at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
 175
 176         do {
 177                 cpu_relax();
 178         } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
 179 }
 180
 181 /* USB function clocks (PLLB must be 48 MHz) */
 182 static struct clk udpck = {
 183         .name           = "udpck",
 184         .parent         = &pllb,
 185         .mode           = pmc_sys_mode,
 186 };
 187 struct clk utmi_clk = {
 188         .name           = "utmi_clk",
 189         .parent         = &main_clk,
 190         .pmc_mask       = AT91_PMC_UPLLEN,      /* in CKGR_UCKR */
 191         .mode           = pmc_uckr_mode,
 192         .type           = CLK_TYPE_PLL,
 193 };
 194 static struct clk uhpck = {
 195         .name           = "uhpck",
 196         /*.parent               = ... we choose parent at runtime */
 197         .mode           = pmc_sys_mode,
 198 };
 199
 200
 201 /*
 202  * The master clock is divided from the CPU clock (by 1-4).  It's used for
 203  * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
 204  * (e.g baud rate generation).  It's sourced from one of the primary clocks.
 205  */
 206 struct clk mck = {
 207         .name           = "mck",
 208         .pmc_mask       = AT91_PMC_MCKRDY,      /* in PMC_SR */
 209 };
 210
 211 static void pmc_periph_mode(struct clk *clk, int is_on)
 212 {
 213         if (is_on)
 214                 at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
 215         else
 216                 at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
 217 }
 218
 219 static struct clk __init *at91_css_to_clk(unsigned long css)
 220 {
 221         switch (css) {
 222                 case AT91_PMC_CSS_SLOW:
 223                         return &clk32k;
 224                 case AT91_PMC_CSS_MAIN:
 225                         return &main_clk;
 226                 case AT91_PMC_CSS_PLLA:
 227                         return &plla;
 228                 case AT91_PMC_CSS_PLLB:
 229                         if (cpu_has_upll())
 230                                 /* CSS_PLLB == CSS_UPLL */
 231                                 return &utmi_clk;
 232                         else if (cpu_has_pllb())
 233                                 return &pllb;
 234                         break;
 235                 /* alternate PMC: can use master clock */
 236                 case AT91_PMC_CSS_MASTER:
 237                         return &mck;
 238         }
 239
 240         return NULL;
 241 }
 242
 243 static int pmc_prescaler_divider(u32 reg)
 244 {
 245         if (cpu_has_alt_prescaler()) {
 246                 return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
 247         } else {
 248                 return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
 249         }
 250 }
 251
 252 static void __clk_enable(struct clk *clk)
 253 {
 254         if (clk->parent)
 255                 __clk_enable(clk->parent);
 256         if (clk->users++ == 0 && clk->mode)
 257                 clk->mode(clk, 1);
 258 }
 259
 260 int clk_enable(struct clk *clk)
 261 {
 262         unsigned long   flags;
 263
 264         spin_lock_irqsave(&clk_lock, flags);
 265         __clk_enable(clk);
 266         spin_unlock_irqrestore(&clk_lock, flags);
 267         return 0;
 268 }
 269 EXPORT_SYMBOL(clk_enable);
 270
 271 static void __clk_disable(struct clk *clk)
 272 {
 273         BUG_ON(clk->users == 0);
 274         if (--clk->users == 0 && clk->mode)
 275                 clk->mode(clk, 0);
 276         if (clk->parent)
 277                 __clk_disable(clk->parent);
 278 }
 279
 280 void clk_disable(struct clk *clk)
 281 {
 282         unsigned long   flags;
 283
 284         spin_lock_irqsave(&clk_lock, flags);
 285         __clk_disable(clk);
 286         spin_unlock_irqrestore(&clk_lock, flags);
 287 }
 288 EXPORT_SYMBOL(clk_disable);
 289
 290 unsigned long clk_get_rate(struct clk *clk)
 291 {
 292         unsigned long   flags;
 293         unsigned long   rate;
 294
 295         spin_lock_irqsave(&clk_lock, flags);
 296         for (;;) {
 297                 rate = clk->rate_hz;
 298                 if (rate || !clk->parent)
 299                         break;
 300                 clk = clk->parent;
 301         }
 302         spin_unlock_irqrestore(&clk_lock, flags);
 303         return rate;
 304 }
 305 EXPORT_SYMBOL(clk_get_rate);
 306
 307 /*------------------------------------------------------------------------*/
 308
 309 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 310
 311 /*
 312  * For now, only the programmable clocks support reparenting (MCK could
 313  * do this too, with care) or rate changing (the PLLs could do this too,
 314  * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
 315  * a better rate match; we don't.
 316  */
 317
 318 long clk_round_rate(struct clk *clk, unsigned long rate)
 319 {
 320         unsigned long   flags;
 321         unsigned        prescale;
 322         unsigned long   actual;
 323         unsigned long   prev = ULONG_MAX;
 324
 325         if (!clk_is_programmable(clk))
 326                 return -EINVAL;
 327         spin_lock_irqsave(&clk_lock, flags);
 328
 329         actual = clk->parent->rate_hz;
 330         for (prescale = 0; prescale < 7; prescale++) {
 331                 if (actual > rate)
 332                         prev = actual;
 333
 334                 if (actual && actual <= rate) {
 335                         if ((prev - rate) < (rate - actual)) {
 336                                 actual = prev;
 337                                 prescale--;
 338                         }
 339                         break;
 340                 }
 341                 actual >>= 1;
 342         }
 343
 344         spin_unlock_irqrestore(&clk_lock, flags);
 345         return (prescale < 7) ? actual : -ENOENT;
 346 }
 347 EXPORT_SYMBOL(clk_round_rate);
 348
 349 int clk_set_rate(struct clk *clk, unsigned long rate)
 350 {
 351         unsigned long   flags;
 352         unsigned        prescale;
 353         unsigned long   prescale_offset, css_mask;
 354         unsigned long   actual;
 355
 356         if (!clk_is_programmable(clk))
 357                 return -EINVAL;
 358         if (clk->users)
 359                 return -EBUSY;
 360
 361         if (cpu_has_alt_prescaler()) {
 362                 prescale_offset = PMC_ALT_PRES_OFFSET;
 363                 css_mask = AT91_PMC_ALT_PCKR_CSS;
 364         } else {
 365                 prescale_offset = PMC_PRES_OFFSET;
 366                 css_mask = AT91_PMC_CSS;
 367         }
 368
 369         spin_lock_irqsave(&clk_lock, flags);
 370
 371         actual = clk->parent->rate_hz;
 372         for (prescale = 0; prescale < 7; prescale++) {
 373                 if (actual && actual <= rate) {
 374                         u32     pckr;
 375
 376                         pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
 377                         pckr &= css_mask;       /* keep clock selection */
 378                         pckr |= prescale << prescale_offset;
 379                         at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
 380                         clk->rate_hz = actual;
 381                         break;
 382                 }
 383                 actual >>= 1;
 384         }
 385
 386         spin_unlock_irqrestore(&clk_lock, flags);
 387         return (prescale < 7) ? actual : -ENOENT;
 388 }
 389 EXPORT_SYMBOL(clk_set_rate);
 390
 391 struct clk *clk_get_parent(struct clk *clk)
 392 {
 393         return clk->parent;
 394 }
 395 EXPORT_SYMBOL(clk_get_parent);
 396
 397 int clk_set_parent(struct clk *clk, struct clk *parent)
 398 {
 399         unsigned long   flags;
 400
 401         if (clk->users)
 402                 return -EBUSY;
 403         if (!clk_is_primary(parent) || !clk_is_programmable(clk))
 404                 return -EINVAL;
 405
 406         if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
 407                 return -EINVAL;
 408
 409         spin_lock_irqsave(&clk_lock, flags);
 410
 411         clk->rate_hz = parent->rate_hz;
 412         clk->parent = parent;
 413         at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
 414
 415         spin_unlock_irqrestore(&clk_lock, flags);
 416         return 0;
 417 }
 418 EXPORT_SYMBOL(clk_set_parent);
 419
 420 /* establish PCK0..PCKN parentage and rate */
 421 static void __init init_programmable_clock(struct clk *clk)
 422 {
 423         struct clk      *parent;
 424         u32             pckr;
 425         unsigned int    css_mask;
 426
 427         if (cpu_has_alt_prescaler())
 428                 css_mask = AT91_PMC_ALT_PCKR_CSS;
 429         else
 430                 css_mask = AT91_PMC_CSS;
 431
 432         pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
 433         parent = at91_css_to_clk(pckr & css_mask);
 434         clk->parent = parent;
 435         clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
 436 }
 437
 438 #endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
 439
 440 /*------------------------------------------------------------------------*/
 441
 442 #ifdef CONFIG_DEBUG_FS
 443
 444 static int at91_clk_show(struct seq_file *s, void *unused)
 445 {
 446         u32             scsr, pcsr, uckr = 0, sr;
 447         struct clk      *clk;
 448
 449         scsr = at91_pmc_read(AT91_PMC_SCSR);
 450         pcsr = at91_pmc_read(AT91_PMC_PCSR);
 451         sr = at91_pmc_read(AT91_PMC_SR);
 452         seq_printf(s, "SCSR = %8x\n", scsr);
 453         seq_printf(s, "PCSR = %8x\n", pcsr);
 454         seq_printf(s, "MOR  = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
 455         seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
 456         seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
 457         if (cpu_has_pllb())
 458                 seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
 459         if (cpu_has_utmi()) {
 460                 uckr = at91_pmc_read(AT91_CKGR_UCKR);
 461                 seq_printf(s, "UCKR = %8x\n", uckr);
 462         }
 463         seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
 464         if (cpu_has_upll())
 465                 seq_printf(s, "USB  = %8x\n", at91_pmc_read(AT91_PMC_USB));
 466         seq_printf(s, "SR   = %8x\n", sr);
 467
 468         seq_printf(s, "\n");
 469
 470         list_for_each_entry(clk, &clocks, node) {
 471                 char    *state;
 472
 473                 if (clk->mode == pmc_sys_mode)
 474                         state = (scsr & clk->pmc_mask) ? "on" : "off";
 475                 else if (clk->mode == pmc_periph_mode)
 476                         state = (pcsr & clk->pmc_mask) ? "on" : "off";
 477                 else if (clk->mode == pmc_uckr_mode)
 478                         state = (uckr & clk->pmc_mask) ? "on" : "off";
 479                 else if (clk->pmc_mask)
 480                         state = (sr & clk->pmc_mask) ? "on" : "off";
 481                 else if (clk == &clk32k || clk == &main_clk)
 482                         state = "on";
 483                 else
 484                         state = "";
 485
 486                 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
 487                         clk->name, clk->users, state, clk_get_rate(clk),
 488                         clk->parent ? clk->parent->name : "");
 489         }
 490         return 0;
 491 }
 492
 493 static int at91_clk_open(struct inode *inode, struct file *file)
 494 {
 495         return single_open(file, at91_clk_show, NULL);
 496 }
 497
 498 static const struct file_operations at91_clk_operations = {
 499         .open           = at91_clk_open,
 500         .read           = seq_read,
 501         .llseek         = seq_lseek,
 502         .release        = single_release,
 503 };
 504
 505 static int __init at91_clk_debugfs_init(void)
 506 {
 507         /* /sys/kernel/debug/at91_clk */
 508         (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
 509
 510         return 0;
 511 }
 512 postcore_initcall(at91_clk_debugfs_init);
 513
 514 #endif
 515
 516 /*------------------------------------------------------------------------*/
 517
 518 /* Register a new clock */
 519 static void __init at91_clk_add(struct clk *clk)
 520 {
 521         list_add_tail(&clk->node, &clocks);
 522
 523         clk->cl.con_id = clk->name;
 524         clk->cl.clk = clk;
 525         clkdev_add(&clk->cl);
 526 }
 527
 528 int __init clk_register(struct clk *clk)
 529 {
 530         if (clk_is_peripheral(clk)) {
 531                 if (!clk->parent)
 532                         clk->parent = &mck;
 533                 clk->mode = pmc_periph_mode;
 534         }
 535         else if (clk_is_sys(clk)) {
 536                 clk->parent = &mck;
 537                 clk->mode = pmc_sys_mode;
 538         }
 539 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 540         else if (clk_is_programmable(clk)) {
 541                 clk->mode = pmc_sys_mode;
 542                 init_programmable_clock(clk);
 543         }
 544 #endif
 545
 546         at91_clk_add(clk);
 547
 548         return 0;
 549 }
 550
 551 /*------------------------------------------------------------------------*/
 552
 553 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
 554 {
 555         unsigned mul, div;
 556
 557         div = reg & 0xff;
 558         mul = (reg >> 16) & 0x7ff;
 559         if (div && mul) {
 560                 freq /= div;
 561                 freq *= mul + 1;
 562         } else
 563                 freq = 0;
 564
 565         return freq;
 566 }
 567
 568 static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
 569 {
 570         if (pll == &pllb && (reg & AT91_PMC_USB96M))
 571                 return freq / 2;
 572         else
 573                 return freq;
 574 }
 575
 576 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
 577 {
 578         unsigned i, div = 0, mul = 0, diff = 1 << 30;
 579         unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
 580
 581         /* PLL output max 240 MHz (or 180 MHz per errata) */
 582         if (out_freq > 240000000)
 583                 goto fail;
 584
 585         for (i = 1; i < 256; i++) {
 586                 int diff1;
 587                 unsigned input, mul1;
 588
 589                 /*
 590                  * PLL input between 1MHz and 32MHz per spec, but lower
 591                  * frequences seem necessary in some cases so allow 100K.
 592                  * Warning: some newer products need 2MHz min.
 593                  */
 594                 input = main_freq / i;
 595                 if (cpu_is_at91sam9g20() && input < 2000000)
 596                         continue;
 597                 if (input < 100000)
 598                         continue;
 599                 if (input > 32000000)
 600                         continue;
 601
 602                 mul1 = out_freq / input;
 603                 if (cpu_is_at91sam9g20() && mul > 63)
 604                         continue;
 605                 if (mul1 > 2048)
 606                         continue;
 607                 if (mul1 < 2)
 608                         goto fail;
 609
 610                 diff1 = out_freq - input * mul1;
 611                 if (diff1 < 0)
 612                         diff1 = -diff1;
 613                 if (diff > diff1) {
 614                         diff = diff1;
 615                         div = i;
 616                         mul = mul1;
 617                         if (diff == 0)
 618                                 break;
 619                 }
 620         }
 621         if (i == 256 && diff > (out_freq >> 5))
 622                 goto fail;
 623         return ret | ((mul - 1) << 16) | div;
 624 fail:
 625         return 0;
 626 }
 627
 628 static struct clk *const standard_pmc_clocks[] __initdata = {
 629         /* four primary clocks */
 630         &clk32k,
 631         &main_clk,
 632         &plla,
 633
 634         /* MCK */
 635         &mck
 636 };
 637
 638 /* PLLB generated USB full speed clock init */
 639 static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
 640 {
 641         /*
 642          * USB clock init:  choose 48 MHz PLLB value,
 643          * disable 48MHz clock during usb peripheral suspend.
 644          *
 645          * REVISIT:  assumes MCK doesn't derive from PLLB!
 646          */
 647         uhpck.parent = &pllb;
 648
 649         at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
 650         pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
 651         if (cpu_is_at91rm9200()) {
 652                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
 653                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
 654                 at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
 655         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
 656                    cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
 657                    cpu_is_at91sam9g10()) {
 658                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
 659                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
 660         }
 661         at91_pmc_write(AT91_CKGR_PLLBR, 0);
 662
 663         udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 664         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 665 }
 666
 667 /* UPLL generated USB full speed clock init */
 668 static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
 669 {
 670         /*
 671          * USB clock init: choose 480 MHz from UPLL,
 672          */
 673         unsigned int usbr = AT91_PMC_USBS_UPLL;
 674
 675         /* Setup divider by 10 to reach 48 MHz */
 676         usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
 677
 678         at91_pmc_write(AT91_PMC_USB, usbr);
 679
 680         /* Now set uhpck values */
 681         uhpck.parent = &utmi_clk;
 682         uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
 683         uhpck.rate_hz = utmi_clk.rate_hz;
 684         uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 685 }
 686
 687 static int __init at91_pmc_init(unsigned long main_clock)
 688 {
 689         unsigned tmp, freq, mckr;
 690         int i;
 691         int pll_overclock = false;
 692
 693         /*
 694          * When the bootloader initialized the main oscillator correctly,
 695          * there's no problem using the cycle counter.  But if it didn't,
 696          * or when using oscillator bypass mode, we must be told the speed
 697          * of the main clock.
 698          */
 699         if (!main_clock) {
 700                 do {
 701                         tmp = at91_pmc_read(AT91_CKGR_MCFR);
 702                 } while (!(tmp & AT91_PMC_MAINRDY));
 703                 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
 704         }
 705         main_clk.rate_hz = main_clock;
 706
 707         /* report if PLLA is more than mildly overclocked */
 708         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
 709         if (cpu_has_300M_plla()) {
 710                 if (plla.rate_hz > 300000000)
 711                         pll_overclock = true;
 712         } else if (cpu_has_800M_plla()) {
 713                 if (plla.rate_hz > 800000000)
 714                         pll_overclock = true;
 715         } else if (cpu_has_240M_plla()) {
 716                 if (plla.rate_hz > 240000000)
 717                         pll_overclock = true;
 718         } else if (cpu_has_210M_plla()) {
 719                 if (plla.rate_hz > 210000000)
 720                         pll_overclock = true;
 721         } else {
 722                 if (plla.rate_hz > 209000000)
 723                         pll_overclock = true;
 724         }
 725         if (pll_overclock)
 726                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 727
 728         if (cpu_has_plladiv2()) {
 729                 mckr = at91_pmc_read(AT91_PMC_MCKR);
 730                 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));      /* plla divisor by 2 */
 731         }
 732
 733         if (!cpu_has_pllb() && cpu_has_upll()) {
 734                 /* setup UTMI clock as the fourth primary clock
 735                  * (instead of pllb) */
 736                 utmi_clk.type |= CLK_TYPE_PRIMARY;
 737                 utmi_clk.id = 3;
 738         }
 739
 740
 741         /*
 742          * USB HS clock init
 743          */
 744         if (cpu_has_utmi()) {
 745                 /*
 746                  * multiplier is hard-wired to 40
 747                  * (obtain the USB High Speed 480 MHz when input is 12 MHz)
 748                  */
 749                 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
 750
 751                 /* UTMI bias and PLL are managed at the same time */
 752                 if (cpu_has_upll())
 753                         utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
 754         }
 755
 756         /*
 757          * USB FS clock init
 758          */
 759         if (cpu_has_pllb())
 760                 at91_pllb_usbfs_clock_init(main_clock);
 761         if (cpu_has_upll())
 762                 /* assumes that we choose UPLL for USB and not PLLA */
 763                 at91_upll_usbfs_clock_init(main_clock);
 764
 765         /*
 766          * MCK and CPU derive from one of those primary clocks.
 767          * For now, assume this parentage won't change.
 768          */
 769         mckr = at91_pmc_read(AT91_PMC_MCKR);
 770         mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
 771         freq = mck.parent->rate_hz;
 772         freq /= pmc_prescaler_divider(mckr);                                    /* prescale */
 773         if (cpu_is_at91rm9200()) {
 774                 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
 775         } else if (cpu_is_at91sam9g20()) {
 776                 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
 777                         freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
 778                 if (mckr & AT91_PMC_PDIV)
 779                         freq /= 2;              /* processor clock division */
 780         } else if (cpu_has_mdiv3()) {
 781                 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
 782                         freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
 783         } else {
 784                 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));              /* mdiv */
 785         }
 786
 787         if (cpu_has_alt_prescaler()) {
 788                 /* Programmable clocks can use MCK */
 789                 mck.type |= CLK_TYPE_PRIMARY;
 790                 mck.id = 4;
 791         }
 792
 793         /* Register the PMC's standard clocks */
 794         for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
 795                 at91_clk_add(standard_pmc_clocks[i]);
 796
 797         if (cpu_has_pllb())
 798                 at91_clk_add(&pllb);
 799
 800         if (cpu_has_uhp())
 801                 at91_clk_add(&uhpck);
 802
 803         if (cpu_has_udpfs())
 804                 at91_clk_add(&udpck);
 805
 806         if (cpu_has_utmi())
 807                 at91_clk_add(&utmi_clk);
 808
 809         /* MCK and CPU clock are "always on" */
 810         clk_enable(&mck);
 811
 812         printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
 813                 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
 814                 (unsigned) main_clock / 1000000,
 815                 ((unsigned) main_clock % 1000000) / 1000);
 816
 817         return 0;
 818 }
 819
 820 #if defined(CONFIG_OF)
 821 static struct of_device_id pmc_ids[] = {
 822         { .compatible = "atmel,at91rm9200-pmc" },
 823         { /*sentinel*/ }
 824 };
 825
 826 static struct of_device_id osc_ids[] = {
 827         { .compatible = "atmel,osc" },
 828         { /*sentinel*/ }
 829 };
 830
 831 int __init at91_dt_clock_init(void)
 832 {
 833         struct device_node *np;
 834         u32 main_clock = 0;
 835
 836         np = of_find_matching_node(NULL, pmc_ids);
 837         if (!np)
 838                 panic("unable to find compatible pmc node in dtb\n");
 839
 840         at91_pmc_base = of_iomap(np, 0);
 841         if (!at91_pmc_base)
 842                 panic("unable to map pmc cpu registers\n");
 843
 844         of_node_put(np);
 845
 846         /* retrieve the freqency of fixed clocks from device tree */
 847         np = of_find_matching_node(NULL, osc_ids);
 848         if (np) {
 849                 u32 rate;
 850                 if (!of_property_read_u32(np, "clock-frequency", &rate))
 851                         main_clock = rate;
 852         }
 853
 854         of_node_put(np);
 855
 856         return at91_pmc_init(main_clock);
 857 }
 858 #endif
 859
 860 int __init at91_clock_init(unsigned long main_clock)
 861 {
 862         at91_pmc_base = ioremap(AT91_PMC, 256);
 863         if (!at91_pmc_base)
 864                 panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
 865
 866         return at91_pmc_init(main_clock);
 867 }
 868
 869 /*
 870  * Several unused clocks may be active.  Turn them off.
 871  */
 872 static int __init at91_clock_reset(void)
 873 {
 874         unsigned long pcdr = 0;
 875         unsigned long scdr = 0;
 876         struct clk *clk;
 877
 878         list_for_each_entry(clk, &clocks, node) {
 879                 if (clk->users > 0)
 880                         continue;
 881
 882                 if (clk->mode == pmc_periph_mode)
 883                         pcdr |= clk->pmc_mask;
 884
 885                 if (clk->mode == pmc_sys_mode)
 886                         scdr |= clk->pmc_mask;
 887
 888                 pr_debug("Clocks: disable unused %s\n", clk->name);
 889         }
 890
 891         at91_pmc_write(AT91_PMC_PCDR, pcdr);
 892         at91_pmc_write(AT91_PMC_SCDR, scdr);
 893
 894         return 0;
 895 }
 896 late_initcall(at91_clock_reset);
 897
 898 void at91sam9_idle(void)
 899 {
 900         at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 901         cpu_do_idle();
 902 }