2 * linux/arch/arm/mach-at91/gpio.c
4 * Copyright (C) 2005 HP Labs
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/clk.h>
13 #include <linux/errno.h>
14 #include <linux/device.h>
15 #include <linux/gpio.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/debugfs.h>
19 #include <linux/seq_file.h>
20 #include <linux/kernel.h>
21 #include <linux/list.h>
22 #include <linux/module.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_gpio.h>
29 #include <mach/hardware.h>
30 #include <mach/at91_pio.h>
34 struct at91_gpio_chip
{
35 struct gpio_chip chip
;
36 struct at91_gpio_chip
*next
; /* Bank sharing same clock */
37 int pioc_hwirq
; /* PIO bank interrupt identifier on AIC */
38 int pioc_virq
; /* PIO bank Linux virtual interrupt */
39 int pioc_idx
; /* PIO bank index */
40 void __iomem
*regbase
; /* PIO bank virtual address */
41 struct clk
*clock
; /* associated clock */
42 struct irq_domain
*domain
; /* associated irq domain */
45 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
47 static void at91_gpiolib_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
);
48 static void at91_gpiolib_set(struct gpio_chip
*chip
, unsigned offset
, int val
);
49 static int at91_gpiolib_get(struct gpio_chip
*chip
, unsigned offset
);
50 static int at91_gpiolib_direction_output(struct gpio_chip
*chip
,
51 unsigned offset
, int val
);
52 static int at91_gpiolib_direction_input(struct gpio_chip
*chip
,
54 static int at91_gpiolib_to_irq(struct gpio_chip
*chip
, unsigned offset
);
56 #define AT91_GPIO_CHIP(name, nr_gpio) \
60 .direction_input = at91_gpiolib_direction_input, \
61 .direction_output = at91_gpiolib_direction_output, \
62 .get = at91_gpiolib_get, \
63 .set = at91_gpiolib_set, \
64 .dbg_show = at91_gpiolib_dbg_show, \
65 .to_irq = at91_gpiolib_to_irq, \
70 static struct at91_gpio_chip gpio_chip
[] = {
71 AT91_GPIO_CHIP("pioA", 32),
72 AT91_GPIO_CHIP("pioB", 32),
73 AT91_GPIO_CHIP("pioC", 32),
74 AT91_GPIO_CHIP("pioD", 32),
75 AT91_GPIO_CHIP("pioE", 32),
78 static int gpio_banks
;
79 static unsigned long at91_gpio_caps
;
81 /* All PIO controllers support PIO3 features */
82 #define AT91_GPIO_CAP_PIO3 (1 << 0)
84 #define has_pio3() (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
86 /*--------------------------------------------------------------------------*/
88 static inline void __iomem
*pin_to_controller(unsigned pin
)
91 if (likely(pin
< gpio_banks
))
92 return gpio_chip
[pin
].regbase
;
97 static inline unsigned pin_to_mask(unsigned pin
)
99 return 1 << (pin
% 32);
103 static char peripheral_function(void __iomem
*pio
, unsigned mask
)
110 select
= !!(__raw_readl(pio
+ PIO_ABCDSR1
) & mask
);
111 select
|= (!!(__raw_readl(pio
+ PIO_ABCDSR2
) & mask
) << 1);
114 ret
= __raw_readl(pio
+ PIO_ABSR
) & mask
?
122 /*--------------------------------------------------------------------------*/
124 /* Not all hardware capabilities are exposed through these calls; they
125 * only encapsulate the most common features and modes. (So if you
126 * want to change signals in groups, do it directly.)
128 * Bootloaders will usually handle some of the pin multiplexing setup.
129 * The intent is certainly that by the time Linux is fully booted, all
130 * pins should have been fully initialized. These setup calls should
131 * only be used by board setup routines, or possibly in driver probe().
133 * For bootloaders doing all that setup, these calls could be inlined
134 * as NOPs so Linux won't duplicate any setup code
139 * mux the pin to the "GPIO" peripheral role.
141 int __init_or_module
at91_set_GPIO_periph(unsigned pin
, int use_pullup
)
143 void __iomem
*pio
= pin_to_controller(pin
);
144 unsigned mask
= pin_to_mask(pin
);
148 __raw_writel(mask
, pio
+ PIO_IDR
);
149 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
150 __raw_writel(mask
, pio
+ PIO_PER
);
153 EXPORT_SYMBOL(at91_set_GPIO_periph
);
157 * mux the pin to the "A" internal peripheral role.
159 int __init_or_module
at91_set_A_periph(unsigned pin
, int use_pullup
)
161 void __iomem
*pio
= pin_to_controller(pin
);
162 unsigned mask
= pin_to_mask(pin
);
167 __raw_writel(mask
, pio
+ PIO_IDR
);
168 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
170 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR1
) & ~mask
,
172 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR2
) & ~mask
,
175 __raw_writel(mask
, pio
+ PIO_ASR
);
177 __raw_writel(mask
, pio
+ PIO_PDR
);
180 EXPORT_SYMBOL(at91_set_A_periph
);
184 * mux the pin to the "B" internal peripheral role.
186 int __init_or_module
at91_set_B_periph(unsigned pin
, int use_pullup
)
188 void __iomem
*pio
= pin_to_controller(pin
);
189 unsigned mask
= pin_to_mask(pin
);
194 __raw_writel(mask
, pio
+ PIO_IDR
);
195 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
197 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR1
) | mask
,
199 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR2
) & ~mask
,
202 __raw_writel(mask
, pio
+ PIO_BSR
);
204 __raw_writel(mask
, pio
+ PIO_PDR
);
207 EXPORT_SYMBOL(at91_set_B_periph
);
211 * mux the pin to the "C" internal peripheral role.
213 int __init_or_module
at91_set_C_periph(unsigned pin
, int use_pullup
)
215 void __iomem
*pio
= pin_to_controller(pin
);
216 unsigned mask
= pin_to_mask(pin
);
218 if (!pio
|| !has_pio3())
221 __raw_writel(mask
, pio
+ PIO_IDR
);
222 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
223 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR1
) & ~mask
, pio
+ PIO_ABCDSR1
);
224 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR2
) | mask
, pio
+ PIO_ABCDSR2
);
225 __raw_writel(mask
, pio
+ PIO_PDR
);
228 EXPORT_SYMBOL(at91_set_C_periph
);
232 * mux the pin to the "D" internal peripheral role.
234 int __init_or_module
at91_set_D_periph(unsigned pin
, int use_pullup
)
236 void __iomem
*pio
= pin_to_controller(pin
);
237 unsigned mask
= pin_to_mask(pin
);
239 if (!pio
|| !has_pio3())
242 __raw_writel(mask
, pio
+ PIO_IDR
);
243 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
244 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR1
) | mask
, pio
+ PIO_ABCDSR1
);
245 __raw_writel(__raw_readl(pio
+ PIO_ABCDSR2
) | mask
, pio
+ PIO_ABCDSR2
);
246 __raw_writel(mask
, pio
+ PIO_PDR
);
249 EXPORT_SYMBOL(at91_set_D_periph
);
253 * mux the pin to the gpio controller (instead of "A", "B", "C"
254 * or "D" peripheral), and configure it for an input.
256 int __init_or_module
at91_set_gpio_input(unsigned pin
, int use_pullup
)
258 void __iomem
*pio
= pin_to_controller(pin
);
259 unsigned mask
= pin_to_mask(pin
);
264 __raw_writel(mask
, pio
+ PIO_IDR
);
265 __raw_writel(mask
, pio
+ (use_pullup
? PIO_PUER
: PIO_PUDR
));
266 __raw_writel(mask
, pio
+ PIO_ODR
);
267 __raw_writel(mask
, pio
+ PIO_PER
);
270 EXPORT_SYMBOL(at91_set_gpio_input
);
274 * mux the pin to the gpio controller (instead of "A", "B", "C"
275 * or "D" peripheral), and configure it for an output.
277 int __init_or_module
at91_set_gpio_output(unsigned pin
, int value
)
279 void __iomem
*pio
= pin_to_controller(pin
);
280 unsigned mask
= pin_to_mask(pin
);
285 __raw_writel(mask
, pio
+ PIO_IDR
);
286 __raw_writel(mask
, pio
+ PIO_PUDR
);
287 __raw_writel(mask
, pio
+ (value
? PIO_SODR
: PIO_CODR
));
288 __raw_writel(mask
, pio
+ PIO_OER
);
289 __raw_writel(mask
, pio
+ PIO_PER
);
292 EXPORT_SYMBOL(at91_set_gpio_output
);
296 * enable/disable the glitch filter; mostly used with IRQ handling.
298 int __init_or_module
at91_set_deglitch(unsigned pin
, int is_on
)
300 void __iomem
*pio
= pin_to_controller(pin
);
301 unsigned mask
= pin_to_mask(pin
);
306 if (has_pio3() && is_on
)
307 __raw_writel(mask
, pio
+ PIO_IFSCDR
);
308 __raw_writel(mask
, pio
+ (is_on
? PIO_IFER
: PIO_IFDR
));
311 EXPORT_SYMBOL(at91_set_deglitch
);
314 * enable/disable the debounce filter;
316 int __init_or_module
at91_set_debounce(unsigned pin
, int is_on
, int div
)
318 void __iomem
*pio
= pin_to_controller(pin
);
319 unsigned mask
= pin_to_mask(pin
);
321 if (!pio
|| !has_pio3())
325 __raw_writel(mask
, pio
+ PIO_IFSCER
);
326 __raw_writel(div
& PIO_SCDR_DIV
, pio
+ PIO_SCDR
);
327 __raw_writel(mask
, pio
+ PIO_IFER
);
329 __raw_writel(mask
, pio
+ PIO_IFDR
);
333 EXPORT_SYMBOL(at91_set_debounce
);
336 * enable/disable the multi-driver; This is only valid for output and
337 * allows the output pin to run as an open collector output.
339 int __init_or_module
at91_set_multi_drive(unsigned pin
, int is_on
)
341 void __iomem
*pio
= pin_to_controller(pin
);
342 unsigned mask
= pin_to_mask(pin
);
347 __raw_writel(mask
, pio
+ (is_on
? PIO_MDER
: PIO_MDDR
));
350 EXPORT_SYMBOL(at91_set_multi_drive
);
353 * enable/disable the pull-down.
354 * If pull-up already enabled while calling the function, we disable it.
356 int __init_or_module
at91_set_pulldown(unsigned pin
, int is_on
)
358 void __iomem
*pio
= pin_to_controller(pin
);
359 unsigned mask
= pin_to_mask(pin
);
361 if (!pio
|| !has_pio3())
364 /* Disable pull-up anyway */
365 __raw_writel(mask
, pio
+ PIO_PUDR
);
366 __raw_writel(mask
, pio
+ (is_on
? PIO_PPDER
: PIO_PPDDR
));
369 EXPORT_SYMBOL(at91_set_pulldown
);
372 * disable Schmitt trigger
374 int __init_or_module
at91_disable_schmitt_trig(unsigned pin
)
376 void __iomem
*pio
= pin_to_controller(pin
);
377 unsigned mask
= pin_to_mask(pin
);
379 if (!pio
|| !has_pio3())
382 __raw_writel(__raw_readl(pio
+ PIO_SCHMITT
) | mask
, pio
+ PIO_SCHMITT
);
385 EXPORT_SYMBOL(at91_disable_schmitt_trig
);
388 * assuming the pin is muxed as a gpio output, set its value.
390 int at91_set_gpio_value(unsigned pin
, int value
)
392 void __iomem
*pio
= pin_to_controller(pin
);
393 unsigned mask
= pin_to_mask(pin
);
397 __raw_writel(mask
, pio
+ (value
? PIO_SODR
: PIO_CODR
));
400 EXPORT_SYMBOL(at91_set_gpio_value
);
404 * read the pin's value (works even if it's not muxed as a gpio).
406 int at91_get_gpio_value(unsigned pin
)
408 void __iomem
*pio
= pin_to_controller(pin
);
409 unsigned mask
= pin_to_mask(pin
);
414 pdsr
= __raw_readl(pio
+ PIO_PDSR
);
415 return (pdsr
& mask
) != 0;
417 EXPORT_SYMBOL(at91_get_gpio_value
);
419 /*--------------------------------------------------------------------------*/
423 static u32 wakeups
[MAX_GPIO_BANKS
];
424 static u32 backups
[MAX_GPIO_BANKS
];
426 static int gpio_irq_set_wake(struct irq_data
*d
, unsigned state
)
428 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
429 unsigned mask
= 1 << d
->hwirq
;
430 unsigned bank
= at91_gpio
->pioc_idx
;
432 if (unlikely(bank
>= MAX_GPIO_BANKS
))
436 wakeups
[bank
] |= mask
;
438 wakeups
[bank
] &= ~mask
;
440 irq_set_irq_wake(at91_gpio
->pioc_virq
, state
);
445 void at91_gpio_suspend(void)
449 for (i
= 0; i
< gpio_banks
; i
++) {
450 void __iomem
*pio
= gpio_chip
[i
].regbase
;
452 backups
[i
] = __raw_readl(pio
+ PIO_IMR
);
453 __raw_writel(backups
[i
], pio
+ PIO_IDR
);
454 __raw_writel(wakeups
[i
], pio
+ PIO_IER
);
457 clk_unprepare(gpio_chip
[i
].clock
);
458 clk_disable(gpio_chip
[i
].clock
);
460 #ifdef CONFIG_PM_DEBUG
461 printk(KERN_DEBUG
"GPIO-%c may wake for %08x\n", 'A'+i
, wakeups
[i
]);
467 void at91_gpio_resume(void)
471 for (i
= 0; i
< gpio_banks
; i
++) {
472 void __iomem
*pio
= gpio_chip
[i
].regbase
;
475 if (clk_prepare(gpio_chip
[i
].clock
) == 0)
476 clk_enable(gpio_chip
[i
].clock
);
479 __raw_writel(wakeups
[i
], pio
+ PIO_IDR
);
480 __raw_writel(backups
[i
], pio
+ PIO_IER
);
485 #define gpio_irq_set_wake NULL
489 /* Several AIC controller irqs are dispatched through this GPIO handler.
490 * To use any AT91_PIN_* as an externally triggered IRQ, first call
491 * at91_set_gpio_input() then maybe enable its glitch filter.
492 * Then just request_irq() with the pin ID; it works like any ARM IRQ
494 * First implementation always triggers on rising and falling edges
495 * whereas the newer PIO3 can be additionally configured to trigger on
496 * level, edge with any polarity.
498 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
499 * configuring them with at91_set_a_periph() or at91_set_b_periph().
500 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
503 static void gpio_irq_mask(struct irq_data
*d
)
505 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
506 void __iomem
*pio
= at91_gpio
->regbase
;
507 unsigned mask
= 1 << d
->hwirq
;
510 __raw_writel(mask
, pio
+ PIO_IDR
);
513 static void gpio_irq_unmask(struct irq_data
*d
)
515 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
516 void __iomem
*pio
= at91_gpio
->regbase
;
517 unsigned mask
= 1 << d
->hwirq
;
520 __raw_writel(mask
, pio
+ PIO_IER
);
523 static int gpio_irq_type(struct irq_data
*d
, unsigned type
)
527 case IRQ_TYPE_EDGE_BOTH
:
534 /* Alternate irq type for PIO3 support */
535 static int alt_gpio_irq_type(struct irq_data
*d
, unsigned type
)
537 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(d
);
538 void __iomem
*pio
= at91_gpio
->regbase
;
539 unsigned mask
= 1 << d
->hwirq
;
542 case IRQ_TYPE_EDGE_RISING
:
543 __raw_writel(mask
, pio
+ PIO_ESR
);
544 __raw_writel(mask
, pio
+ PIO_REHLSR
);
546 case IRQ_TYPE_EDGE_FALLING
:
547 __raw_writel(mask
, pio
+ PIO_ESR
);
548 __raw_writel(mask
, pio
+ PIO_FELLSR
);
550 case IRQ_TYPE_LEVEL_LOW
:
551 __raw_writel(mask
, pio
+ PIO_LSR
);
552 __raw_writel(mask
, pio
+ PIO_FELLSR
);
554 case IRQ_TYPE_LEVEL_HIGH
:
555 __raw_writel(mask
, pio
+ PIO_LSR
);
556 __raw_writel(mask
, pio
+ PIO_REHLSR
);
558 case IRQ_TYPE_EDGE_BOTH
:
560 * disable additional interrupt modes:
561 * fall back to default behavior
563 __raw_writel(mask
, pio
+ PIO_AIMDR
);
567 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d
->irq
));
571 /* enable additional interrupt modes */
572 __raw_writel(mask
, pio
+ PIO_AIMER
);
577 static struct irq_chip gpio_irqchip
= {
579 .irq_disable
= gpio_irq_mask
,
580 .irq_mask
= gpio_irq_mask
,
581 .irq_unmask
= gpio_irq_unmask
,
582 /* .irq_set_type is set dynamically */
583 .irq_set_wake
= gpio_irq_set_wake
,
586 static void gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
588 struct irq_data
*idata
= irq_desc_get_irq_data(desc
);
589 struct irq_chip
*chip
= irq_data_get_irq_chip(idata
);
590 struct at91_gpio_chip
*at91_gpio
= irq_data_get_irq_chip_data(idata
);
591 void __iomem
*pio
= at91_gpio
->regbase
;
595 /* temporarily mask (level sensitive) parent IRQ */
596 chip
->irq_ack(idata
);
598 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
599 * When there none are pending, we're finished unless we need
600 * to process multiple banks (like ID_PIOCDE on sam9263).
602 isr
= __raw_readl(pio
+ PIO_ISR
) & __raw_readl(pio
+ PIO_IMR
);
604 if (!at91_gpio
->next
)
606 at91_gpio
= at91_gpio
->next
;
607 pio
= at91_gpio
->regbase
;
611 n
= find_first_bit(&isr
, BITS_PER_LONG
);
612 while (n
< BITS_PER_LONG
) {
613 generic_handle_irq(irq_find_mapping(at91_gpio
->domain
, n
));
614 n
= find_next_bit(&isr
, BITS_PER_LONG
, n
+ 1);
617 chip
->irq_unmask(idata
);
618 /* now it may re-trigger */
621 /*--------------------------------------------------------------------------*/
623 #ifdef CONFIG_DEBUG_FS
625 static void gpio_printf(struct seq_file
*s
, void __iomem
*pio
, unsigned mask
)
627 char *trigger
= NULL
;
628 char *polarity
= NULL
;
630 if (__raw_readl(pio
+ PIO_IMR
) & mask
) {
631 if (!has_pio3() || !(__raw_readl(pio
+ PIO_AIMMR
) & mask
)) {
635 if (__raw_readl(pio
+ PIO_ELSR
) & mask
) {
637 polarity
= __raw_readl(pio
+ PIO_FRLHSR
) & mask
?
641 polarity
= __raw_readl(pio
+ PIO_FRLHSR
) & mask
?
642 "rising" : "falling";
645 seq_printf(s
, "IRQ:%s-%s\t", trigger
, polarity
);
647 seq_printf(s
, "GPIO:%s\t\t",
648 __raw_readl(pio
+ PIO_PDSR
) & mask
? "1" : "0");
652 static int at91_gpio_show(struct seq_file
*s
, void *unused
)
657 seq_printf(s
, "Pin\t");
658 for (bank
= 0; bank
< gpio_banks
; bank
++) {
659 seq_printf(s
, "PIO%c\t\t", 'A' + bank
);
661 seq_printf(s
, "\n\n");
663 /* print pin status */
664 for (j
= 0; j
< 32; j
++) {
665 seq_printf(s
, "%i:\t", j
);
667 for (bank
= 0; bank
< gpio_banks
; bank
++) {
668 unsigned pin
= (32 * bank
) + j
;
669 void __iomem
*pio
= pin_to_controller(pin
);
670 unsigned mask
= pin_to_mask(pin
);
672 if (__raw_readl(pio
+ PIO_PSR
) & mask
)
673 gpio_printf(s
, pio
, mask
);
675 seq_printf(s
, "%c\t\t",
676 peripheral_function(pio
, mask
));
685 static int at91_gpio_open(struct inode
*inode
, struct file
*file
)
687 return single_open(file
, at91_gpio_show
, NULL
);
690 static const struct file_operations at91_gpio_operations
= {
691 .open
= at91_gpio_open
,
694 .release
= single_release
,
697 static int __init
at91_gpio_debugfs_init(void)
699 /* /sys/kernel/debug/at91_gpio */
700 (void) debugfs_create_file("at91_gpio", S_IFREG
| S_IRUGO
, NULL
, NULL
, &at91_gpio_operations
);
703 postcore_initcall(at91_gpio_debugfs_init
);
707 /*--------------------------------------------------------------------------*/
710 * This lock class tells lockdep that GPIO irqs are in a different
711 * category than their parents, so it won't report false recursion.
713 static struct lock_class_key gpio_lock_class
;
715 #if defined(CONFIG_OF)
716 static int at91_gpio_irq_map(struct irq_domain
*h
, unsigned int virq
,
719 struct at91_gpio_chip
*at91_gpio
= h
->host_data
;
721 irq_set_lockdep_class(virq
, &gpio_lock_class
);
724 * Can use the "simple" and not "edge" handler since it's
725 * shorter, and the AIC handles interrupts sanely.
727 irq_set_chip_and_handler(virq
, &gpio_irqchip
,
729 set_irq_flags(virq
, IRQF_VALID
);
730 irq_set_chip_data(virq
, at91_gpio
);
735 static struct irq_domain_ops at91_gpio_ops
= {
736 .map
= at91_gpio_irq_map
,
737 .xlate
= irq_domain_xlate_twocell
,
740 int __init
at91_gpio_of_irq_setup(struct device_node
*node
,
741 struct device_node
*parent
)
743 struct at91_gpio_chip
*prev
= NULL
;
744 int alias_idx
= of_alias_get_id(node
, "gpio");
745 struct at91_gpio_chip
*at91_gpio
= &gpio_chip
[alias_idx
];
747 /* Setup proper .irq_set_type function */
749 gpio_irqchip
.irq_set_type
= alt_gpio_irq_type
;
751 gpio_irqchip
.irq_set_type
= gpio_irq_type
;
753 /* Disable irqs of this PIO controller */
754 __raw_writel(~0, at91_gpio
->regbase
+ PIO_IDR
);
756 /* Setup irq domain */
757 at91_gpio
->domain
= irq_domain_add_linear(node
, at91_gpio
->chip
.ngpio
,
758 &at91_gpio_ops
, at91_gpio
);
759 if (!at91_gpio
->domain
)
760 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
761 at91_gpio
->pioc_idx
);
763 /* Setup chained handler */
764 if (at91_gpio
->pioc_idx
)
765 prev
= &gpio_chip
[at91_gpio
->pioc_idx
- 1];
767 /* The toplevel handler handles one bank of GPIOs, except
768 * on some SoC it can handles up to three...
769 * We only set up the handler for the first of the list.
771 if (prev
&& prev
->next
== at91_gpio
)
774 at91_gpio
->pioc_virq
= irq_create_mapping(irq_find_host(parent
),
775 at91_gpio
->pioc_hwirq
);
776 irq_set_chip_data(at91_gpio
->pioc_virq
, at91_gpio
);
777 irq_set_chained_handler(at91_gpio
->pioc_virq
, gpio_irq_handler
);
782 int __init
at91_gpio_of_irq_setup(struct device_node
*node
,
783 struct device_node
*parent
)
790 * irqdomain initialization: pile up irqdomains on top of AIC range
792 static void __init
at91_gpio_irqdomain(struct at91_gpio_chip
*at91_gpio
)
796 irq_base
= irq_alloc_descs(-1, 0, at91_gpio
->chip
.ngpio
, 0);
798 panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
799 at91_gpio
->pioc_idx
, irq_base
);
800 at91_gpio
->domain
= irq_domain_add_legacy(NULL
, at91_gpio
->chip
.ngpio
,
802 &irq_domain_simple_ops
, NULL
);
803 if (!at91_gpio
->domain
)
804 panic("at91_gpio.%d: couldn't allocate irq domain.\n",
805 at91_gpio
->pioc_idx
);
809 * Called from the processor-specific init to enable GPIO interrupt support.
811 void __init
at91_gpio_irq_setup(void)
815 struct at91_gpio_chip
*this, *prev
;
817 /* Setup proper .irq_set_type function */
819 gpio_irqchip
.irq_set_type
= alt_gpio_irq_type
;
821 gpio_irqchip
.irq_set_type
= gpio_irq_type
;
823 for (pioc
= 0, this = gpio_chip
, prev
= NULL
;
825 prev
= this, this++) {
828 __raw_writel(~0, this->regbase
+ PIO_IDR
);
830 /* setup irq domain for this GPIO controller */
831 at91_gpio_irqdomain(this);
833 for (offset
= 0; offset
< this->chip
.ngpio
; offset
++) {
834 unsigned int virq
= irq_find_mapping(this->domain
, offset
);
835 irq_set_lockdep_class(virq
, &gpio_lock_class
);
838 * Can use the "simple" and not "edge" handler since it's
839 * shorter, and the AIC handles interrupts sanely.
841 irq_set_chip_and_handler(virq
, &gpio_irqchip
,
843 set_irq_flags(virq
, IRQF_VALID
);
844 irq_set_chip_data(virq
, this);
849 /* The toplevel handler handles one bank of GPIOs, except
850 * on some SoC it can handles up to three...
851 * We only set up the handler for the first of the list.
853 if (prev
&& prev
->next
== this)
856 this->pioc_virq
= irq_create_mapping(NULL
, this->pioc_hwirq
);
857 irq_set_chip_data(this->pioc_virq
, this);
858 irq_set_chained_handler(this->pioc_virq
, gpio_irq_handler
);
860 pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr
, gpio_banks
);
863 /* gpiolib support */
864 static int at91_gpiolib_direction_input(struct gpio_chip
*chip
,
867 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
868 void __iomem
*pio
= at91_gpio
->regbase
;
869 unsigned mask
= 1 << offset
;
871 __raw_writel(mask
, pio
+ PIO_ODR
);
875 static int at91_gpiolib_direction_output(struct gpio_chip
*chip
,
876 unsigned offset
, int val
)
878 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
879 void __iomem
*pio
= at91_gpio
->regbase
;
880 unsigned mask
= 1 << offset
;
882 __raw_writel(mask
, pio
+ (val
? PIO_SODR
: PIO_CODR
));
883 __raw_writel(mask
, pio
+ PIO_OER
);
887 static int at91_gpiolib_get(struct gpio_chip
*chip
, unsigned offset
)
889 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
890 void __iomem
*pio
= at91_gpio
->regbase
;
891 unsigned mask
= 1 << offset
;
894 pdsr
= __raw_readl(pio
+ PIO_PDSR
);
895 return (pdsr
& mask
) != 0;
898 static void at91_gpiolib_set(struct gpio_chip
*chip
, unsigned offset
, int val
)
900 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
901 void __iomem
*pio
= at91_gpio
->regbase
;
902 unsigned mask
= 1 << offset
;
904 __raw_writel(mask
, pio
+ (val
? PIO_SODR
: PIO_CODR
));
907 static void at91_gpiolib_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
911 for (i
= 0; i
< chip
->ngpio
; i
++) {
912 unsigned pin
= chip
->base
+ i
;
913 void __iomem
*pio
= pin_to_controller(pin
);
914 unsigned mask
= pin_to_mask(pin
);
915 const char *gpio_label
;
917 gpio_label
= gpiochip_is_requested(chip
, i
);
919 seq_printf(s
, "[%s] GPIO%s%d: ",
920 gpio_label
, chip
->label
, i
);
921 if (__raw_readl(pio
+ PIO_PSR
) & mask
)
922 seq_printf(s
, "[gpio] %s\n",
923 at91_get_gpio_value(pin
) ?
926 seq_printf(s
, "[periph %c]\n",
927 peripheral_function(pio
, mask
));
932 static int at91_gpiolib_to_irq(struct gpio_chip
*chip
, unsigned offset
)
934 struct at91_gpio_chip
*at91_gpio
= to_at91_gpio_chip(chip
);
937 if (offset
< chip
->ngpio
)
938 virq
= irq_create_mapping(at91_gpio
->domain
, offset
);
942 dev_dbg(chip
->dev
, "%s: request IRQ for GPIO %d, return %d\n",
943 chip
->label
, offset
+ chip
->base
, virq
);
947 static int __init
at91_gpio_setup_clk(int idx
)
949 struct at91_gpio_chip
*at91_gpio
= &gpio_chip
[idx
];
951 /* retreive PIO controller's clock */
952 at91_gpio
->clock
= clk_get_sys(NULL
, at91_gpio
->chip
.label
);
953 if (IS_ERR(at91_gpio
->clock
)) {
954 pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx
);
958 if (clk_prepare(at91_gpio
->clock
))
961 /* enable PIO controller's clock */
962 if (clk_enable(at91_gpio
->clock
)) {
963 pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx
);
970 clk_unprepare(at91_gpio
->clock
);
972 clk_put(at91_gpio
->clock
);
977 #ifdef CONFIG_OF_GPIO
978 static void __init
of_at91_gpio_init_one(struct device_node
*np
)
981 struct at91_gpio_chip
*at91_gpio
;
986 alias_idx
= of_alias_get_id(np
, "gpio");
987 if (alias_idx
>= MAX_GPIO_BANKS
) {
988 pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
989 alias_idx
, MAX_GPIO_BANKS
);
993 at91_gpio
= &gpio_chip
[alias_idx
];
994 at91_gpio
->chip
.base
= alias_idx
* at91_gpio
->chip
.ngpio
;
996 at91_gpio
->regbase
= of_iomap(np
, 0);
997 if (!at91_gpio
->regbase
) {
998 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
1003 /* Get the interrupts property */
1004 if (of_property_read_u32(np
, "interrupts", &at91_gpio
->pioc_hwirq
)) {
1005 pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
1010 /* Get capabilities from compatibility property */
1011 if (of_device_is_compatible(np
, "atmel,at91sam9x5-gpio"))
1012 at91_gpio_caps
|= AT91_GPIO_CAP_PIO3
;
1015 if (at91_gpio_setup_clk(alias_idx
))
1018 at91_gpio
->chip
.of_node
= np
;
1019 gpio_banks
= max(gpio_banks
, alias_idx
+ 1);
1020 at91_gpio
->pioc_idx
= alias_idx
;
1024 iounmap(at91_gpio
->regbase
);
1027 static int __init
of_at91_gpio_init(void)
1029 struct device_node
*np
= NULL
;
1032 * This isn't ideal, but it gets things hooked up until this
1033 * driver is converted into a platform_device
1035 for_each_compatible_node(np
, NULL
, "atmel,at91rm9200-gpio")
1036 of_at91_gpio_init_one(np
);
1038 return gpio_banks
> 0 ? 0 : -EINVAL
;
1041 static int __init
of_at91_gpio_init(void)
1047 static void __init
at91_gpio_init_one(int idx
, u32 regbase
, int pioc_hwirq
)
1049 struct at91_gpio_chip
*at91_gpio
= &gpio_chip
[idx
];
1051 at91_gpio
->chip
.base
= idx
* at91_gpio
->chip
.ngpio
;
1052 at91_gpio
->pioc_hwirq
= pioc_hwirq
;
1053 at91_gpio
->pioc_idx
= idx
;
1055 at91_gpio
->regbase
= ioremap(regbase
, 512);
1056 if (!at91_gpio
->regbase
) {
1057 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx
);
1061 if (at91_gpio_setup_clk(idx
))
1064 gpio_banks
= max(gpio_banks
, idx
+ 1);
1068 iounmap(at91_gpio
->regbase
);
1072 * Called from the processor-specific init to enable GPIO pin support.
1074 void __init
at91_gpio_init(struct at91_gpio_bank
*data
, int nr_banks
)
1077 struct at91_gpio_chip
*at91_gpio
, *last
= NULL
;
1079 BUG_ON(nr_banks
> MAX_GPIO_BANKS
);
1081 if (of_at91_gpio_init() < 0) {
1082 /* No GPIO controller found in device tree */
1083 for (i
= 0; i
< nr_banks
; i
++)
1084 at91_gpio_init_one(i
, data
[i
].regbase
, data
[i
].id
);
1087 for (i
= 0; i
< gpio_banks
; i
++) {
1088 at91_gpio
= &gpio_chip
[i
];
1091 * GPIO controller are grouped on some SoC:
1092 * PIOC, PIOD and PIOE can share the same IRQ line
1094 if (last
&& last
->pioc_hwirq
== at91_gpio
->pioc_hwirq
)
1095 last
->next
= at91_gpio
;
1098 gpiochip_add(&at91_gpio
->chip
);