2 * arch/arm/mach-at91/pm.c
3 * AT91 Power Management
5 * Copyright (C) 2005 David Brownell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/gpio.h>
14 #include <linux/suspend.h>
15 #include <linux/sched.h>
16 #include <linux/proc_fs.h>
17 #include <linux/genalloc.h>
18 #include <linux/interrupt.h>
19 #include <linux/sysfs.h>
20 #include <linux/module.h>
22 #include <linux/of_platform.h>
23 #include <linux/of_address.h>
24 #include <linux/platform_device.h>
26 #include <linux/clk/at91_pmc.h>
29 #include <linux/atomic.h>
30 #include <asm/mach/time.h>
31 #include <asm/mach/irq.h>
32 #include <asm/fncpy.h>
33 #include <asm/cacheflush.h>
34 #include <asm/system_misc.h>
39 static void __iomem
*pmc
;
42 * FIXME: this is needed to communicate between the pinctrl driver and
43 * the PM implementation in the machine. Possibly part of the PM
44 * implementation should be moved down into the pinctrl driver and get
45 * called as part of the generic suspend/resume path.
47 #ifdef CONFIG_PINCTRL_AT91
48 extern void at91_pinctrl_gpio_suspend(void);
49 extern void at91_pinctrl_gpio_resume(void);
53 unsigned long uhp_udp_mask
;
57 void __iomem
*at91_ramc_base
[2];
59 static int at91_pm_valid_state(suspend_state_t state
)
63 case PM_SUSPEND_STANDBY
:
73 static suspend_state_t target_state
;
76 * Called after processes are frozen, but before we shutdown devices.
78 static int at91_pm_begin(suspend_state_t state
)
85 * Verify that all the clocks are correct before entering
88 static int at91_pm_verify_clocks(void)
93 scsr
= readl(pmc
+ AT91_PMC_SCSR
);
95 /* USB must not be using PLLB */
96 if ((scsr
& at91_pm_data
.uhp_udp_mask
) != 0) {
97 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
101 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
102 for (i
= 0; i
< 4; i
++) {
105 if ((scsr
& (AT91_PMC_PCK0
<< i
)) == 0)
107 css
= readl(pmc
+ AT91_PMC_PCKR(i
)) & AT91_PMC_CSS
;
108 if (css
!= AT91_PMC_CSS_SLOW
) {
109 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i
, css
);
118 * Call this from platform driver suspend() to see how deeply to suspend.
119 * For example, some controllers (like OHCI) need one of the PLL clocks
120 * in order to act as a wakeup source, and those are not available when
121 * going into slow clock mode.
123 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
124 * the very same problem (but not using at91 main_clk), and it'd be better
125 * to add one generic API rather than lots of platform-specific ones.
127 int at91_suspend_entering_slow_clock(void)
129 return (target_state
== PM_SUSPEND_MEM
);
131 EXPORT_SYMBOL(at91_suspend_entering_slow_clock
);
133 static void (*at91_suspend_sram_fn
)(void __iomem
*pmc
, void __iomem
*ramc0
,
134 void __iomem
*ramc1
, int memctrl
);
136 extern void at91_pm_suspend_in_sram(void __iomem
*pmc
, void __iomem
*ramc0
,
137 void __iomem
*ramc1
, int memctrl
);
138 extern u32 at91_pm_suspend_in_sram_sz
;
140 static void at91_pm_suspend(suspend_state_t state
)
142 unsigned int pm_data
= at91_pm_data
.memctrl
;
144 pm_data
|= (state
== PM_SUSPEND_MEM
) ?
145 AT91_PM_MODE(AT91_PM_SLOW_CLOCK
) : 0;
150 at91_suspend_sram_fn(pmc
, at91_ramc_base
[0],
151 at91_ramc_base
[1], pm_data
);
156 static int at91_pm_enter(suspend_state_t state
)
158 #ifdef CONFIG_PINCTRL_AT91
159 at91_pinctrl_gpio_suspend();
163 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
164 * drivers must suspend more deeply, the master clock switches
165 * to the clk32k and turns off the main oscillator
169 * Ensure that clocks are in a valid state.
171 if (!at91_pm_verify_clocks())
174 at91_pm_suspend(state
);
179 * STANDBY mode has *all* drivers suspended; ignores irqs not
180 * marked as 'wakeup' event sources; and reduces DRAM power.
181 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
182 * nothing fancy done with main or cpu clocks.
184 case PM_SUSPEND_STANDBY
:
185 at91_pm_suspend(state
);
193 pr_debug("AT91: PM - bogus suspend state %d\n", state
);
198 target_state
= PM_SUSPEND_ON
;
200 #ifdef CONFIG_PINCTRL_AT91
201 at91_pinctrl_gpio_resume();
207 * Called right prior to thawing processes.
209 static void at91_pm_end(void)
211 target_state
= PM_SUSPEND_ON
;
215 static const struct platform_suspend_ops at91_pm_ops
= {
216 .valid
= at91_pm_valid_state
,
217 .begin
= at91_pm_begin
,
218 .enter
= at91_pm_enter
,
222 static struct platform_device at91_cpuidle_device
= {
223 .name
= "cpuidle-at91",
226 static void at91_pm_set_standby(void (*at91_standby
)(void))
229 at91_cpuidle_device
.dev
.platform_data
= at91_standby
;
233 * The AT91RM9200 goes into self-refresh mode with this command, and will
234 * terminate self-refresh automatically on the next SDRAM access.
236 * Self-refresh mode is exited as soon as a memory access is made, but we don't
237 * know for sure when that happens. However, we need to restore the low-power
238 * mode if it was enabled before going idle. Restoring low-power mode while
239 * still in self-refresh is "not recommended", but seems to work.
241 static void at91rm9200_standby(void)
243 u32 lpr
= at91_ramc_read(0, AT91_MC_SDRAMC_LPR
);
248 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
249 " str %0, [%1, %2]\n\t"
250 " str %3, [%1, %4]\n\t"
251 " mcr p15, 0, %0, c7, c0, 4\n\t"
254 : "r" (0), "r" (at91_ramc_base
[0]), "r" (AT91_MC_SDRAMC_LPR
),
255 "r" (1), "r" (AT91_MC_SDRAMC_SRR
),
259 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
262 static void at91_ddr_standby(void)
264 /* Those two values allow us to delay self-refresh activation
267 u32 saved_lpr0
, saved_lpr1
= 0;
269 if (at91_ramc_base
[1]) {
270 saved_lpr1
= at91_ramc_read(1, AT91_DDRSDRC_LPR
);
271 lpr1
= saved_lpr1
& ~AT91_DDRSDRC_LPCB
;
272 lpr1
|= AT91_DDRSDRC_LPCB_SELF_REFRESH
;
275 saved_lpr0
= at91_ramc_read(0, AT91_DDRSDRC_LPR
);
276 lpr0
= saved_lpr0
& ~AT91_DDRSDRC_LPCB
;
277 lpr0
|= AT91_DDRSDRC_LPCB_SELF_REFRESH
;
279 /* self-refresh mode now */
280 at91_ramc_write(0, AT91_DDRSDRC_LPR
, lpr0
);
281 if (at91_ramc_base
[1])
282 at91_ramc_write(1, AT91_DDRSDRC_LPR
, lpr1
);
286 at91_ramc_write(0, AT91_DDRSDRC_LPR
, saved_lpr0
);
287 if (at91_ramc_base
[1])
288 at91_ramc_write(1, AT91_DDRSDRC_LPR
, saved_lpr1
);
291 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
294 static void at91sam9_sdram_standby(void)
297 u32 saved_lpr0
, saved_lpr1
= 0;
299 if (at91_ramc_base
[1]) {
300 saved_lpr1
= at91_ramc_read(1, AT91_SDRAMC_LPR
);
301 lpr1
= saved_lpr1
& ~AT91_SDRAMC_LPCB
;
302 lpr1
|= AT91_SDRAMC_LPCB_SELF_REFRESH
;
305 saved_lpr0
= at91_ramc_read(0, AT91_SDRAMC_LPR
);
306 lpr0
= saved_lpr0
& ~AT91_SDRAMC_LPCB
;
307 lpr0
|= AT91_SDRAMC_LPCB_SELF_REFRESH
;
309 /* self-refresh mode now */
310 at91_ramc_write(0, AT91_SDRAMC_LPR
, lpr0
);
311 if (at91_ramc_base
[1])
312 at91_ramc_write(1, AT91_SDRAMC_LPR
, lpr1
);
316 at91_ramc_write(0, AT91_SDRAMC_LPR
, saved_lpr0
);
317 if (at91_ramc_base
[1])
318 at91_ramc_write(1, AT91_SDRAMC_LPR
, saved_lpr1
);
321 static const struct of_device_id
const ramc_ids
[] __initconst
= {
322 { .compatible
= "atmel,at91rm9200-sdramc", .data
= at91rm9200_standby
},
323 { .compatible
= "atmel,at91sam9260-sdramc", .data
= at91sam9_sdram_standby
},
324 { .compatible
= "atmel,at91sam9g45-ddramc", .data
= at91_ddr_standby
},
325 { .compatible
= "atmel,sama5d3-ddramc", .data
= at91_ddr_standby
},
329 static __init
void at91_dt_ramc(void)
331 struct device_node
*np
;
332 const struct of_device_id
*of_id
;
334 const void *standby
= NULL
;
336 for_each_matching_node_and_match(np
, ramc_ids
, &of_id
) {
337 at91_ramc_base
[idx
] = of_iomap(np
, 0);
338 if (!at91_ramc_base
[idx
])
339 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx
);
342 standby
= of_id
->data
;
348 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
351 pr_warn("ramc no standby function available\n");
355 at91_pm_set_standby(standby
);
358 void at91rm9200_idle(void)
361 * Disable the processor clock. The processor will be automatically
362 * re-enabled by an interrupt or by a reset.
364 writel(AT91_PMC_PCK
, pmc
+ AT91_PMC_SCDR
);
367 void at91sam9_idle(void)
369 writel(AT91_PMC_PCK
, pmc
+ AT91_PMC_SCDR
);
373 static void __init
at91_pm_sram_init(void)
375 struct gen_pool
*sram_pool
;
376 phys_addr_t sram_pbase
;
377 unsigned long sram_base
;
378 struct device_node
*node
;
379 struct platform_device
*pdev
= NULL
;
381 for_each_compatible_node(node
, NULL
, "mmio-sram") {
382 pdev
= of_find_device_by_node(node
);
390 pr_warn("%s: failed to find sram device!\n", __func__
);
394 sram_pool
= gen_pool_get(&pdev
->dev
, NULL
);
396 pr_warn("%s: sram pool unavailable!\n", __func__
);
400 sram_base
= gen_pool_alloc(sram_pool
, at91_pm_suspend_in_sram_sz
);
402 pr_warn("%s: unable to alloc sram!\n", __func__
);
406 sram_pbase
= gen_pool_virt_to_phys(sram_pool
, sram_base
);
407 at91_suspend_sram_fn
= __arm_ioremap_exec(sram_pbase
,
408 at91_pm_suspend_in_sram_sz
, false);
409 if (!at91_suspend_sram_fn
) {
410 pr_warn("SRAM: Could not map\n");
414 /* Copy the pm suspend handler to SRAM */
415 at91_suspend_sram_fn
= fncpy(at91_suspend_sram_fn
,
416 &at91_pm_suspend_in_sram
, at91_pm_suspend_in_sram_sz
);
419 static const struct of_device_id atmel_pmc_ids
[] __initconst
= {
420 { .compatible
= "atmel,at91rm9200-pmc" },
421 { .compatible
= "atmel,at91sam9260-pmc" },
422 { .compatible
= "atmel,at91sam9g45-pmc" },
423 { .compatible
= "atmel,at91sam9n12-pmc" },
424 { .compatible
= "atmel,at91sam9x5-pmc" },
425 { .compatible
= "atmel,sama5d3-pmc" },
426 { .compatible
= "atmel,sama5d2-pmc" },
430 static void __init
at91_pm_init(void (*pm_idle
)(void))
432 struct device_node
*pmc_np
;
434 if (at91_cpuidle_device
.dev
.platform_data
)
435 platform_device_register(&at91_cpuidle_device
);
437 pmc_np
= of_find_matching_node(NULL
, atmel_pmc_ids
);
438 pmc
= of_iomap(pmc_np
, 0);
440 pr_err("AT91: PM not supported, PMC not found\n");
445 arm_pm_idle
= pm_idle
;
449 if (at91_suspend_sram_fn
)
450 suspend_set_ops(&at91_pm_ops
);
452 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
455 void __init
at91rm9200_pm_init(void)
460 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
462 at91_ramc_write(0, AT91_MC_SDRAMC_LPR
, 0);
464 at91_pm_data
.uhp_udp_mask
= AT91RM9200_PMC_UHP
| AT91RM9200_PMC_UDP
;
465 at91_pm_data
.memctrl
= AT91_MEMCTRL_MC
;
467 at91_pm_init(at91rm9200_idle
);
470 void __init
at91sam9260_pm_init(void)
473 at91_pm_data
.memctrl
= AT91_MEMCTRL_SDRAMC
;
474 at91_pm_data
.uhp_udp_mask
= AT91SAM926x_PMC_UHP
| AT91SAM926x_PMC_UDP
;
475 at91_pm_init(at91sam9_idle
);
478 void __init
at91sam9g45_pm_init(void)
481 at91_pm_data
.uhp_udp_mask
= AT91SAM926x_PMC_UHP
;
482 at91_pm_data
.memctrl
= AT91_MEMCTRL_DDRSDR
;
483 at91_pm_init(at91sam9_idle
);
486 void __init
at91sam9x5_pm_init(void)
489 at91_pm_data
.uhp_udp_mask
= AT91SAM926x_PMC_UHP
| AT91SAM926x_PMC_UDP
;
490 at91_pm_data
.memctrl
= AT91_MEMCTRL_DDRSDR
;
491 at91_pm_init(at91sam9_idle
);
494 void __init
sama5_pm_init(void)
497 at91_pm_data
.uhp_udp_mask
= AT91SAM926x_PMC_UHP
| AT91SAM926x_PMC_UDP
;
498 at91_pm_data
.memctrl
= AT91_MEMCTRL_DDRSDR
;