arch/arm/mach-at91/pm.h

   1 #ifdef CONFIG_ARCH_AT91RM9200
   2 #include <mach/at91rm9200_mc.h>
   3
   4 /*
   5  * The AT91RM9200 goes into self-refresh mode with this command, and will
   6  * terminate self-refresh automatically on the next SDRAM access.
   7  *
   8  * Self-refresh mode is exited as soon as a memory access is made, but we don't
   9  * know for sure when that happens. However, we need to restore the low-power
  10  * mode if it was enabled before going idle. Restoring low-power mode while
  11  * still in self-refresh is "not recommended", but seems to work.
  12  */
  13
  14 static inline u32 sdram_selfrefresh_enable(void)
  15 {
  16         u32 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
  17
  18         at91_sys_write(AT91_SDRAMC_LPR, 0);
  19         at91_sys_write(AT91_SDRAMC_SRR, 1);
  20         return saved_lpr;
  21 }
  22
  23 #define sdram_selfrefresh_disable(saved_lpr)    at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
  24 #define wait_for_interrupt_enable()             asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
  25                                                                 : : "r" (0))
  26
  27 #elif defined(CONFIG_ARCH_AT91SAM9G45)
  28 #include <mach/at91sam9_ddrsdr.h>
  29
  30 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
  31  * remember.
  32  */
  33 static u32 saved_lpr1;
  34
  35 static inline u32 sdram_selfrefresh_enable(void)
  36 {
  37         /* Those tow values allow us to delay self-refresh activation
  38          * to the maximum. */
  39         u32 lpr0, lpr1;
  40         u32 saved_lpr0;
  41
  42         saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
  43         lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
  44         lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
  45
  46         saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
  47         lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
  48         lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
  49
  50         /* self-refresh mode now */
  51         at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
  52         at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
  53
  54         return saved_lpr0;
  55 }
  56
  57 #define sdram_selfrefresh_disable(saved_lpr0)   \
  58         do { \
  59                 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
  60                 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
  61         } while (0)
  62 #define wait_for_interrupt_enable()             cpu_do_idle()
  63
  64 #else
  65 #include <mach/at91sam9_sdramc.h>
  66
  67 #ifdef CONFIG_ARCH_AT91SAM9263
  68 /*
  69  * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
  70  * handle those cases both here and in the Suspend-To-RAM support.
  71  */
  72 #warning Assuming EB1 SDRAM controller is *NOT* used
  73 #endif
  74
  75 static inline u32 sdram_selfrefresh_enable(void)
  76 {
  77         u32 saved_lpr, lpr;
  78
  79         saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
  80
  81         lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
  82         at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
  83         return saved_lpr;
  84 }
  85
  86 #define sdram_selfrefresh_disable(saved_lpr)    at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
  87 #define wait_for_interrupt_enable()             cpu_do_idle()
  88
  89 #endif