arch/arm/mach-bcm/platsmp.c

   1 /*
   2  * Copyright (C) 2014-2015 Broadcom Corporation
   3  * Copyright 2014 Linaro Limited
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation version 2.
   8  *
   9  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  10  * kind, whether express or implied; without even the implied warranty
  11  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/cpumask.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/sched.h>
  24 #include <linux/smp.h>
  25
  26 #include <asm/cacheflush.h>
  27 #include <asm/smp.h>
  28 #include <asm/smp_plat.h>
  29 #include <asm/smp_scu.h>
  30
  31 /* Size of mapped Cortex A9 SCU address space */
  32 #define CORTEX_A9_SCU_SIZE      0x58
  33
  34 #define SECONDARY_TIMEOUT_NS    NSEC_PER_MSEC   /* 1 msec (in nanoseconds) */
  35 #define BOOT_ADDR_CPUID_MASK    0x3
  36
  37 /* Name of device node property defining secondary boot register location */
  38 #define OF_SECONDARY_BOOT       "secondary-boot-reg"
  39 #define MPIDR_CPUID_BITMASK     0x3
  40
  41 /*
  42  * Enable the Cortex A9 Snoop Control Unit
  43  *
  44  * By the time this is called we already know there are multiple
  45  * cores present.  We assume we're running on a Cortex A9 processor,
  46  * so any trouble getting the base address register or getting the
  47  * SCU base is a problem.
  48  *
  49  * Return 0 if successful or an error code otherwise.
  50  */
  51 static int __init scu_a9_enable(void)
  52 {
  53         unsigned long config_base;
  54         void __iomem *scu_base;
  55
  56         if (!scu_a9_has_base()) {
  57                 pr_err("no configuration base address register!\n");
  58                 return -ENXIO;
  59         }
  60
  61         /* Config base address register value is zero for uniprocessor */
  62         config_base = scu_a9_get_base();
  63         if (!config_base) {
  64                 pr_err("hardware reports only one core\n");
  65                 return -ENOENT;
  66         }
  67
  68         scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
  69         if (!scu_base) {
  70                 pr_err("failed to remap config base (%lu/%u) for SCU\n",
  71                         config_base, CORTEX_A9_SCU_SIZE);
  72                 return -ENOMEM;
  73         }
  74
  75         scu_enable(scu_base);
  76
  77         iounmap(scu_base);      /* That's the last we'll need of this */
  78
  79         return 0;
  80 }
  81
  82 static u32 secondary_boot_addr_for(unsigned int cpu)
  83 {
  84         u32 secondary_boot_addr = 0;
  85         struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);
  86
  87         if (!cpu_node) {
  88                 pr_err("Failed to find device tree node for CPU%u\n", cpu);
  89                 return 0;
  90         }
  91
  92         if (of_property_read_u32(cpu_node,
  93                                  OF_SECONDARY_BOOT,
  94                                  &secondary_boot_addr))
  95                 pr_err("required secondary boot register not specified for CPU%u\n",
  96                         cpu);
  97
  98         of_node_put(cpu_node);
  99
 100         return secondary_boot_addr;
 101 }
 102
 103 static int nsp_write_lut(unsigned int cpu)
 104 {
 105         void __iomem *sku_rom_lut;
 106         phys_addr_t secondary_startup_phy;
 107         const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
 108
 109         if (!secondary_boot_addr)
 110                 return -EINVAL;
 111
 112         sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr,
 113                                       sizeof(phys_addr_t));
 114         if (!sku_rom_lut) {
 115                 pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu);
 116                 return -ENOMEM;
 117         }
 118
 119         secondary_startup_phy = virt_to_phys(secondary_startup);
 120         BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
 121
 122         writel_relaxed(secondary_startup_phy, sku_rom_lut);
 123
 124         /* Ensure the write is visible to the secondary core */
 125         smp_wmb();
 126
 127         iounmap(sku_rom_lut);
 128
 129         return 0;
 130 }
 131
 132 static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
 133 {
 134         const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
 135
 136         /* Enable the SCU on Cortex A9 based SoCs */
 137         if (scu_a9_enable()) {
 138                 /* Update the CPU present map to reflect uniprocessor mode */
 139                 pr_warn("failed to enable A9 SCU - disabling SMP\n");
 140                 init_cpu_present(&only_cpu_0);
 141         }
 142 }
 143
 144 /*
 145  * The ROM code has the secondary cores looping, waiting for an event.
 146  * When an event occurs each core examines the bottom two bits of the
 147  * secondary boot register.  When a core finds those bits contain its
 148  * own core id, it performs initialization, including computing its boot
 149  * address by clearing the boot register value's bottom two bits.  The
 150  * core signals that it is beginning its execution by writing its boot
 151  * address back to the secondary boot register, and finally jumps to
 152  * that address.
 153  *
 154  * So to start a core executing we need to:
 155  * - Encode the (hardware) CPU id with the bottom bits of the secondary
 156  *   start address.
 157  * - Write that value into the secondary boot register.
 158  * - Generate an event to wake up the secondary CPU(s).
 159  * - Wait for the secondary boot register to be re-written, which
 160  *   indicates the secondary core has started.
 161  */
 162 static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
 163 {
 164         void __iomem *boot_reg;
 165         phys_addr_t boot_func;
 166         u64 start_clock;
 167         u32 cpu_id;
 168         u32 boot_val;
 169         bool timeout = false;
 170         const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
 171
 172         cpu_id = cpu_logical_map(cpu);
 173         if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
 174                 pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
 175                 return -EINVAL;
 176         }
 177
 178         if (!secondary_boot_addr)
 179                 return -EINVAL;
 180
 181         boot_reg = ioremap_nocache((phys_addr_t)secondary_boot_addr,
 182                                    sizeof(phys_addr_t));
 183         if (!boot_reg) {
 184                 pr_err("unable to map boot register for cpu %u\n", cpu_id);
 185                 return -ENOMEM;
 186         }
 187
 188         /*
 189          * Secondary cores will start in secondary_startup(),
 190          * defined in "arch/arm/kernel/head.S"
 191          */
 192         boot_func = virt_to_phys(secondary_startup);
 193         BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
 194         BUG_ON(boot_func > (phys_addr_t)U32_MAX);
 195
 196         /* The core to start is encoded in the low bits */
 197         boot_val = (u32)boot_func | cpu_id;
 198         writel_relaxed(boot_val, boot_reg);
 199
 200         sev();
 201
 202         /* The low bits will be cleared once the core has started */
 203         start_clock = local_clock();
 204         while (!timeout && readl_relaxed(boot_reg) == boot_val)
 205                 timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
 206
 207         iounmap(boot_reg);
 208
 209         if (!timeout)
 210                 return 0;
 211
 212         pr_err("timeout waiting for cpu %u to start\n", cpu_id);
 213
 214         return -ENXIO;
 215 }
 216
 217 /* Cluster Dormant Control command to bring CPU into a running state */
 218 #define CDC_CMD                 6
 219 #define CDC_CMD_OFFSET          0
 220 #define CDC_CMD_REG(cpu)        (CDC_CMD_OFFSET + 4*(cpu))
 221
 222 /*
 223  * BCM23550 has a Cluster Dormant Control block that keeps the core in
 224  * idle state. A command needs to be sent to the block to bring the CPU
 225  * into running state.
 226  */
 227 static int bcm23550_boot_secondary(unsigned int cpu, struct task_struct *idle)
 228 {
 229         void __iomem *cdc_base;
 230         struct device_node *dn;
 231         char *name;
 232         int ret;
 233
 234         /* Make sure a CDC node exists before booting the
 235          * secondary core.
 236          */
 237         name = "brcm,bcm23550-cdc";
 238         dn = of_find_compatible_node(NULL, NULL, name);
 239         if (!dn) {
 240                 pr_err("unable to find cdc node\n");
 241                 return -ENODEV;
 242         }
 243
 244         cdc_base = of_iomap(dn, 0);
 245         of_node_put(dn);
 246
 247         if (!cdc_base) {
 248                 pr_err("unable to remap cdc base register\n");
 249                 return -ENOMEM;
 250         }
 251
 252         /* Boot the secondary core */
 253         ret = kona_boot_secondary(cpu, idle);
 254         if (ret)
 255                 goto out;
 256
 257         /* Bring this CPU to RUN state so that nIRQ nFIQ
 258          * signals are unblocked.
 259          */
 260         writel_relaxed(CDC_CMD, cdc_base + CDC_CMD_REG(cpu));
 261
 262 out:
 263         iounmap(cdc_base);
 264
 265         return ret;
 266 }
 267
 268 static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
 269 {
 270         int ret;
 271
 272         /*
 273          * After wake up, secondary core branches to the startup
 274          * address programmed at SKU ROM LUT location.
 275          */
 276         ret = nsp_write_lut(cpu);
 277         if (ret) {
 278                 pr_err("unable to write startup addr to SKU ROM LUT\n");
 279                 goto out;
 280         }
 281
 282         /* Send a CPU wakeup interrupt to the secondary core */
 283         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 284
 285 out:
 286         return ret;
 287 }
 288
 289 static const struct smp_operations kona_smp_ops __initconst = {
 290         .smp_prepare_cpus       = bcm_smp_prepare_cpus,
 291         .smp_boot_secondary     = kona_boot_secondary,
 292 };
 293 CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
 294                         &kona_smp_ops);
 295
 296 static const struct smp_operations bcm23550_smp_ops __initconst = {
 297         .smp_boot_secondary     = bcm23550_boot_secondary,
 298 };
 299 CPU_METHOD_OF_DECLARE(bcm_smp_bcm23550, "brcm,bcm23550",
 300                         &bcm23550_smp_ops);
 301
 302 static const struct smp_operations nsp_smp_ops __initconst = {
 303         .smp_prepare_cpus       = bcm_smp_prepare_cpus,
 304         .smp_boot_secondary     = nsp_boot_secondary,
 305 };
 306 CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);