arch/arm/mach-bcm/platsmp.c

   1 /*
   2  * Copyright (C) 2014-2015 Broadcom Corporation
   3  * Copyright 2014 Linaro Limited
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation version 2.
   8  *
   9  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  10  * kind, whether express or implied; without even the implied warranty
  11  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/cpumask.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/sched.h>
  24 #include <linux/smp.h>
  25
  26 #include <asm/cacheflush.h>
  27 #include <asm/smp.h>
  28 #include <asm/smp_plat.h>
  29 #include <asm/smp_scu.h>
  30
  31 /* Size of mapped Cortex A9 SCU address space */
  32 #define CORTEX_A9_SCU_SIZE      0x58
  33
  34 #define SECONDARY_TIMEOUT_NS    NSEC_PER_MSEC   /* 1 msec (in nanoseconds) */
  35 #define BOOT_ADDR_CPUID_MASK    0x3
  36
  37 /* Name of device node property defining secondary boot register location */
  38 #define OF_SECONDARY_BOOT       "secondary-boot-reg"
  39 #define MPIDR_CPUID_BITMASK     0x3
  40
  41 /* I/O address of register used to coordinate secondary core startup */
  42 static u32      secondary_boot_addr;
  43
  44 /*
  45  * Enable the Cortex A9 Snoop Control Unit
  46  *
  47  * By the time this is called we already know there are multiple
  48  * cores present.  We assume we're running on a Cortex A9 processor,
  49  * so any trouble getting the base address register or getting the
  50  * SCU base is a problem.
  51  *
  52  * Return 0 if successful or an error code otherwise.
  53  */
  54 static int __init scu_a9_enable(void)
  55 {
  56         unsigned long config_base;
  57         void __iomem *scu_base;
  58
  59         if (!scu_a9_has_base()) {
  60                 pr_err("no configuration base address register!\n");
  61                 return -ENXIO;
  62         }
  63
  64         /* Config base address register value is zero for uniprocessor */
  65         config_base = scu_a9_get_base();
  66         if (!config_base) {
  67                 pr_err("hardware reports only one core\n");
  68                 return -ENOENT;
  69         }
  70
  71         scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
  72         if (!scu_base) {
  73                 pr_err("failed to remap config base (%lu/%u) for SCU\n",
  74                         config_base, CORTEX_A9_SCU_SIZE);
  75                 return -ENOMEM;
  76         }
  77
  78         scu_enable(scu_base);
  79
  80         iounmap(scu_base);      /* That's the last we'll need of this */
  81
  82         return 0;
  83 }
  84
  85 static int nsp_write_lut(void)
  86 {
  87         void __iomem *sku_rom_lut;
  88         phys_addr_t secondary_startup_phy;
  89
  90         if (!secondary_boot_addr) {
  91                 pr_warn("required secondary boot register not specified\n");
  92                 return -EINVAL;
  93         }
  94
  95         sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr,
  96                                                 sizeof(secondary_boot_addr));
  97         if (!sku_rom_lut) {
  98                 pr_warn("unable to ioremap SKU-ROM LUT register\n");
  99                 return -ENOMEM;
 100         }
 101
 102         secondary_startup_phy = virt_to_phys(secondary_startup);
 103         BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
 104
 105         writel_relaxed(secondary_startup_phy, sku_rom_lut);
 106
 107         /* Ensure the write is visible to the secondary core */
 108         smp_wmb();
 109
 110         iounmap(sku_rom_lut);
 111
 112         return 0;
 113 }
 114
 115 static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
 116 {
 117         static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
 118         struct device_node *cpus_node = NULL;
 119         struct device_node *cpu_node = NULL;
 120         int ret;
 121
 122         /*
 123          * This function is only called via smp_ops->smp_prepare_cpu().
 124          * That only happens if a "/cpus" device tree node exists
 125          * and has an "enable-method" property that selects the SMP
 126          * operations defined herein.
 127          */
 128         cpus_node = of_find_node_by_path("/cpus");
 129         if (!cpus_node)
 130                 return;
 131
 132         for_each_child_of_node(cpus_node, cpu_node) {
 133                 u32 cpuid;
 134
 135                 if (of_node_cmp(cpu_node->type, "cpu"))
 136                         continue;
 137
 138                 if (of_property_read_u32(cpu_node, "reg", &cpuid)) {
 139                         pr_debug("%s: missing reg property\n",
 140                                      cpu_node->full_name);
 141                         ret = -ENOENT;
 142                         goto out;
 143                 }
 144
 145                 /*
 146                  * "secondary-boot-reg" property should be defined only
 147                  * for secondary cpu
 148                  */
 149                 if ((cpuid & MPIDR_CPUID_BITMASK) == 1) {
 150                         /*
 151                          * Our secondary enable method requires a
 152                          * "secondary-boot-reg" property to specify a register
 153                          * address used to request the ROM code boot a secondary
 154                          * core. If we have any trouble getting this we fall
 155                          * back to uniprocessor mode.
 156                          */
 157                         if (of_property_read_u32(cpu_node,
 158                                                 OF_SECONDARY_BOOT,
 159                                                 &secondary_boot_addr)) {
 160                                 pr_warn("%s: no" OF_SECONDARY_BOOT "property\n",
 161                                         cpu_node->name);
 162                                 ret = -ENOENT;
 163                                 goto out;
 164                         }
 165                 }
 166         }
 167
 168         /*
 169          * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
 170          * returned, the SoC reported a uniprocessor configuration.
 171          * We bail on any other error.
 172          */
 173         ret = scu_a9_enable();
 174 out:
 175         of_node_put(cpu_node);
 176         of_node_put(cpus_node);
 177
 178         if (ret) {
 179                 /* Update the CPU present map to reflect uniprocessor mode */
 180                 pr_warn("disabling SMP\n");
 181                 init_cpu_present(&only_cpu_0);
 182         }
 183 }
 184
 185 /*
 186  * The ROM code has the secondary cores looping, waiting for an event.
 187  * When an event occurs each core examines the bottom two bits of the
 188  * secondary boot register.  When a core finds those bits contain its
 189  * own core id, it performs initialization, including computing its boot
 190  * address by clearing the boot register value's bottom two bits.  The
 191  * core signals that it is beginning its execution by writing its boot
 192  * address back to the secondary boot register, and finally jumps to
 193  * that address.
 194  *
 195  * So to start a core executing we need to:
 196  * - Encode the (hardware) CPU id with the bottom bits of the secondary
 197  *   start address.
 198  * - Write that value into the secondary boot register.
 199  * - Generate an event to wake up the secondary CPU(s).
 200  * - Wait for the secondary boot register to be re-written, which
 201  *   indicates the secondary core has started.
 202  */
 203 static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
 204 {
 205         void __iomem *boot_reg;
 206         phys_addr_t boot_func;
 207         u64 start_clock;
 208         u32 cpu_id;
 209         u32 boot_val;
 210         bool timeout = false;
 211
 212         cpu_id = cpu_logical_map(cpu);
 213         if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
 214                 pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
 215                 return -EINVAL;
 216         }
 217
 218         if (!secondary_boot_addr) {
 219                 pr_err("required secondary boot register not specified\n");
 220                 return -EINVAL;
 221         }
 222
 223         boot_reg = ioremap_nocache(
 224                         (phys_addr_t)secondary_boot_addr, sizeof(u32));
 225         if (!boot_reg) {
 226                 pr_err("unable to map boot register for cpu %u\n", cpu_id);
 227                 return -ENOMEM;
 228         }
 229
 230         /*
 231          * Secondary cores will start in secondary_startup(),
 232          * defined in "arch/arm/kernel/head.S"
 233          */
 234         boot_func = virt_to_phys(secondary_startup);
 235         BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
 236         BUG_ON(boot_func > (phys_addr_t)U32_MAX);
 237
 238         /* The core to start is encoded in the low bits */
 239         boot_val = (u32)boot_func | cpu_id;
 240         writel_relaxed(boot_val, boot_reg);
 241
 242         sev();
 243
 244         /* The low bits will be cleared once the core has started */
 245         start_clock = local_clock();
 246         while (!timeout && readl_relaxed(boot_reg) == boot_val)
 247                 timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
 248
 249         iounmap(boot_reg);
 250
 251         if (!timeout)
 252                 return 0;
 253
 254         pr_err("timeout waiting for cpu %u to start\n", cpu_id);
 255
 256         return -ENXIO;
 257 }
 258
 259 /* Cluster Dormant Control command to bring CPU into a running state */
 260 #define CDC_CMD                 6
 261 #define CDC_CMD_OFFSET          0
 262 #define CDC_CMD_REG(cpu)        (CDC_CMD_OFFSET + 4*(cpu))
 263
 264 /*
 265  * BCM23550 has a Cluster Dormant Control block that keeps the core in
 266  * idle state. A command needs to be sent to the block to bring the CPU
 267  * into running state.
 268  */
 269 static int bcm23550_boot_secondary(unsigned int cpu, struct task_struct *idle)
 270 {
 271         void __iomem *cdc_base;
 272         struct device_node *dn;
 273         char *name;
 274         int ret;
 275
 276         /* Make sure a CDC node exists before booting the
 277          * secondary core.
 278          */
 279         name = "brcm,bcm23550-cdc";
 280         dn = of_find_compatible_node(NULL, NULL, name);
 281         if (!dn) {
 282                 pr_err("unable to find cdc node\n");
 283                 return -ENODEV;
 284         }
 285
 286         cdc_base = of_iomap(dn, 0);
 287         of_node_put(dn);
 288
 289         if (!cdc_base) {
 290                 pr_err("unable to remap cdc base register\n");
 291                 return -ENOMEM;
 292         }
 293
 294         /* Boot the secondary core */
 295         ret = kona_boot_secondary(cpu, idle);
 296         if (ret)
 297                 goto out;
 298
 299         /* Bring this CPU to RUN state so that nIRQ nFIQ
 300          * signals are unblocked.
 301          */
 302         writel_relaxed(CDC_CMD, cdc_base + CDC_CMD_REG(cpu));
 303
 304 out:
 305         iounmap(cdc_base);
 306
 307         return ret;
 308 }
 309
 310 static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
 311 {
 312         int ret;
 313
 314         /*
 315          * After wake up, secondary core branches to the startup
 316          * address programmed at SKU ROM LUT location.
 317          */
 318         ret = nsp_write_lut();
 319         if (ret) {
 320                 pr_err("unable to write startup addr to SKU ROM LUT\n");
 321                 goto out;
 322         }
 323
 324         /* Send a CPU wakeup interrupt to the secondary core */
 325         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 326
 327 out:
 328         return ret;
 329 }
 330
 331 static const struct smp_operations bcm_smp_ops __initconst = {
 332         .smp_prepare_cpus       = bcm_smp_prepare_cpus,
 333         .smp_boot_secondary     = kona_boot_secondary,
 334 };
 335 CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
 336                         &bcm_smp_ops);
 337
 338 static const struct smp_operations bcm23550_smp_ops __initconst = {
 339         .smp_boot_secondary     = bcm23550_boot_secondary,
 340 };
 341 CPU_METHOD_OF_DECLARE(bcm_smp_bcm23550, "brcm,bcm23550",
 342                         &bcm23550_smp_ops);
 343
 344 static const struct smp_operations nsp_smp_ops __initconst = {
 345         .smp_prepare_cpus       = bcm_smp_prepare_cpus,
 346         .smp_boot_secondary     = nsp_boot_secondary,
 347 };
 348 CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);