arch/arm/mach-bcmring/core.c

   1 /*
   2  *  derived from linux/arch/arm/mach-versatile/core.c
   3  *  linux/arch/arm/mach-bcmring/core.c
   4  *
   5  *  Copyright (C) 1999 - 2003 ARM Limited
   6  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22 /* Portions copyright Broadcom 2008 */
  23
  24 #include <linux/init.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/sysdev.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/amba/bus.h>
  31 #include <linux/clocksource.h>
  32 #include <linux/clockchips.h>
  33 #include <linux/clkdev.h>
  34
  35 #include <mach/csp/mm_addr.h>
  36 #include <mach/hardware.h>
  37 #include <linux/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/hardware/arm_timer.h>
  40 #include <asm/hardware/timer-sp.h>
  41 #include <asm/mach-types.h>
  42
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/flash.h>
  45 #include <asm/mach/irq.h>
  46 #include <asm/mach/time.h>
  47 #include <asm/mach/map.h>
  48
  49 #include <cfg_global.h>
  50
  51 #include "clock.h"
  52
  53 #include <csp/secHw.h>
  54 #include <mach/csp/secHw_def.h>
  55 #include <mach/csp/chipcHw_inline.h>
  56 #include <mach/csp/tmrHw_reg.h>
  57
  58 #define AMBA_DEVICE(name, initname, base, plat, size)       \
  59 static struct amba_device name##_device = {     \
  60    .dev = {                                     \
  61       .coherent_dma_mask = ~0,                  \
  62       .init_name = initname,                    \
  63       .platform_data = plat                     \
  64    },                                           \
  65    .res = {                                     \
  66       .start = MM_ADDR_IO_##base,               \
  67                 .end = MM_ADDR_IO_##base + (size) - 1,    \
  68       .flags = IORESOURCE_MEM                   \
  69    },                                           \
  70    .dma_mask = ~0,                              \
  71    .irq = {                                     \
  72       IRQ_##base                                \
  73    }                                            \
  74 }
  75
  76
  77 AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
  78 AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
  79
  80 static struct clk pll1_clk = {
  81         .name = "PLL1",
  82         .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
  83         .rate_hz = 2000000000,
  84         .use_cnt = 7,
  85 };
  86
  87 static struct clk uart_clk = {
  88         .name = "UART",
  89         .type = CLK_TYPE_PROGRAMMABLE,
  90         .csp_id = chipcHw_CLOCK_UART,
  91         .rate_hz = HW_CFG_UART_CLK_HZ,
  92         .parent = &pll1_clk,
  93 };
  94
  95 static struct clk dummy_apb_pclk = {
  96         .name = "BUSCLK",
  97         .type = CLK_TYPE_PRIMARY,
  98         .mode = CLK_MODE_XTAL,
  99 };
 100
 101 /* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
 102 #if defined(CONFIG_ARCH_FPGA11107)
 103 /* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
 104 /* slow down Linux's sense of time */
 105 #define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
 106 #define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
 107 #define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
 108 #define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
 109 #else
 110 #define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
 111 #define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
 112 #define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
 113 #define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
 114 #endif
 115
 116 static struct clk sp804_timer1_clk = {
 117         .name = "sp804-timer-1",
 118         .type = CLK_TYPE_PRIMARY,
 119         .mode = CLK_MODE_XTAL,
 120         .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
 121 };
 122
 123 static struct clk sp804_timer3_clk = {
 124         .name = "sp804-timer-3",
 125         .type = CLK_TYPE_PRIMARY,
 126         .mode = CLK_MODE_XTAL,
 127         .rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
 128 };
 129
 130 static struct clk_lookup lookups[] = {
 131         {                       /* Bus clock */
 132                 .con_id = "apb_pclk",
 133                 .clk = &dummy_apb_pclk,
 134         }, {                    /* UART0 */
 135                 .dev_id = "uarta",
 136                 .clk = &uart_clk,
 137         }, {                    /* UART1 */
 138                 .dev_id = "uartb",
 139                 .clk = &uart_clk,
 140         }, {                    /* SP804 timer 1 */
 141                 .dev_id = "sp804",
 142                 .con_id = "timer1",
 143                 .clk = &sp804_timer1_clk,
 144         }, {                    /* SP804 timer 3 */
 145                 .dev_id = "sp804",
 146                 .con_id = "timer3",
 147                 .clk = &sp804_timer3_clk,
 148         }
 149 };
 150
 151 static struct amba_device *amba_devs[] __initdata = {
 152         &uartA_device,
 153         &uartB_device,
 154 };
 155
 156 void __init bcmring_amba_init(void)
 157 {
 158         int i;
 159         u32 bus_clock;
 160
 161 /* Linux is run initially in non-secure mode. Secure peripherals */
 162 /* generate FIQ, and must be handled in secure mode. Until we have */
 163 /* a linux security monitor implementation, keep everything in */
 164 /* non-secure mode. */
 165         chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
 166         secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
 167                           secHw_BLK_MASK_KEY_SCAN |
 168                           secHw_BLK_MASK_TOUCH_SCREEN |
 169                           secHw_BLK_MASK_UART0 |
 170                           secHw_BLK_MASK_UART1 |
 171                           secHw_BLK_MASK_WATCHDOG |
 172                           secHw_BLK_MASK_SPUM |
 173                           secHw_BLK_MASK_DDR2 |
 174                           secHw_BLK_MASK_SPU |
 175                           secHw_BLK_MASK_PKA |
 176                           secHw_BLK_MASK_RNG |
 177                           secHw_BLK_MASK_RTC |
 178                           secHw_BLK_MASK_OTP |
 179                           secHw_BLK_MASK_BOOT |
 180                           secHw_BLK_MASK_MPU |
 181                           secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
 182
 183         /* Only the devices attached to the AMBA bus are enabled just before the bus is */
 184         /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
 185         /* driver to access these blocks. The bus is probed, and the drivers are loaded. */
 186         /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
 187         bus_clock = chipcHw_REG_BUS_CLOCK_GE
 188             | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
 189
 190         chipcHw_busInterfaceClockEnable(bus_clock);
 191
 192         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 193                 struct amba_device *d = amba_devs[i];
 194                 amba_device_register(d, &iomem_resource);
 195         }
 196 }
 197
 198 /*
 199  * Where is the timer (VA)?
 200  */
 201 #define TIMER0_VA_BASE          ((void __iomem *)MM_IO_BASE_TMR)
 202 #define TIMER1_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
 203 #define TIMER2_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
 204 #define TIMER3_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
 205
 206 #define TICKS_PER_uSEC     TIMER0_FREQUENCY_MHZ
 207
 208 /*
 209  *  These are useconds NOT ticks.
 210  *
 211  */
 212 #define mSEC_1                          1000
 213 #define mSEC_10                         (mSEC_1 * 10)
 214
 215 /*
 216  * How long is the timer interval?
 217  */
 218 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 219 #if TIMER_INTERVAL >= 0x100000
 220 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 221 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 222 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 223 #elif TIMER_INTERVAL >= 0x10000
 224 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)   /* Divide by 16 */
 225 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 226 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 227 #else
 228 #define TIMER_RELOAD    (TIMER_INTERVAL)
 229 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 230 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 231 #endif
 232
 233 static void timer_set_mode(enum clock_event_mode mode,
 234                            struct clock_event_device *clk)
 235 {
 236         unsigned long ctrl;
 237
 238         switch (mode) {
 239         case CLOCK_EVT_MODE_PERIODIC:
 240                 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
 241
 242                 ctrl = TIMER_CTRL_PERIODIC;
 243                 ctrl |=
 244                     TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE |
 245                     TIMER_CTRL_ENABLE;
 246                 break;
 247         case CLOCK_EVT_MODE_ONESHOT:
 248                 /* period set, and timer enabled in 'next_event' hook */
 249                 ctrl = TIMER_CTRL_ONESHOT;
 250                 ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 251                 break;
 252         case CLOCK_EVT_MODE_UNUSED:
 253         case CLOCK_EVT_MODE_SHUTDOWN:
 254         default:
 255                 ctrl = 0;
 256         }
 257
 258         writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
 259 }
 260
 261 static int timer_set_next_event(unsigned long evt,
 262                                 struct clock_event_device *unused)
 263 {
 264         unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
 265
 266         writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
 267         writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
 268
 269         return 0;
 270 }
 271
 272 static struct clock_event_device timer0_clockevent = {
 273         .name = "timer0",
 274         .shift = 32,
 275         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 276         .set_mode = timer_set_mode,
 277         .set_next_event = timer_set_next_event,
 278 };
 279
 280 /*
 281  * IRQ handler for the timer
 282  */
 283 static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
 284 {
 285         struct clock_event_device *evt = &timer0_clockevent;
 286
 287         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 288
 289         evt->event_handler(evt);
 290
 291         return IRQ_HANDLED;
 292 }
 293
 294 static struct irqaction bcmring_timer_irq = {
 295         .name = "bcmring Timer Tick",
 296         .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 297         .handler = bcmring_timer_interrupt,
 298 };
 299
 300 static int __init bcmring_clocksource_init(void)
 301 {
 302         /* setup timer1 as free-running clocksource */
 303         sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
 304
 305         /* setup timer3 as free-running clocksource */
 306         sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
 307
 308         return 0;
 309 }
 310
 311 /*
 312  * Set up timer interrupt, and return the current time in seconds.
 313  */
 314 void __init bcmring_init_timer(void)
 315 {
 316         printk(KERN_INFO "bcmring_init_timer\n");
 317         /*
 318          * Initialise to a known state (all timers off)
 319          */
 320         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 321         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 322         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 323         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 324
 325         /*
 326          * Make irqs happen for the system timer
 327          */
 328         setup_irq(IRQ_TIMER0, &bcmring_timer_irq);
 329
 330         bcmring_clocksource_init();
 331
 332         timer0_clockevent.mult =
 333             div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
 334         timer0_clockevent.max_delta_ns =
 335             clockevent_delta2ns(0xffffffff, &timer0_clockevent);
 336         timer0_clockevent.min_delta_ns =
 337             clockevent_delta2ns(0xf, &timer0_clockevent);
 338
 339         timer0_clockevent.cpumask = cpumask_of(0);
 340         clockevents_register_device(&timer0_clockevent);
 341 }
 342
 343 struct sys_timer bcmring_timer = {
 344         .init = bcmring_init_timer,
 345 };
 346
 347 void __init bcmring_init_early(void)
 348 {
 349         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 350 }