2 * Copyright 1999 - 2003 ARM Limited
3 * Copyright 2000 Deep Blue Solutions Ltd
4 * Copyright 2008 Cavium Networks
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/clockchips.h>
15 #include <linux/irqchip/arm-gic.h>
16 #include <asm/mach/map.h>
17 #include <asm/mach/time.h>
18 #include <asm/mach/irq.h>
19 #include <asm/hardware/cache-l2x0.h>
20 #include <mach/cns3xxx.h>
23 static struct map_desc cns3xxx_io_desc
[] __initdata
= {
25 .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT
,
26 .pfn
= __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE
),
30 .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT
,
31 .pfn
= __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE
),
35 .virtual = CNS3XXX_GPIOA_BASE_VIRT
,
36 .pfn
= __phys_to_pfn(CNS3XXX_GPIOA_BASE
),
40 .virtual = CNS3XXX_GPIOB_BASE_VIRT
,
41 .pfn
= __phys_to_pfn(CNS3XXX_GPIOB_BASE
),
45 .virtual = CNS3XXX_MISC_BASE_VIRT
,
46 .pfn
= __phys_to_pfn(CNS3XXX_MISC_BASE
),
50 .virtual = CNS3XXX_PM_BASE_VIRT
,
51 .pfn
= __phys_to_pfn(CNS3XXX_PM_BASE
),
57 void __init
cns3xxx_map_io(void)
59 iotable_init(cns3xxx_io_desc
, ARRAY_SIZE(cns3xxx_io_desc
));
62 /* used by entry-macro.S */
63 void __init
cns3xxx_init_irq(void)
65 gic_init(0, 29, IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT
),
66 IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT
));
69 void cns3xxx_power_off(void)
71 u32 __iomem
*pm_base
= IOMEM(CNS3XXX_PM_BASE_VIRT
);
74 printk(KERN_INFO
"powering system down...\n");
76 clkctrl
= readl(pm_base
+ PM_SYS_CLK_CTRL_OFFSET
);
77 clkctrl
&= 0xfffff1ff;
78 clkctrl
|= (0x5 << 9); /* Hibernate */
79 writel(clkctrl
, pm_base
+ PM_SYS_CLK_CTRL_OFFSET
);
86 static void __iomem
*cns3xxx_tmr1
;
88 static void cns3xxx_timer_set_mode(enum clock_event_mode mode
,
89 struct clock_event_device
*clk
)
91 unsigned long ctrl
= readl(cns3xxx_tmr1
+ TIMER1_2_CONTROL_OFFSET
);
92 int pclk
= cns3xxx_cpu_clock() / 8;
96 case CLOCK_EVT_MODE_PERIODIC
:
97 reload
= pclk
* 20 / (3 * HZ
) * 0x25000;
98 writel(reload
, cns3xxx_tmr1
+ TIMER1_AUTO_RELOAD_OFFSET
);
99 ctrl
|= (1 << 0) | (1 << 2) | (1 << 9);
101 case CLOCK_EVT_MODE_ONESHOT
:
102 /* period set, and timer enabled in 'next_event' hook */
103 ctrl
|= (1 << 2) | (1 << 9);
105 case CLOCK_EVT_MODE_UNUSED
:
106 case CLOCK_EVT_MODE_SHUTDOWN
:
111 writel(ctrl
, cns3xxx_tmr1
+ TIMER1_2_CONTROL_OFFSET
);
114 static int cns3xxx_timer_set_next_event(unsigned long evt
,
115 struct clock_event_device
*unused
)
117 unsigned long ctrl
= readl(cns3xxx_tmr1
+ TIMER1_2_CONTROL_OFFSET
);
119 writel(evt
, cns3xxx_tmr1
+ TIMER1_AUTO_RELOAD_OFFSET
);
120 writel(ctrl
| (1 << 0), cns3xxx_tmr1
+ TIMER1_2_CONTROL_OFFSET
);
125 static struct clock_event_device cns3xxx_tmr1_clockevent
= {
126 .name
= "cns3xxx timer1",
127 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
128 .set_mode
= cns3xxx_timer_set_mode
,
129 .set_next_event
= cns3xxx_timer_set_next_event
,
131 .cpumask
= cpu_all_mask
,
134 static void __init
cns3xxx_clockevents_init(unsigned int timer_irq
)
136 cns3xxx_tmr1_clockevent
.irq
= timer_irq
;
137 clockevents_config_and_register(&cns3xxx_tmr1_clockevent
,
138 (cns3xxx_cpu_clock() >> 3) * 1000000,
143 * IRQ handler for the timer
145 static irqreturn_t
cns3xxx_timer_interrupt(int irq
, void *dev_id
)
147 struct clock_event_device
*evt
= &cns3xxx_tmr1_clockevent
;
148 u32 __iomem
*stat
= cns3xxx_tmr1
+ TIMER1_2_INTERRUPT_STATUS_OFFSET
;
151 /* Clear the interrupt */
153 writel(val
& ~(1 << 2), stat
);
155 evt
->event_handler(evt
);
160 static struct irqaction cns3xxx_timer_irq
= {
162 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
163 .handler
= cns3xxx_timer_interrupt
,
167 * Set up the clock source and clock events devices
169 static void __init
__cns3xxx_timer_init(unsigned int timer_irq
)
175 * Initialise to a known state (all timers off)
178 /* disable timer1 and timer2 */
179 writel(0, cns3xxx_tmr1
+ TIMER1_2_CONTROL_OFFSET
);
180 /* stop free running timer3 */
181 writel(0, cns3xxx_tmr1
+ TIMER_FREERUN_CONTROL_OFFSET
);
184 writel(0x5C800, cns3xxx_tmr1
+ TIMER1_COUNTER_OFFSET
);
185 writel(0x5C800, cns3xxx_tmr1
+ TIMER1_AUTO_RELOAD_OFFSET
);
187 writel(0, cns3xxx_tmr1
+ TIMER1_MATCH_V1_OFFSET
);
188 writel(0, cns3xxx_tmr1
+ TIMER1_MATCH_V2_OFFSET
);
190 /* mask irq, non-mask timer1 overflow */
191 irq_mask
= readl(cns3xxx_tmr1
+ TIMER1_2_INTERRUPT_MASK_OFFSET
);
192 irq_mask
&= ~(1 << 2);
194 writel(irq_mask
, cns3xxx_tmr1
+ TIMER1_2_INTERRUPT_MASK_OFFSET
);
197 val
= readl(cns3xxx_tmr1
+ TIMER1_2_CONTROL_OFFSET
);
199 writel(val
, cns3xxx_tmr1
+ TIMER1_2_CONTROL_OFFSET
);
202 writel(0, cns3xxx_tmr1
+ TIMER2_MATCH_V1_OFFSET
);
203 writel(0, cns3xxx_tmr1
+ TIMER2_MATCH_V2_OFFSET
);
206 irq_mask
= readl(cns3xxx_tmr1
+ TIMER1_2_INTERRUPT_MASK_OFFSET
);
207 irq_mask
|= ((1 << 3) | (1 << 4) | (1 << 5));
208 writel(irq_mask
, cns3xxx_tmr1
+ TIMER1_2_INTERRUPT_MASK_OFFSET
);
211 val
= readl(cns3xxx_tmr1
+ TIMER1_2_CONTROL_OFFSET
);
213 writel(val
, cns3xxx_tmr1
+ TIMER1_2_CONTROL_OFFSET
);
215 /* Make irqs happen for the system timer */
216 setup_irq(timer_irq
, &cns3xxx_timer_irq
);
218 cns3xxx_clockevents_init(timer_irq
);
221 void __init
cns3xxx_timer_init(void)
223 cns3xxx_tmr1
= IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT
);
225 __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0
);
228 #ifdef CONFIG_CACHE_L2X0
230 void __init
cns3xxx_l2x0_init(void)
232 void __iomem
*base
= ioremap(CNS3XXX_L2C_BASE
, SZ_4K
);
239 * Tag RAM Control register
241 * bit[10:8] - 1 cycle of write accesses latency
242 * bit[6:4] - 1 cycle of read accesses latency
243 * bit[3:0] - 1 cycle of setup latency
245 * 1 cycle of latency for setup, read and write accesses
247 val
= readl(base
+ L2X0_TAG_LATENCY_CTRL
);
249 writel(val
, base
+ L2X0_TAG_LATENCY_CTRL
);
252 * Data RAM Control register
254 * bit[10:8] - 1 cycles of write accesses latency
255 * bit[6:4] - 1 cycles of read accesses latency
256 * bit[3:0] - 1 cycle of setup latency
258 * 1 cycle of latency for setup, read and write accesses
260 val
= readl(base
+ L2X0_DATA_LATENCY_CTRL
);
262 writel(val
, base
+ L2X0_DATA_LATENCY_CTRL
);
264 /* 32 KiB, 8-way, parity disable */
265 l2x0_init(base
, 0x00540000, 0xfe000fff);
268 #endif /* CONFIG_CACHE_L2X0 */