arch/arm/mach-cns3xxx/pm.c

   1 /*
   2  * Copyright 2008 Cavium Networks
   3  *
   4  * This file is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License, Version 2, as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/delay.h>
  10 #include <mach/system.h>
  11 #include <mach/cns3xxx.h>
  12
  13 void cns3xxx_pwr_clk_en(unsigned int block)
  14 {
  15         PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
  16 }
  17
  18 void cns3xxx_pwr_power_up(unsigned int block)
  19 {
  20         PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
  21
  22         /* Wait for 300us for the PLL output clock locked. */
  23         udelay(300);
  24 };
  25
  26 void cns3xxx_pwr_power_down(unsigned int block)
  27 {
  28         /* write '1' to power down */
  29         PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
  30 };
  31
  32 static void cns3xxx_pwr_soft_rst_force(unsigned int block)
  33 {
  34         /*
  35          * bit 0, 28, 29 => program low to reset,
  36          * the other else program low and then high
  37          */
  38         if (block & 0x30000001) {
  39                 PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
  40         } else {
  41                 PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
  42                 PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
  43         }
  44 }
  45
  46 void cns3xxx_pwr_soft_rst(unsigned int block)
  47 {
  48         static unsigned int soft_reset;
  49
  50         if (soft_reset & block) {
  51                 /* SPI/I2C/GPIO use the same block, reset once. */
  52                 return;
  53         } else {
  54                 soft_reset |= block;
  55         }
  56         cns3xxx_pwr_soft_rst_force(block);
  57 }
  58
  59 void arch_reset(char mode, const char *cmd)
  60 {
  61         /*
  62          * To reset, we hit the on-board reset register
  63          * in the system FPGA.
  64          */
  65         cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
  66 }
  67
  68 /*
  69  * cns3xxx_cpu_clock - return CPU/L2 clock
  70  *  aclk: cpu clock/2
  71  *  hclk: cpu clock/4
  72  *  pclk: cpu clock/8
  73  */
  74 int cns3xxx_cpu_clock(void)
  75 {
  76         int cpu;
  77         int cpu_sel;
  78         int div_sel;
  79
  80         cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
  81         div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
  82
  83         cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
  84
  85         return cpu;
  86 }