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ARM: mach-davinci: move from ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size
[deliverable/linux.git] / arch / arm / mach-davinci / board-dm646x-evm.c
1 /*
2 * TI DaVinci DM646X EVM board
3 *
4 * Derived from: arch/arm/mach-davinci/board-evm.c
5 * Copyright (C) 2006 Texas Instruments.
6 *
7 * (C) 2007-2008, MontaVista Software, Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 *
13 */
14
15 /**************************************************************************
16 * Included Files
17 **************************************************************************/
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/leds.h>
22 #include <linux/gpio.h>
23 #include <linux/platform_device.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c/at24.h>
26 #include <linux/i2c/pcf857x.h>
27
28 #include <media/tvp514x.h>
29
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/clk.h>
34
35 #include <asm/mach-types.h>
36 #include <asm/mach/arch.h>
37
38 #include <mach/dm646x.h>
39 #include <mach/common.h>
40 #include <mach/serial.h>
41 #include <mach/i2c.h>
42 #include <mach/nand.h>
43 #include <mach/clock.h>
44 #include <mach/cdce949.h>
45 #include <mach/aemif.h>
46
47 #include "clock.h"
48
49 #define NAND_BLOCK_SIZE SZ_128K
50
51 /* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
52 * and U-Boot environment this avoids dependency on any particular combination
53 * of UBL, U-Boot or flashing tools etc.
54 */
55 static struct mtd_partition davinci_nand_partitions[] = {
56 {
57 /* UBL, U-Boot with environment */
58 .name = "bootloader",
59 .offset = MTDPART_OFS_APPEND,
60 .size = 16 * NAND_BLOCK_SIZE,
61 .mask_flags = MTD_WRITEABLE, /* force read-only */
62 }, {
63 .name = "kernel",
64 .offset = MTDPART_OFS_APPEND,
65 .size = SZ_4M,
66 .mask_flags = 0,
67 }, {
68 .name = "filesystem",
69 .offset = MTDPART_OFS_APPEND,
70 .size = MTDPART_SIZ_FULL,
71 .mask_flags = 0,
72 }
73 };
74
75 static struct davinci_aemif_timing dm6467tevm_nandflash_timing = {
76 .wsetup = 29,
77 .wstrobe = 24,
78 .whold = 14,
79 .rsetup = 19,
80 .rstrobe = 33,
81 .rhold = 0,
82 .ta = 29,
83 };
84
85 static struct davinci_nand_pdata davinci_nand_data = {
86 .mask_cle = 0x80000,
87 .mask_ale = 0x40000,
88 .parts = davinci_nand_partitions,
89 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
90 .ecc_mode = NAND_ECC_HW,
91 .options = 0,
92 };
93
94 static struct resource davinci_nand_resources[] = {
95 {
96 .start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
97 .end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
98 .flags = IORESOURCE_MEM,
99 }, {
100 .start = DM646X_ASYNC_EMIF_CONTROL_BASE,
101 .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
102 .flags = IORESOURCE_MEM,
103 },
104 };
105
106 static struct platform_device davinci_nand_device = {
107 .name = "davinci_nand",
108 .id = 0,
109
110 .num_resources = ARRAY_SIZE(davinci_nand_resources),
111 .resource = davinci_nand_resources,
112
113 .dev = {
114 .platform_data = &davinci_nand_data,
115 },
116 };
117
118 #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
119 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
120 #define HAS_ATA 1
121 #else
122 #define HAS_ATA 0
123 #endif
124
125 /* CPLD Register 0 bits to control ATA */
126 #define DM646X_EVM_ATA_RST BIT(0)
127 #define DM646X_EVM_ATA_PWD BIT(1)
128
129 /* CPLD Register 0 Client: used for I/O Control */
130 static int cpld_reg0_probe(struct i2c_client *client,
131 const struct i2c_device_id *id)
132 {
133 if (HAS_ATA) {
134 u8 data;
135 struct i2c_msg msg[2] = {
136 {
137 .addr = client->addr,
138 .flags = I2C_M_RD,
139 .len = 1,
140 .buf = &data,
141 },
142 {
143 .addr = client->addr,
144 .flags = 0,
145 .len = 1,
146 .buf = &data,
147 },
148 };
149
150 /* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */
151 i2c_transfer(client->adapter, msg, 1);
152 data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD);
153 i2c_transfer(client->adapter, msg + 1, 1);
154 }
155
156 return 0;
157 }
158
159 static const struct i2c_device_id cpld_reg_ids[] = {
160 { "cpld_reg0", 0, },
161 { },
162 };
163
164 static struct i2c_driver dm6467evm_cpld_driver = {
165 .driver.name = "cpld_reg0",
166 .id_table = cpld_reg_ids,
167 .probe = cpld_reg0_probe,
168 };
169
170 /* LEDS */
171
172 static struct gpio_led evm_leds[] = {
173 { .name = "DS1", .active_low = 1, },
174 { .name = "DS2", .active_low = 1, },
175 { .name = "DS3", .active_low = 1, },
176 { .name = "DS4", .active_low = 1, },
177 };
178
179 static const struct gpio_led_platform_data evm_led_data = {
180 .num_leds = ARRAY_SIZE(evm_leds),
181 .leds = evm_leds,
182 };
183
184 static struct platform_device *evm_led_dev;
185
186 static int evm_led_setup(struct i2c_client *client, int gpio,
187 unsigned int ngpio, void *c)
188 {
189 struct gpio_led *leds = evm_leds;
190 int status;
191
192 while (ngpio--) {
193 leds->gpio = gpio++;
194 leds++;
195 };
196
197 evm_led_dev = platform_device_alloc("leds-gpio", 0);
198 platform_device_add_data(evm_led_dev, &evm_led_data,
199 sizeof(evm_led_data));
200
201 evm_led_dev->dev.parent = &client->dev;
202 status = platform_device_add(evm_led_dev);
203 if (status < 0) {
204 platform_device_put(evm_led_dev);
205 evm_led_dev = NULL;
206 }
207 return status;
208 }
209
210 static int evm_led_teardown(struct i2c_client *client, int gpio,
211 unsigned ngpio, void *c)
212 {
213 if (evm_led_dev) {
214 platform_device_unregister(evm_led_dev);
215 evm_led_dev = NULL;
216 }
217 return 0;
218 }
219
220 static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL };
221
222 static int evm_sw_setup(struct i2c_client *client, int gpio,
223 unsigned ngpio, void *c)
224 {
225 int status;
226 int i;
227 char label[10];
228
229 for (i = 0; i < 4; ++i) {
230 snprintf(label, 10, "user_sw%d", i);
231 status = gpio_request(gpio, label);
232 if (status)
233 goto out_free;
234 evm_sw_gpio[i] = gpio++;
235
236 status = gpio_direction_input(evm_sw_gpio[i]);
237 if (status) {
238 gpio_free(evm_sw_gpio[i]);
239 evm_sw_gpio[i] = -EINVAL;
240 goto out_free;
241 }
242
243 status = gpio_export(evm_sw_gpio[i], 0);
244 if (status) {
245 gpio_free(evm_sw_gpio[i]);
246 evm_sw_gpio[i] = -EINVAL;
247 goto out_free;
248 }
249 }
250 return status;
251 out_free:
252 for (i = 0; i < 4; ++i) {
253 if (evm_sw_gpio[i] != -EINVAL) {
254 gpio_free(evm_sw_gpio[i]);
255 evm_sw_gpio[i] = -EINVAL;
256 }
257 }
258 return status;
259 }
260
261 static int evm_sw_teardown(struct i2c_client *client, int gpio,
262 unsigned ngpio, void *c)
263 {
264 int i;
265
266 for (i = 0; i < 4; ++i) {
267 if (evm_sw_gpio[i] != -EINVAL) {
268 gpio_unexport(evm_sw_gpio[i]);
269 gpio_free(evm_sw_gpio[i]);
270 evm_sw_gpio[i] = -EINVAL;
271 }
272 }
273 return 0;
274 }
275
276 static int evm_pcf_setup(struct i2c_client *client, int gpio,
277 unsigned int ngpio, void *c)
278 {
279 int status;
280
281 if (ngpio < 8)
282 return -EINVAL;
283
284 status = evm_sw_setup(client, gpio, 4, c);
285 if (status)
286 return status;
287
288 return evm_led_setup(client, gpio+4, 4, c);
289 }
290
291 static int evm_pcf_teardown(struct i2c_client *client, int gpio,
292 unsigned int ngpio, void *c)
293 {
294 BUG_ON(ngpio < 8);
295
296 evm_sw_teardown(client, gpio, 4, c);
297 evm_led_teardown(client, gpio+4, 4, c);
298
299 return 0;
300 }
301
302 static struct pcf857x_platform_data pcf_data = {
303 .gpio_base = DAVINCI_N_GPIO+1,
304 .setup = evm_pcf_setup,
305 .teardown = evm_pcf_teardown,
306 };
307
308 /* Most of this EEPROM is unused, but U-Boot uses some data:
309 * - 0x7f00, 6 bytes Ethernet Address
310 * - ... newer boards may have more
311 */
312
313 static struct at24_platform_data eeprom_info = {
314 .byte_len = (256*1024) / 8,
315 .page_size = 64,
316 .flags = AT24_FLAG_ADDR16,
317 .setup = davinci_get_mac_addr,
318 .context = (void *)0x7f00,
319 };
320
321 static u8 dm646x_iis_serializer_direction[] = {
322 TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE,
323 };
324
325 static u8 dm646x_dit_serializer_direction[] = {
326 TX_MODE,
327 };
328
329 static struct snd_platform_data dm646x_evm_snd_data[] = {
330 {
331 .tx_dma_offset = 0x400,
332 .rx_dma_offset = 0x400,
333 .op_mode = DAVINCI_MCASP_IIS_MODE,
334 .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction),
335 .tdm_slots = 2,
336 .serial_dir = dm646x_iis_serializer_direction,
337 .asp_chan_q = EVENTQ_0,
338 },
339 {
340 .tx_dma_offset = 0x400,
341 .rx_dma_offset = 0,
342 .op_mode = DAVINCI_MCASP_DIT_MODE,
343 .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction),
344 .tdm_slots = 32,
345 .serial_dir = dm646x_dit_serializer_direction,
346 .asp_chan_q = EVENTQ_0,
347 },
348 };
349
350 static struct i2c_client *cpld_client;
351
352 static int cpld_video_probe(struct i2c_client *client,
353 const struct i2c_device_id *id)
354 {
355 cpld_client = client;
356 return 0;
357 }
358
359 static int __devexit cpld_video_remove(struct i2c_client *client)
360 {
361 cpld_client = NULL;
362 return 0;
363 }
364
365 static const struct i2c_device_id cpld_video_id[] = {
366 { "cpld_video", 0 },
367 { }
368 };
369
370 static struct i2c_driver cpld_video_driver = {
371 .driver = {
372 .name = "cpld_video",
373 },
374 .probe = cpld_video_probe,
375 .remove = cpld_video_remove,
376 .id_table = cpld_video_id,
377 };
378
379 static void evm_init_cpld(void)
380 {
381 i2c_add_driver(&cpld_video_driver);
382 }
383
384 static struct i2c_board_info __initdata i2c_info[] = {
385 {
386 I2C_BOARD_INFO("24c256", 0x50),
387 .platform_data = &eeprom_info,
388 },
389 {
390 I2C_BOARD_INFO("pcf8574a", 0x38),
391 .platform_data = &pcf_data,
392 },
393 {
394 I2C_BOARD_INFO("cpld_reg0", 0x3a),
395 },
396 {
397 I2C_BOARD_INFO("tlv320aic33", 0x18),
398 },
399 {
400 I2C_BOARD_INFO("cpld_video", 0x3b),
401 },
402 {
403 I2C_BOARD_INFO("cdce949", 0x6c),
404 },
405 };
406
407 static struct davinci_i2c_platform_data i2c_pdata = {
408 .bus_freq = 100 /* kHz */,
409 .bus_delay = 0 /* usec */,
410 };
411
412 #define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
413 #define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
414 #define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
415 #define VCH2CLK_SYSCLK8 (BIT(9))
416 #define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
417 #define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
418 #define VCH3CLK_SYSCLK8 (BIT(13))
419 #define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
420
421 #define VIDCH2CLK (BIT(10))
422 #define VIDCH3CLK (BIT(11))
423 #define VIDCH1CLK (BIT(4))
424 #define TVP7002_INPUT (BIT(4))
425 #define TVP5147_INPUT (~BIT(4))
426 #define VPIF_INPUT_ONE_CHANNEL (BIT(5))
427 #define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
428 #define TVP5147_CH0 "tvp514x-0"
429 #define TVP5147_CH1 "tvp514x-1"
430
431 static void __iomem *vpif_vidclkctl_reg;
432 static void __iomem *vpif_vsclkdis_reg;
433 /* spin lock for updating above registers */
434 static spinlock_t vpif_reg_lock;
435
436 static int set_vpif_clock(int mux_mode, int hd)
437 {
438 unsigned long flags;
439 unsigned int value;
440 int val = 0;
441 int err = 0;
442
443 if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client)
444 return -ENXIO;
445
446 /* disable the clock */
447 spin_lock_irqsave(&vpif_reg_lock, flags);
448 value = __raw_readl(vpif_vsclkdis_reg);
449 value |= (VIDCH3CLK | VIDCH2CLK);
450 __raw_writel(value, vpif_vsclkdis_reg);
451 spin_unlock_irqrestore(&vpif_reg_lock, flags);
452
453 val = i2c_smbus_read_byte(cpld_client);
454 if (val < 0)
455 return val;
456
457 if (mux_mode == 1)
458 val &= ~0x40;
459 else
460 val |= 0x40;
461
462 err = i2c_smbus_write_byte(cpld_client, val);
463 if (err)
464 return err;
465
466 value = __raw_readl(vpif_vidclkctl_reg);
467 value &= ~(VCH2CLK_MASK);
468 value &= ~(VCH3CLK_MASK);
469
470 if (hd >= 1)
471 value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8);
472 else
473 value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
474
475 __raw_writel(value, vpif_vidclkctl_reg);
476
477 spin_lock_irqsave(&vpif_reg_lock, flags);
478 value = __raw_readl(vpif_vsclkdis_reg);
479 /* enable the clock */
480 value &= ~(VIDCH3CLK | VIDCH2CLK);
481 __raw_writel(value, vpif_vsclkdis_reg);
482 spin_unlock_irqrestore(&vpif_reg_lock, flags);
483
484 return 0;
485 }
486
487 static struct vpif_subdev_info dm646x_vpif_subdev[] = {
488 {
489 .name = "adv7343",
490 .board_info = {
491 I2C_BOARD_INFO("adv7343", 0x2a),
492 },
493 },
494 {
495 .name = "ths7303",
496 .board_info = {
497 I2C_BOARD_INFO("ths7303", 0x2c),
498 },
499 },
500 };
501
502 static const char *output[] = {
503 "Composite",
504 "Component",
505 "S-Video",
506 };
507
508 static struct vpif_display_config dm646x_vpif_display_config = {
509 .set_clock = set_vpif_clock,
510 .subdevinfo = dm646x_vpif_subdev,
511 .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
512 .output = output,
513 .output_count = ARRAY_SIZE(output),
514 .card_name = "DM646x EVM",
515 };
516
517 /**
518 * setup_vpif_input_path()
519 * @channel: channel id (0 - CH0, 1 - CH1)
520 * @sub_dev_name: ptr sub device name
521 *
522 * This will set vpif input to capture data from tvp514x or
523 * tvp7002.
524 */
525 static int setup_vpif_input_path(int channel, const char *sub_dev_name)
526 {
527 int err = 0;
528 int val;
529
530 /* for channel 1, we don't do anything */
531 if (channel != 0)
532 return 0;
533
534 if (!cpld_client)
535 return -ENXIO;
536
537 val = i2c_smbus_read_byte(cpld_client);
538 if (val < 0)
539 return val;
540
541 if (!strcmp(sub_dev_name, TVP5147_CH0) ||
542 !strcmp(sub_dev_name, TVP5147_CH1))
543 val &= TVP5147_INPUT;
544 else
545 val |= TVP7002_INPUT;
546
547 err = i2c_smbus_write_byte(cpld_client, val);
548 if (err)
549 return err;
550 return 0;
551 }
552
553 /**
554 * setup_vpif_input_channel_mode()
555 * @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel
556 *
557 * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147)
558 */
559 static int setup_vpif_input_channel_mode(int mux_mode)
560 {
561 unsigned long flags;
562 int err = 0;
563 int val;
564 u32 value;
565
566 if (!vpif_vsclkdis_reg || !cpld_client)
567 return -ENXIO;
568
569 val = i2c_smbus_read_byte(cpld_client);
570 if (val < 0)
571 return val;
572
573 spin_lock_irqsave(&vpif_reg_lock, flags);
574 value = __raw_readl(vpif_vsclkdis_reg);
575 if (mux_mode) {
576 val &= VPIF_INPUT_TWO_CHANNEL;
577 value |= VIDCH1CLK;
578 } else {
579 val |= VPIF_INPUT_ONE_CHANNEL;
580 value &= ~VIDCH1CLK;
581 }
582 __raw_writel(value, vpif_vsclkdis_reg);
583 spin_unlock_irqrestore(&vpif_reg_lock, flags);
584
585 err = i2c_smbus_write_byte(cpld_client, val);
586 if (err)
587 return err;
588
589 return 0;
590 }
591
592 static struct tvp514x_platform_data tvp5146_pdata = {
593 .clk_polarity = 0,
594 .hs_polarity = 1,
595 .vs_polarity = 1
596 };
597
598 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
599
600 static struct vpif_subdev_info vpif_capture_sdev_info[] = {
601 {
602 .name = TVP5147_CH0,
603 .board_info = {
604 I2C_BOARD_INFO("tvp5146", 0x5d),
605 .platform_data = &tvp5146_pdata,
606 },
607 .input = INPUT_CVBS_VI2B,
608 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
609 .can_route = 1,
610 .vpif_if = {
611 .if_type = VPIF_IF_BT656,
612 .hd_pol = 1,
613 .vd_pol = 1,
614 .fid_pol = 0,
615 },
616 },
617 {
618 .name = TVP5147_CH1,
619 .board_info = {
620 I2C_BOARD_INFO("tvp5146", 0x5c),
621 .platform_data = &tvp5146_pdata,
622 },
623 .input = INPUT_SVIDEO_VI2C_VI1C,
624 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
625 .can_route = 1,
626 .vpif_if = {
627 .if_type = VPIF_IF_BT656,
628 .hd_pol = 1,
629 .vd_pol = 1,
630 .fid_pol = 0,
631 },
632 },
633 };
634
635 static const struct vpif_input dm6467_ch0_inputs[] = {
636 {
637 .input = {
638 .index = 0,
639 .name = "Composite",
640 .type = V4L2_INPUT_TYPE_CAMERA,
641 .std = TVP514X_STD_ALL,
642 },
643 .subdev_name = TVP5147_CH0,
644 },
645 };
646
647 static const struct vpif_input dm6467_ch1_inputs[] = {
648 {
649 .input = {
650 .index = 0,
651 .name = "S-Video",
652 .type = V4L2_INPUT_TYPE_CAMERA,
653 .std = TVP514X_STD_ALL,
654 },
655 .subdev_name = TVP5147_CH1,
656 },
657 };
658
659 static struct vpif_capture_config dm646x_vpif_capture_cfg = {
660 .setup_input_path = setup_vpif_input_path,
661 .setup_input_channel_mode = setup_vpif_input_channel_mode,
662 .subdev_info = vpif_capture_sdev_info,
663 .subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
664 .chan_config[0] = {
665 .inputs = dm6467_ch0_inputs,
666 .input_count = ARRAY_SIZE(dm6467_ch0_inputs),
667 },
668 .chan_config[1] = {
669 .inputs = dm6467_ch1_inputs,
670 .input_count = ARRAY_SIZE(dm6467_ch1_inputs),
671 },
672 };
673
674 static void __init evm_init_video(void)
675 {
676 vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4);
677 vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4);
678 if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) {
679 pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n");
680 return;
681 }
682 spin_lock_init(&vpif_reg_lock);
683
684 dm646x_setup_vpif(&dm646x_vpif_display_config,
685 &dm646x_vpif_capture_cfg);
686 }
687
688 static void __init evm_init_i2c(void)
689 {
690 davinci_init_i2c(&i2c_pdata);
691 i2c_add_driver(&dm6467evm_cpld_driver);
692 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
693 evm_init_cpld();
694 evm_init_video();
695 }
696
697 #define CDCE949_XIN_RATE 27000000
698
699 /* CDCE949 support - "lpsc" field is overridden to work as clock number */
700 static struct clk cdce_clk_in = {
701 .name = "cdce_xin",
702 .rate = CDCE949_XIN_RATE,
703 };
704
705 static struct clk_lookup cdce_clks[] = {
706 CLK(NULL, "xin", &cdce_clk_in),
707 CLK(NULL, NULL, NULL),
708 };
709
710 static void __init cdce_clk_init(void)
711 {
712 struct clk_lookup *c;
713 struct clk *clk;
714
715 for (c = cdce_clks; c->clk; c++) {
716 clk = c->clk;
717 clkdev_add(c);
718 clk_register(clk);
719 }
720 }
721
722 static void __init davinci_map_io(void)
723 {
724 dm646x_init();
725 cdce_clk_init();
726 }
727
728 static struct davinci_uart_config uart_config __initdata = {
729 .enabled_uarts = (1 << 0),
730 };
731
732 #define DM646X_EVM_PHY_ID "0:01"
733 /*
734 * The following EDMA channels/slots are not being used by drivers (for
735 * example: Timer, GPIO, UART events etc) on dm646x, hence they are being
736 * reserved for codecs on the DSP side.
737 */
738 static const s16 dm646x_dma_rsv_chans[][2] = {
739 /* (offset, number) */
740 { 0, 4},
741 {13, 3},
742 {24, 4},
743 {30, 2},
744 {54, 3},
745 {-1, -1}
746 };
747
748 static const s16 dm646x_dma_rsv_slots[][2] = {
749 /* (offset, number) */
750 { 0, 4},
751 {13, 3},
752 {24, 4},
753 {30, 2},
754 {54, 3},
755 {128, 384},
756 {-1, -1}
757 };
758
759 static struct edma_rsv_info dm646x_edma_rsv[] = {
760 {
761 .rsv_chans = dm646x_dma_rsv_chans,
762 .rsv_slots = dm646x_dma_rsv_slots,
763 },
764 };
765
766 static __init void evm_init(void)
767 {
768 struct davinci_soc_info *soc_info = &davinci_soc_info;
769
770 evm_init_i2c();
771 davinci_serial_init(&uart_config);
772 dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
773 dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
774
775 if (machine_is_davinci_dm6467tevm())
776 davinci_nand_data.timing = &dm6467tevm_nandflash_timing;
777
778 platform_device_register(&davinci_nand_device);
779
780 dm646x_init_edma(dm646x_edma_rsv);
781
782 if (HAS_ATA)
783 davinci_init_ide();
784
785 soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
786 }
787
788 #define DM646X_EVM_REF_FREQ 27000000
789 #define DM6467T_EVM_REF_FREQ 33000000
790
791 void __init dm646x_board_setup_refclk(struct clk *clk)
792 {
793 if (machine_is_davinci_dm6467tevm())
794 clk->rate = DM6467T_EVM_REF_FREQ;
795 else
796 clk->rate = DM646X_EVM_REF_FREQ;
797 }
798
799 MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
800 .boot_params = (0x80000100),
801 .map_io = davinci_map_io,
802 .init_irq = davinci_irq_init,
803 .timer = &davinci_timer,
804 .init_machine = evm_init,
805 .dma_zone_size = SZ_128M,
806 MACHINE_END
807
808 MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
809 .boot_params = (0x80000100),
810 .map_io = davinci_map_io,
811 .init_irq = davinci_irq_init,
812 .timer = &davinci_timer,
813 .init_machine = evm_init,
814 .dma_zone_size = SZ_128M,
815 MACHINE_END
816
Linux kernel - Deliverables
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