2 * Critical Link MityOMAP-L138 SoM
4 * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of
8 * any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/console.h>
14 #include <linux/platform_device.h>
15 #include <linux/mtd/partitions.h>
17 #include <asm/mach-types.h>
18 #include <asm/mach/arch.h>
19 #include <mach/common.h>
20 #include <mach/cp_intc.h>
21 #include <mach/da8xx.h>
22 #include <mach/nand.h>
25 #define MITYOMAPL138_PHY_MASK 0x08 /* hardcoded for now */
26 #define MITYOMAPL138_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
29 * MityDSP-L138 includes a 256 MByte large-page NAND flash
32 struct mtd_partition mityomapl138_nandflash_partition
[] = {
37 .mask_flags
= 0, /* MTD_WRITEABLE, */
41 .offset
= MTDPART_OFS_APPEND
,
42 .size
= MTDPART_SIZ_FULL
,
47 static struct davinci_nand_pdata mityomapl138_nandflash_data
= {
48 .parts
= mityomapl138_nandflash_partition
,
49 .nr_parts
= ARRAY_SIZE(mityomapl138_nandflash_partition
),
50 .ecc_mode
= NAND_ECC_HW
,
51 .options
= NAND_USE_FLASH_BBT
| NAND_BUSWIDTH_16
,
52 .ecc_bits
= 1, /* 4 bit mode is not supported with 16 bit NAND */
55 static struct resource mityomapl138_nandflash_resource
[] = {
57 .start
= DA8XX_AEMIF_CS3_BASE
,
58 .end
= DA8XX_AEMIF_CS3_BASE
+ SZ_512K
+ 2 * SZ_1K
- 1,
59 .flags
= IORESOURCE_MEM
,
62 .start
= DA8XX_AEMIF_CTL_BASE
,
63 .end
= DA8XX_AEMIF_CTL_BASE
+ SZ_32K
- 1,
64 .flags
= IORESOURCE_MEM
,
68 static struct platform_device mityomapl138_nandflash_device
= {
69 .name
= "davinci_nand",
72 .platform_data
= &mityomapl138_nandflash_data
,
74 .num_resources
= ARRAY_SIZE(mityomapl138_nandflash_resource
),
75 .resource
= mityomapl138_nandflash_resource
,
78 static struct platform_device
*mityomapl138_devices
[] __initdata
= {
79 &mityomapl138_nandflash_device
,
82 static void __init
mityomapl138_setup_nand(void)
84 platform_add_devices(mityomapl138_devices
,
85 ARRAY_SIZE(mityomapl138_devices
));
88 static struct davinci_uart_config mityomapl138_uart_config __initdata
= {
92 static const short mityomap_mii_pins
[] = {
93 DA850_MII_TXEN
, DA850_MII_TXCLK
, DA850_MII_COL
, DA850_MII_TXD_3
,
94 DA850_MII_TXD_2
, DA850_MII_TXD_1
, DA850_MII_TXD_0
, DA850_MII_RXER
,
95 DA850_MII_CRS
, DA850_MII_RXCLK
, DA850_MII_RXDV
, DA850_MII_RXD_3
,
96 DA850_MII_RXD_2
, DA850_MII_RXD_1
, DA850_MII_RXD_0
, DA850_MDIO_CLK
,
101 static const short mityomap_rmii_pins
[] = {
102 DA850_RMII_TXD_0
, DA850_RMII_TXD_1
, DA850_RMII_TXEN
,
103 DA850_RMII_CRS_DV
, DA850_RMII_RXD_0
, DA850_RMII_RXD_1
,
104 DA850_RMII_RXER
, DA850_RMII_MHZ_50_CLK
, DA850_MDIO_CLK
,
109 static void __init
mityomapl138_config_emac(void)
111 void __iomem
*cfg_chip3_base
;
114 struct davinci_soc_info
*soc_info
= &davinci_soc_info
;
116 soc_info
->emac_pdata
->rmii_en
= 0; /* hardcoded for now */
118 cfg_chip3_base
= DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG
);
119 val
= __raw_readl(cfg_chip3_base
);
121 if (soc_info
->emac_pdata
->rmii_en
) {
123 ret
= davinci_cfg_reg_list(mityomap_rmii_pins
);
124 pr_info("RMII PHY configured\n");
127 ret
= davinci_cfg_reg_list(mityomap_mii_pins
);
128 pr_info("MII PHY configured\n");
132 pr_warning("mii/rmii mux setup failed: %d\n", ret
);
136 /* configure the CFGCHIP3 register for RMII or MII */
137 __raw_writel(val
, cfg_chip3_base
);
139 soc_info
->emac_pdata
->phy_mask
= MITYOMAPL138_PHY_MASK
;
140 pr_debug("setting phy_mask to %x\n", soc_info
->emac_pdata
->phy_mask
);
141 soc_info
->emac_pdata
->mdio_max_freq
= MITYOMAPL138_MDIO_FREQUENCY
;
143 ret
= da8xx_register_emac();
145 pr_warning("emac registration failed: %d\n", ret
);
148 static struct davinci_pm_config da850_pm_pdata
= {
152 static struct platform_device da850_pm_device
= {
153 .name
= "pm-davinci",
155 .platform_data
= &da850_pm_pdata
,
160 static void __init
mityomapl138_init(void)
164 /* for now, no special EDMA channels are reserved */
165 ret
= da850_register_edma(NULL
);
167 pr_warning("edma registration failed: %d\n", ret
);
169 ret
= da8xx_register_watchdog();
171 pr_warning("watchdog registration failed: %d\n", ret
);
173 davinci_serial_init(&mityomapl138_uart_config
);
175 mityomapl138_setup_nand();
177 mityomapl138_config_emac();
179 ret
= da8xx_register_rtc();
181 pr_warning("rtc setup failed: %d\n", ret
);
183 ret
= da850_register_cpufreq("pll0_sysclk3");
185 pr_warning("cpufreq registration failed: %d\n", ret
);
187 ret
= da8xx_register_cpuidle();
189 pr_warning("cpuidle registration failed: %d\n", ret
);
191 ret
= da850_register_pm(&da850_pm_device
);
193 pr_warning("da850_evm_init: suspend registration failed: %d\n",
197 #ifdef CONFIG_SERIAL_8250_CONSOLE
198 static int __init
mityomapl138_console_init(void)
200 if (!machine_is_mityomapl138())
203 return add_preferred_console("ttyS", 1, "115200");
205 console_initcall(mityomapl138_console_init
);
208 static void __init
mityomapl138_map_io(void)
213 MACHINE_START(MITYOMAPL138
, "MityDSP-L138/MityARM-1808")
215 .io_pg_offst
= (__IO_ADDRESS(IO_PHYS
) >> 18) & 0xfffc,
216 .boot_params
= (DA8XX_DDR_BASE
+ 0x100),
217 .map_io
= mityomapl138_map_io
,
218 .init_irq
= cp_intc_init
,
219 .timer
= &davinci_timer
,
220 .init_machine
= mityomapl138_init
,