2 * TI DA850/OMAP-L138 chip specific setup
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
14 #include <linux/clkdev.h>
15 #include <linux/gpio.h>
16 #include <linux/init.h>
17 #include <linux/clk.h>
18 #include <linux/platform_device.h>
19 #include <linux/cpufreq.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/platform_data/gpio-davinci.h>
23 #include <asm/mach/map.h>
26 #include <mach/irqs.h>
27 #include <mach/cputype.h>
28 #include <mach/common.h>
29 #include <mach/time.h>
30 #include <mach/da8xx.h>
31 #include <mach/cpufreq.h>
37 #define DA850_PLL1_BASE 0x01e1a000
38 #define DA850_TIMER64P2_BASE 0x01f0c000
39 #define DA850_TIMER64P3_BASE 0x01f0d000
41 #define DA850_REF_FREQ 24000000
43 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
44 #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
45 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
47 static int da850_set_armrate(struct clk
*clk
, unsigned long rate
);
48 static int da850_round_armrate(struct clk
*clk
, unsigned long rate
);
49 static int da850_set_pll0rate(struct clk
*clk
, unsigned long armrate
);
51 static struct pll_data pll0_data
= {
53 .phys_base
= DA8XX_PLL0_BASE
,
54 .flags
= PLL_HAS_PREDIV
| PLL_HAS_POSTDIV
,
57 static struct clk ref_clk
= {
59 .rate
= DA850_REF_FREQ
,
60 .set_rate
= davinci_simple_set_rate
,
63 static struct clk pll0_clk
= {
66 .pll_data
= &pll0_data
,
68 .set_rate
= da850_set_pll0rate
,
71 static struct clk pll0_aux_clk
= {
72 .name
= "pll0_aux_clk",
74 .flags
= CLK_PLL
| PRE_PLL
,
77 static struct clk pll0_sysclk1
= {
78 .name
= "pll0_sysclk1",
84 static struct clk pll0_sysclk2
= {
85 .name
= "pll0_sysclk2",
91 static struct clk pll0_sysclk3
= {
92 .name
= "pll0_sysclk3",
96 .set_rate
= davinci_set_sysclk_rate
,
100 static struct clk pll0_sysclk4
= {
101 .name
= "pll0_sysclk4",
107 static struct clk pll0_sysclk5
= {
108 .name
= "pll0_sysclk5",
114 static struct clk pll0_sysclk6
= {
115 .name
= "pll0_sysclk6",
121 static struct clk pll0_sysclk7
= {
122 .name
= "pll0_sysclk7",
128 static struct pll_data pll1_data
= {
130 .phys_base
= DA850_PLL1_BASE
,
131 .flags
= PLL_HAS_POSTDIV
,
134 static struct clk pll1_clk
= {
137 .pll_data
= &pll1_data
,
141 static struct clk pll1_aux_clk
= {
142 .name
= "pll1_aux_clk",
144 .flags
= CLK_PLL
| PRE_PLL
,
147 static struct clk pll1_sysclk2
= {
148 .name
= "pll1_sysclk2",
154 static struct clk pll1_sysclk3
= {
155 .name
= "pll1_sysclk3",
161 static int da850_async3_set_parent(struct clk
*clk
, struct clk
*parent
)
165 val
= readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG
));
167 if (parent
== &pll0_sysclk2
) {
168 val
&= ~CFGCHIP3_ASYNC3_CLKSRC
;
169 } else if (parent
== &pll1_sysclk2
) {
170 val
|= CFGCHIP3_ASYNC3_CLKSRC
;
172 pr_err("Bad parent on async3 clock mux\n");
176 writel(val
, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG
));
181 static struct clk async3_clk
= {
183 .parent
= &pll1_sysclk2
,
184 .set_parent
= da850_async3_set_parent
,
187 static struct clk i2c0_clk
= {
189 .parent
= &pll0_aux_clk
,
192 static struct clk timerp64_0_clk
= {
194 .parent
= &pll0_aux_clk
,
197 static struct clk timerp64_1_clk
= {
199 .parent
= &pll0_aux_clk
,
202 static struct clk arm_rom_clk
= {
204 .parent
= &pll0_sysclk2
,
205 .lpsc
= DA8XX_LPSC0_ARM_RAM_ROM
,
206 .flags
= ALWAYS_ENABLED
,
209 static struct clk tpcc0_clk
= {
211 .parent
= &pll0_sysclk2
,
212 .lpsc
= DA8XX_LPSC0_TPCC
,
213 .flags
= ALWAYS_ENABLED
| CLK_PSC
,
216 static struct clk tptc0_clk
= {
218 .parent
= &pll0_sysclk2
,
219 .lpsc
= DA8XX_LPSC0_TPTC0
,
220 .flags
= ALWAYS_ENABLED
,
223 static struct clk tptc1_clk
= {
225 .parent
= &pll0_sysclk2
,
226 .lpsc
= DA8XX_LPSC0_TPTC1
,
227 .flags
= ALWAYS_ENABLED
,
230 static struct clk tpcc1_clk
= {
232 .parent
= &pll0_sysclk2
,
233 .lpsc
= DA850_LPSC1_TPCC1
,
235 .flags
= CLK_PSC
| ALWAYS_ENABLED
,
238 static struct clk tptc2_clk
= {
240 .parent
= &pll0_sysclk2
,
241 .lpsc
= DA850_LPSC1_TPTC2
,
243 .flags
= ALWAYS_ENABLED
,
246 static struct clk pruss_clk
= {
248 .parent
= &pll0_sysclk2
,
249 .lpsc
= DA8XX_LPSC0_PRUSS
,
252 static struct clk uart0_clk
= {
254 .parent
= &pll0_sysclk2
,
255 .lpsc
= DA8XX_LPSC0_UART0
,
258 static struct clk uart1_clk
= {
260 .parent
= &async3_clk
,
261 .lpsc
= DA8XX_LPSC1_UART1
,
265 static struct clk uart2_clk
= {
267 .parent
= &async3_clk
,
268 .lpsc
= DA8XX_LPSC1_UART2
,
272 static struct clk aintc_clk
= {
274 .parent
= &pll0_sysclk4
,
275 .lpsc
= DA8XX_LPSC0_AINTC
,
276 .flags
= ALWAYS_ENABLED
,
279 static struct clk gpio_clk
= {
281 .parent
= &pll0_sysclk4
,
282 .lpsc
= DA8XX_LPSC1_GPIO
,
286 static struct clk i2c1_clk
= {
288 .parent
= &pll0_sysclk4
,
289 .lpsc
= DA8XX_LPSC1_I2C
,
293 static struct clk emif3_clk
= {
295 .parent
= &pll0_sysclk5
,
296 .lpsc
= DA8XX_LPSC1_EMIF3C
,
298 .flags
= ALWAYS_ENABLED
,
301 static struct clk arm_clk
= {
303 .parent
= &pll0_sysclk6
,
304 .lpsc
= DA8XX_LPSC0_ARM
,
305 .flags
= ALWAYS_ENABLED
,
306 .set_rate
= da850_set_armrate
,
307 .round_rate
= da850_round_armrate
,
310 static struct clk rmii_clk
= {
312 .parent
= &pll0_sysclk7
,
315 static struct clk emac_clk
= {
317 .parent
= &pll0_sysclk4
,
318 .lpsc
= DA8XX_LPSC1_CPGMAC
,
322 static struct clk mcasp_clk
= {
324 .parent
= &async3_clk
,
325 .lpsc
= DA8XX_LPSC1_McASP0
,
329 static struct clk lcdc_clk
= {
331 .parent
= &pll0_sysclk2
,
332 .lpsc
= DA8XX_LPSC1_LCDC
,
336 static struct clk mmcsd0_clk
= {
338 .parent
= &pll0_sysclk2
,
339 .lpsc
= DA8XX_LPSC0_MMC_SD
,
342 static struct clk mmcsd1_clk
= {
344 .parent
= &pll0_sysclk2
,
345 .lpsc
= DA850_LPSC1_MMC_SD1
,
349 static struct clk aemif_clk
= {
351 .parent
= &pll0_sysclk3
,
352 .lpsc
= DA8XX_LPSC0_EMIF25
,
353 .flags
= ALWAYS_ENABLED
,
356 static struct clk usb11_clk
= {
358 .parent
= &pll0_sysclk4
,
359 .lpsc
= DA8XX_LPSC1_USB11
,
363 static struct clk usb20_clk
= {
365 .parent
= &pll0_sysclk2
,
366 .lpsc
= DA8XX_LPSC1_USB20
,
370 static struct clk spi0_clk
= {
372 .parent
= &pll0_sysclk2
,
373 .lpsc
= DA8XX_LPSC0_SPI0
,
376 static struct clk spi1_clk
= {
378 .parent
= &async3_clk
,
379 .lpsc
= DA8XX_LPSC1_SPI1
,
383 static struct clk vpif_clk
= {
385 .parent
= &pll0_sysclk2
,
386 .lpsc
= DA850_LPSC1_VPIF
,
390 static struct clk sata_clk
= {
392 .parent
= &pll0_sysclk2
,
393 .lpsc
= DA850_LPSC1_SATA
,
398 static struct clk dsp_clk
= {
400 .parent
= &pll0_sysclk1
,
401 .domain
= DAVINCI_GPSC_DSPDOMAIN
,
402 .lpsc
= DA8XX_LPSC0_GEM
,
403 .flags
= PSC_LRST
| PSC_FORCE
,
406 static struct clk ehrpwm_clk
= {
408 .parent
= &async3_clk
,
409 .lpsc
= DA8XX_LPSC1_PWM
,
413 #define DA8XX_EHRPWM_TBCLKSYNC BIT(12)
415 static void ehrpwm_tblck_enable(struct clk
*clk
)
419 val
= readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG
));
420 val
|= DA8XX_EHRPWM_TBCLKSYNC
;
421 writel(val
, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG
));
424 static void ehrpwm_tblck_disable(struct clk
*clk
)
428 val
= readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG
));
429 val
&= ~DA8XX_EHRPWM_TBCLKSYNC
;
430 writel(val
, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG
));
433 static struct clk ehrpwm_tbclk
= {
434 .name
= "ehrpwm_tbclk",
435 .parent
= &ehrpwm_clk
,
436 .clk_enable
= ehrpwm_tblck_enable
,
437 .clk_disable
= ehrpwm_tblck_disable
,
440 static struct clk ecap_clk
= {
442 .parent
= &async3_clk
,
443 .lpsc
= DA8XX_LPSC1_ECAP
,
447 static struct clk_lookup da850_clks
[] = {
448 CLK(NULL
, "ref", &ref_clk
),
449 CLK(NULL
, "pll0", &pll0_clk
),
450 CLK(NULL
, "pll0_aux", &pll0_aux_clk
),
451 CLK(NULL
, "pll0_sysclk1", &pll0_sysclk1
),
452 CLK(NULL
, "pll0_sysclk2", &pll0_sysclk2
),
453 CLK(NULL
, "pll0_sysclk3", &pll0_sysclk3
),
454 CLK(NULL
, "pll0_sysclk4", &pll0_sysclk4
),
455 CLK(NULL
, "pll0_sysclk5", &pll0_sysclk5
),
456 CLK(NULL
, "pll0_sysclk6", &pll0_sysclk6
),
457 CLK(NULL
, "pll0_sysclk7", &pll0_sysclk7
),
458 CLK(NULL
, "pll1", &pll1_clk
),
459 CLK(NULL
, "pll1_aux", &pll1_aux_clk
),
460 CLK(NULL
, "pll1_sysclk2", &pll1_sysclk2
),
461 CLK(NULL
, "pll1_sysclk3", &pll1_sysclk3
),
462 CLK(NULL
, "async3", &async3_clk
),
463 CLK("i2c_davinci.1", NULL
, &i2c0_clk
),
464 CLK(NULL
, "timer0", &timerp64_0_clk
),
465 CLK("davinci-wdt", NULL
, &timerp64_1_clk
),
466 CLK(NULL
, "arm_rom", &arm_rom_clk
),
467 CLK(NULL
, "tpcc0", &tpcc0_clk
),
468 CLK(NULL
, "tptc0", &tptc0_clk
),
469 CLK(NULL
, "tptc1", &tptc1_clk
),
470 CLK(NULL
, "tpcc1", &tpcc1_clk
),
471 CLK(NULL
, "tptc2", &tptc2_clk
),
472 CLK("pruss_uio", "pruss", &pruss_clk
),
473 CLK("serial8250.0", NULL
, &uart0_clk
),
474 CLK("serial8250.1", NULL
, &uart1_clk
),
475 CLK("serial8250.2", NULL
, &uart2_clk
),
476 CLK(NULL
, "aintc", &aintc_clk
),
477 CLK(NULL
, "gpio", &gpio_clk
),
478 CLK("i2c_davinci.2", NULL
, &i2c1_clk
),
479 CLK(NULL
, "emif3", &emif3_clk
),
480 CLK(NULL
, "arm", &arm_clk
),
481 CLK(NULL
, "rmii", &rmii_clk
),
482 CLK("davinci_emac.1", NULL
, &emac_clk
),
483 CLK("davinci_mdio.0", "fck", &emac_clk
),
484 CLK("davinci-mcasp.0", NULL
, &mcasp_clk
),
485 CLK("da8xx_lcdc.0", "fck", &lcdc_clk
),
486 CLK("da830-mmc.0", NULL
, &mmcsd0_clk
),
487 CLK("da830-mmc.1", NULL
, &mmcsd1_clk
),
488 CLK(NULL
, "aemif", &aemif_clk
),
489 CLK(NULL
, "usb11", &usb11_clk
),
490 CLK(NULL
, "usb20", &usb20_clk
),
491 CLK("spi_davinci.0", NULL
, &spi0_clk
),
492 CLK("spi_davinci.1", NULL
, &spi1_clk
),
493 CLK("vpif", NULL
, &vpif_clk
),
494 CLK("ahci_da850", NULL
, &sata_clk
),
495 CLK("davinci-rproc.0", NULL
, &dsp_clk
),
496 CLK("ehrpwm", "fck", &ehrpwm_clk
),
497 CLK("ehrpwm", "tbclk", &ehrpwm_tbclk
),
498 CLK("ecap", "fck", &ecap_clk
),
499 CLK(NULL
, NULL
, NULL
),
503 * Device specific mux setup
505 * soc description mux mode mode mux dbg
506 * reg offset mask mode
508 static const struct mux_config da850_pins
[] = {
509 #ifdef CONFIG_DAVINCI_MUX
511 MUX_CFG(DA850
, NUART0_CTS
, 3, 24, 15, 2, false)
512 MUX_CFG(DA850
, NUART0_RTS
, 3, 28, 15, 2, false)
513 MUX_CFG(DA850
, UART0_RXD
, 3, 16, 15, 2, false)
514 MUX_CFG(DA850
, UART0_TXD
, 3, 20, 15, 2, false)
516 MUX_CFG(DA850
, UART1_RXD
, 4, 24, 15, 2, false)
517 MUX_CFG(DA850
, UART1_TXD
, 4, 28, 15, 2, false)
519 MUX_CFG(DA850
, UART2_RXD
, 4, 16, 15, 2, false)
520 MUX_CFG(DA850
, UART2_TXD
, 4, 20, 15, 2, false)
522 MUX_CFG(DA850
, I2C1_SCL
, 4, 16, 15, 4, false)
523 MUX_CFG(DA850
, I2C1_SDA
, 4, 20, 15, 4, false)
525 MUX_CFG(DA850
, I2C0_SDA
, 4, 12, 15, 2, false)
526 MUX_CFG(DA850
, I2C0_SCL
, 4, 8, 15, 2, false)
528 MUX_CFG(DA850
, MII_TXEN
, 2, 4, 15, 8, false)
529 MUX_CFG(DA850
, MII_TXCLK
, 2, 8, 15, 8, false)
530 MUX_CFG(DA850
, MII_COL
, 2, 12, 15, 8, false)
531 MUX_CFG(DA850
, MII_TXD_3
, 2, 16, 15, 8, false)
532 MUX_CFG(DA850
, MII_TXD_2
, 2, 20, 15, 8, false)
533 MUX_CFG(DA850
, MII_TXD_1
, 2, 24, 15, 8, false)
534 MUX_CFG(DA850
, MII_TXD_0
, 2, 28, 15, 8, false)
535 MUX_CFG(DA850
, MII_RXCLK
, 3, 0, 15, 8, false)
536 MUX_CFG(DA850
, MII_RXDV
, 3, 4, 15, 8, false)
537 MUX_CFG(DA850
, MII_RXER
, 3, 8, 15, 8, false)
538 MUX_CFG(DA850
, MII_CRS
, 3, 12, 15, 8, false)
539 MUX_CFG(DA850
, MII_RXD_3
, 3, 16, 15, 8, false)
540 MUX_CFG(DA850
, MII_RXD_2
, 3, 20, 15, 8, false)
541 MUX_CFG(DA850
, MII_RXD_1
, 3, 24, 15, 8, false)
542 MUX_CFG(DA850
, MII_RXD_0
, 3, 28, 15, 8, false)
543 MUX_CFG(DA850
, MDIO_CLK
, 4, 0, 15, 8, false)
544 MUX_CFG(DA850
, MDIO_D
, 4, 4, 15, 8, false)
545 MUX_CFG(DA850
, RMII_TXD_0
, 14, 12, 15, 8, false)
546 MUX_CFG(DA850
, RMII_TXD_1
, 14, 8, 15, 8, false)
547 MUX_CFG(DA850
, RMII_TXEN
, 14, 16, 15, 8, false)
548 MUX_CFG(DA850
, RMII_CRS_DV
, 15, 4, 15, 8, false)
549 MUX_CFG(DA850
, RMII_RXD_0
, 14, 24, 15, 8, false)
550 MUX_CFG(DA850
, RMII_RXD_1
, 14, 20, 15, 8, false)
551 MUX_CFG(DA850
, RMII_RXER
, 14, 28, 15, 8, false)
552 MUX_CFG(DA850
, RMII_MHZ_50_CLK
, 15, 0, 15, 0, false)
554 MUX_CFG(DA850
, ACLKR
, 0, 0, 15, 1, false)
555 MUX_CFG(DA850
, ACLKX
, 0, 4, 15, 1, false)
556 MUX_CFG(DA850
, AFSR
, 0, 8, 15, 1, false)
557 MUX_CFG(DA850
, AFSX
, 0, 12, 15, 1, false)
558 MUX_CFG(DA850
, AHCLKR
, 0, 16, 15, 1, false)
559 MUX_CFG(DA850
, AHCLKX
, 0, 20, 15, 1, false)
560 MUX_CFG(DA850
, AMUTE
, 0, 24, 15, 1, false)
561 MUX_CFG(DA850
, AXR_15
, 1, 0, 15, 1, false)
562 MUX_CFG(DA850
, AXR_14
, 1, 4, 15, 1, false)
563 MUX_CFG(DA850
, AXR_13
, 1, 8, 15, 1, false)
564 MUX_CFG(DA850
, AXR_12
, 1, 12, 15, 1, false)
565 MUX_CFG(DA850
, AXR_11
, 1, 16, 15, 1, false)
566 MUX_CFG(DA850
, AXR_10
, 1, 20, 15, 1, false)
567 MUX_CFG(DA850
, AXR_9
, 1, 24, 15, 1, false)
568 MUX_CFG(DA850
, AXR_8
, 1, 28, 15, 1, false)
569 MUX_CFG(DA850
, AXR_7
, 2, 0, 15, 1, false)
570 MUX_CFG(DA850
, AXR_6
, 2, 4, 15, 1, false)
571 MUX_CFG(DA850
, AXR_5
, 2, 8, 15, 1, false)
572 MUX_CFG(DA850
, AXR_4
, 2, 12, 15, 1, false)
573 MUX_CFG(DA850
, AXR_3
, 2, 16, 15, 1, false)
574 MUX_CFG(DA850
, AXR_2
, 2, 20, 15, 1, false)
575 MUX_CFG(DA850
, AXR_1
, 2, 24, 15, 1, false)
576 MUX_CFG(DA850
, AXR_0
, 2, 28, 15, 1, false)
578 MUX_CFG(DA850
, LCD_D_7
, 16, 8, 15, 2, false)
579 MUX_CFG(DA850
, LCD_D_6
, 16, 12, 15, 2, false)
580 MUX_CFG(DA850
, LCD_D_5
, 16, 16, 15, 2, false)
581 MUX_CFG(DA850
, LCD_D_4
, 16, 20, 15, 2, false)
582 MUX_CFG(DA850
, LCD_D_3
, 16, 24, 15, 2, false)
583 MUX_CFG(DA850
, LCD_D_2
, 16, 28, 15, 2, false)
584 MUX_CFG(DA850
, LCD_D_1
, 17, 0, 15, 2, false)
585 MUX_CFG(DA850
, LCD_D_0
, 17, 4, 15, 2, false)
586 MUX_CFG(DA850
, LCD_D_15
, 17, 8, 15, 2, false)
587 MUX_CFG(DA850
, LCD_D_14
, 17, 12, 15, 2, false)
588 MUX_CFG(DA850
, LCD_D_13
, 17, 16, 15, 2, false)
589 MUX_CFG(DA850
, LCD_D_12
, 17, 20, 15, 2, false)
590 MUX_CFG(DA850
, LCD_D_11
, 17, 24, 15, 2, false)
591 MUX_CFG(DA850
, LCD_D_10
, 17, 28, 15, 2, false)
592 MUX_CFG(DA850
, LCD_D_9
, 18, 0, 15, 2, false)
593 MUX_CFG(DA850
, LCD_D_8
, 18, 4, 15, 2, false)
594 MUX_CFG(DA850
, LCD_PCLK
, 18, 24, 15, 2, false)
595 MUX_CFG(DA850
, LCD_HSYNC
, 19, 0, 15, 2, false)
596 MUX_CFG(DA850
, LCD_VSYNC
, 19, 4, 15, 2, false)
597 MUX_CFG(DA850
, NLCD_AC_ENB_CS
, 19, 24, 15, 2, false)
598 /* MMC/SD0 function */
599 MUX_CFG(DA850
, MMCSD0_DAT_0
, 10, 8, 15, 2, false)
600 MUX_CFG(DA850
, MMCSD0_DAT_1
, 10, 12, 15, 2, false)
601 MUX_CFG(DA850
, MMCSD0_DAT_2
, 10, 16, 15, 2, false)
602 MUX_CFG(DA850
, MMCSD0_DAT_3
, 10, 20, 15, 2, false)
603 MUX_CFG(DA850
, MMCSD0_CLK
, 10, 0, 15, 2, false)
604 MUX_CFG(DA850
, MMCSD0_CMD
, 10, 4, 15, 2, false)
605 /* MMC/SD1 function */
606 MUX_CFG(DA850
, MMCSD1_DAT_0
, 18, 8, 15, 2, false)
607 MUX_CFG(DA850
, MMCSD1_DAT_1
, 19, 16, 15, 2, false)
608 MUX_CFG(DA850
, MMCSD1_DAT_2
, 19, 12, 15, 2, false)
609 MUX_CFG(DA850
, MMCSD1_DAT_3
, 19, 8, 15, 2, false)
610 MUX_CFG(DA850
, MMCSD1_CLK
, 18, 12, 15, 2, false)
611 MUX_CFG(DA850
, MMCSD1_CMD
, 18, 16, 15, 2, false)
612 /* EMIF2.5/EMIFA function */
613 MUX_CFG(DA850
, EMA_D_7
, 9, 0, 15, 1, false)
614 MUX_CFG(DA850
, EMA_D_6
, 9, 4, 15, 1, false)
615 MUX_CFG(DA850
, EMA_D_5
, 9, 8, 15, 1, false)
616 MUX_CFG(DA850
, EMA_D_4
, 9, 12, 15, 1, false)
617 MUX_CFG(DA850
, EMA_D_3
, 9, 16, 15, 1, false)
618 MUX_CFG(DA850
, EMA_D_2
, 9, 20, 15, 1, false)
619 MUX_CFG(DA850
, EMA_D_1
, 9, 24, 15, 1, false)
620 MUX_CFG(DA850
, EMA_D_0
, 9, 28, 15, 1, false)
621 MUX_CFG(DA850
, EMA_A_1
, 12, 24, 15, 1, false)
622 MUX_CFG(DA850
, EMA_A_2
, 12, 20, 15, 1, false)
623 MUX_CFG(DA850
, NEMA_CS_3
, 7, 4, 15, 1, false)
624 MUX_CFG(DA850
, NEMA_CS_4
, 7, 8, 15, 1, false)
625 MUX_CFG(DA850
, NEMA_WE
, 7, 16, 15, 1, false)
626 MUX_CFG(DA850
, NEMA_OE
, 7, 20, 15, 1, false)
627 MUX_CFG(DA850
, EMA_A_0
, 12, 28, 15, 1, false)
628 MUX_CFG(DA850
, EMA_A_3
, 12, 16, 15, 1, false)
629 MUX_CFG(DA850
, EMA_A_4
, 12, 12, 15, 1, false)
630 MUX_CFG(DA850
, EMA_A_5
, 12, 8, 15, 1, false)
631 MUX_CFG(DA850
, EMA_A_6
, 12, 4, 15, 1, false)
632 MUX_CFG(DA850
, EMA_A_7
, 12, 0, 15, 1, false)
633 MUX_CFG(DA850
, EMA_A_8
, 11, 28, 15, 1, false)
634 MUX_CFG(DA850
, EMA_A_9
, 11, 24, 15, 1, false)
635 MUX_CFG(DA850
, EMA_A_10
, 11, 20, 15, 1, false)
636 MUX_CFG(DA850
, EMA_A_11
, 11, 16, 15, 1, false)
637 MUX_CFG(DA850
, EMA_A_12
, 11, 12, 15, 1, false)
638 MUX_CFG(DA850
, EMA_A_13
, 11, 8, 15, 1, false)
639 MUX_CFG(DA850
, EMA_A_14
, 11, 4, 15, 1, false)
640 MUX_CFG(DA850
, EMA_A_15
, 11, 0, 15, 1, false)
641 MUX_CFG(DA850
, EMA_A_16
, 10, 28, 15, 1, false)
642 MUX_CFG(DA850
, EMA_A_17
, 10, 24, 15, 1, false)
643 MUX_CFG(DA850
, EMA_A_18
, 10, 20, 15, 1, false)
644 MUX_CFG(DA850
, EMA_A_19
, 10, 16, 15, 1, false)
645 MUX_CFG(DA850
, EMA_A_20
, 10, 12, 15, 1, false)
646 MUX_CFG(DA850
, EMA_A_21
, 10, 8, 15, 1, false)
647 MUX_CFG(DA850
, EMA_A_22
, 10, 4, 15, 1, false)
648 MUX_CFG(DA850
, EMA_A_23
, 10, 0, 15, 1, false)
649 MUX_CFG(DA850
, EMA_D_8
, 8, 28, 15, 1, false)
650 MUX_CFG(DA850
, EMA_D_9
, 8, 24, 15, 1, false)
651 MUX_CFG(DA850
, EMA_D_10
, 8, 20, 15, 1, false)
652 MUX_CFG(DA850
, EMA_D_11
, 8, 16, 15, 1, false)
653 MUX_CFG(DA850
, EMA_D_12
, 8, 12, 15, 1, false)
654 MUX_CFG(DA850
, EMA_D_13
, 8, 8, 15, 1, false)
655 MUX_CFG(DA850
, EMA_D_14
, 8, 4, 15, 1, false)
656 MUX_CFG(DA850
, EMA_D_15
, 8, 0, 15, 1, false)
657 MUX_CFG(DA850
, EMA_BA_1
, 5, 24, 15, 1, false)
658 MUX_CFG(DA850
, EMA_CLK
, 6, 0, 15, 1, false)
659 MUX_CFG(DA850
, EMA_WAIT_1
, 6, 24, 15, 1, false)
660 MUX_CFG(DA850
, NEMA_CS_2
, 7, 0, 15, 1, false)
662 MUX_CFG(DA850
, GPIO2_4
, 6, 12, 15, 8, false)
663 MUX_CFG(DA850
, GPIO2_6
, 6, 4, 15, 8, false)
664 MUX_CFG(DA850
, GPIO2_8
, 5, 28, 15, 8, false)
665 MUX_CFG(DA850
, GPIO2_15
, 5, 0, 15, 8, false)
666 MUX_CFG(DA850
, GPIO3_12
, 7, 12, 15, 8, false)
667 MUX_CFG(DA850
, GPIO3_13
, 7, 8, 15, 8, false)
668 MUX_CFG(DA850
, GPIO4_0
, 10, 28, 15, 8, false)
669 MUX_CFG(DA850
, GPIO4_1
, 10, 24, 15, 8, false)
670 MUX_CFG(DA850
, GPIO6_9
, 13, 24, 15, 8, false)
671 MUX_CFG(DA850
, GPIO6_10
, 13, 20, 15, 8, false)
672 MUX_CFG(DA850
, GPIO6_13
, 13, 8, 15, 8, false)
673 MUX_CFG(DA850
, RTC_ALARM
, 0, 28, 15, 2, false)
675 MUX_CFG(DA850
, VPIF_DIN0
, 15, 4, 15, 1, false)
676 MUX_CFG(DA850
, VPIF_DIN1
, 15, 0, 15, 1, false)
677 MUX_CFG(DA850
, VPIF_DIN2
, 14, 28, 15, 1, false)
678 MUX_CFG(DA850
, VPIF_DIN3
, 14, 24, 15, 1, false)
679 MUX_CFG(DA850
, VPIF_DIN4
, 14, 20, 15, 1, false)
680 MUX_CFG(DA850
, VPIF_DIN5
, 14, 16, 15, 1, false)
681 MUX_CFG(DA850
, VPIF_DIN6
, 14, 12, 15, 1, false)
682 MUX_CFG(DA850
, VPIF_DIN7
, 14, 8, 15, 1, false)
683 MUX_CFG(DA850
, VPIF_DIN8
, 16, 4, 15, 1, false)
684 MUX_CFG(DA850
, VPIF_DIN9
, 16, 0, 15, 1, false)
685 MUX_CFG(DA850
, VPIF_DIN10
, 15, 28, 15, 1, false)
686 MUX_CFG(DA850
, VPIF_DIN11
, 15, 24, 15, 1, false)
687 MUX_CFG(DA850
, VPIF_DIN12
, 15, 20, 15, 1, false)
688 MUX_CFG(DA850
, VPIF_DIN13
, 15, 16, 15, 1, false)
689 MUX_CFG(DA850
, VPIF_DIN14
, 15, 12, 15, 1, false)
690 MUX_CFG(DA850
, VPIF_DIN15
, 15, 8, 15, 1, false)
691 MUX_CFG(DA850
, VPIF_CLKIN0
, 14, 0, 15, 1, false)
692 MUX_CFG(DA850
, VPIF_CLKIN1
, 14, 4, 15, 1, false)
693 MUX_CFG(DA850
, VPIF_CLKIN2
, 19, 8, 15, 1, false)
694 MUX_CFG(DA850
, VPIF_CLKIN3
, 19, 16, 15, 1, false)
696 MUX_CFG(DA850
, VPIF_DOUT0
, 17, 4, 15, 1, false)
697 MUX_CFG(DA850
, VPIF_DOUT1
, 17, 0, 15, 1, false)
698 MUX_CFG(DA850
, VPIF_DOUT2
, 16, 28, 15, 1, false)
699 MUX_CFG(DA850
, VPIF_DOUT3
, 16, 24, 15, 1, false)
700 MUX_CFG(DA850
, VPIF_DOUT4
, 16, 20, 15, 1, false)
701 MUX_CFG(DA850
, VPIF_DOUT5
, 16, 16, 15, 1, false)
702 MUX_CFG(DA850
, VPIF_DOUT6
, 16, 12, 15, 1, false)
703 MUX_CFG(DA850
, VPIF_DOUT7
, 16, 8, 15, 1, false)
704 MUX_CFG(DA850
, VPIF_DOUT8
, 18, 4, 15, 1, false)
705 MUX_CFG(DA850
, VPIF_DOUT9
, 18, 0, 15, 1, false)
706 MUX_CFG(DA850
, VPIF_DOUT10
, 17, 28, 15, 1, false)
707 MUX_CFG(DA850
, VPIF_DOUT11
, 17, 24, 15, 1, false)
708 MUX_CFG(DA850
, VPIF_DOUT12
, 17, 20, 15, 1, false)
709 MUX_CFG(DA850
, VPIF_DOUT13
, 17, 16, 15, 1, false)
710 MUX_CFG(DA850
, VPIF_DOUT14
, 17, 12, 15, 1, false)
711 MUX_CFG(DA850
, VPIF_DOUT15
, 17, 8, 15, 1, false)
712 MUX_CFG(DA850
, VPIF_CLKO2
, 19, 12, 15, 1, false)
713 MUX_CFG(DA850
, VPIF_CLKO3
, 19, 20, 15, 1, false)
717 const short da850_i2c0_pins
[] __initconst
= {
718 DA850_I2C0_SDA
, DA850_I2C0_SCL
,
722 const short da850_i2c1_pins
[] __initconst
= {
723 DA850_I2C1_SCL
, DA850_I2C1_SDA
,
727 const short da850_lcdcntl_pins
[] __initconst
= {
728 DA850_LCD_D_0
, DA850_LCD_D_1
, DA850_LCD_D_2
, DA850_LCD_D_3
,
729 DA850_LCD_D_4
, DA850_LCD_D_5
, DA850_LCD_D_6
, DA850_LCD_D_7
,
730 DA850_LCD_D_8
, DA850_LCD_D_9
, DA850_LCD_D_10
, DA850_LCD_D_11
,
731 DA850_LCD_D_12
, DA850_LCD_D_13
, DA850_LCD_D_14
, DA850_LCD_D_15
,
732 DA850_LCD_PCLK
, DA850_LCD_HSYNC
, DA850_LCD_VSYNC
, DA850_NLCD_AC_ENB_CS
,
736 const short da850_vpif_capture_pins
[] __initconst
= {
737 DA850_VPIF_DIN0
, DA850_VPIF_DIN1
, DA850_VPIF_DIN2
, DA850_VPIF_DIN3
,
738 DA850_VPIF_DIN4
, DA850_VPIF_DIN5
, DA850_VPIF_DIN6
, DA850_VPIF_DIN7
,
739 DA850_VPIF_DIN8
, DA850_VPIF_DIN9
, DA850_VPIF_DIN10
, DA850_VPIF_DIN11
,
740 DA850_VPIF_DIN12
, DA850_VPIF_DIN13
, DA850_VPIF_DIN14
, DA850_VPIF_DIN15
,
741 DA850_VPIF_CLKIN0
, DA850_VPIF_CLKIN1
, DA850_VPIF_CLKIN2
,
746 const short da850_vpif_display_pins
[] __initconst
= {
747 DA850_VPIF_DOUT0
, DA850_VPIF_DOUT1
, DA850_VPIF_DOUT2
, DA850_VPIF_DOUT3
,
748 DA850_VPIF_DOUT4
, DA850_VPIF_DOUT5
, DA850_VPIF_DOUT6
, DA850_VPIF_DOUT7
,
749 DA850_VPIF_DOUT8
, DA850_VPIF_DOUT9
, DA850_VPIF_DOUT10
,
750 DA850_VPIF_DOUT11
, DA850_VPIF_DOUT12
, DA850_VPIF_DOUT13
,
751 DA850_VPIF_DOUT14
, DA850_VPIF_DOUT15
, DA850_VPIF_CLKO2
,
756 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
757 static u8 da850_default_priorities
[DA850_N_CP_INTC_IRQ
] = {
758 [IRQ_DA8XX_COMMTX
] = 7,
759 [IRQ_DA8XX_COMMRX
] = 7,
760 [IRQ_DA8XX_NINT
] = 7,
761 [IRQ_DA8XX_EVTOUT0
] = 7,
762 [IRQ_DA8XX_EVTOUT1
] = 7,
763 [IRQ_DA8XX_EVTOUT2
] = 7,
764 [IRQ_DA8XX_EVTOUT3
] = 7,
765 [IRQ_DA8XX_EVTOUT4
] = 7,
766 [IRQ_DA8XX_EVTOUT5
] = 7,
767 [IRQ_DA8XX_EVTOUT6
] = 7,
768 [IRQ_DA8XX_EVTOUT7
] = 7,
769 [IRQ_DA8XX_CCINT0
] = 7,
770 [IRQ_DA8XX_CCERRINT
] = 7,
771 [IRQ_DA8XX_TCERRINT0
] = 7,
772 [IRQ_DA8XX_AEMIFINT
] = 7,
773 [IRQ_DA8XX_I2CINT0
] = 7,
774 [IRQ_DA8XX_MMCSDINT0
] = 7,
775 [IRQ_DA8XX_MMCSDINT1
] = 7,
776 [IRQ_DA8XX_ALLINT0
] = 7,
778 [IRQ_DA8XX_SPINT0
] = 7,
779 [IRQ_DA8XX_TINT12_0
] = 7,
780 [IRQ_DA8XX_TINT34_0
] = 7,
781 [IRQ_DA8XX_TINT12_1
] = 7,
782 [IRQ_DA8XX_TINT34_1
] = 7,
783 [IRQ_DA8XX_UARTINT0
] = 7,
784 [IRQ_DA8XX_KEYMGRINT
] = 7,
785 [IRQ_DA850_MPUADDRERR0
] = 7,
786 [IRQ_DA8XX_CHIPINT0
] = 7,
787 [IRQ_DA8XX_CHIPINT1
] = 7,
788 [IRQ_DA8XX_CHIPINT2
] = 7,
789 [IRQ_DA8XX_CHIPINT3
] = 7,
790 [IRQ_DA8XX_TCERRINT1
] = 7,
791 [IRQ_DA8XX_C0_RX_THRESH_PULSE
] = 7,
792 [IRQ_DA8XX_C0_RX_PULSE
] = 7,
793 [IRQ_DA8XX_C0_TX_PULSE
] = 7,
794 [IRQ_DA8XX_C0_MISC_PULSE
] = 7,
795 [IRQ_DA8XX_C1_RX_THRESH_PULSE
] = 7,
796 [IRQ_DA8XX_C1_RX_PULSE
] = 7,
797 [IRQ_DA8XX_C1_TX_PULSE
] = 7,
798 [IRQ_DA8XX_C1_MISC_PULSE
] = 7,
799 [IRQ_DA8XX_MEMERR
] = 7,
800 [IRQ_DA8XX_GPIO0
] = 7,
801 [IRQ_DA8XX_GPIO1
] = 7,
802 [IRQ_DA8XX_GPIO2
] = 7,
803 [IRQ_DA8XX_GPIO3
] = 7,
804 [IRQ_DA8XX_GPIO4
] = 7,
805 [IRQ_DA8XX_GPIO5
] = 7,
806 [IRQ_DA8XX_GPIO6
] = 7,
807 [IRQ_DA8XX_GPIO7
] = 7,
808 [IRQ_DA8XX_GPIO8
] = 7,
809 [IRQ_DA8XX_I2CINT1
] = 7,
810 [IRQ_DA8XX_LCDINT
] = 7,
811 [IRQ_DA8XX_UARTINT1
] = 7,
812 [IRQ_DA8XX_MCASPINT
] = 7,
813 [IRQ_DA8XX_ALLINT1
] = 7,
814 [IRQ_DA8XX_SPINT1
] = 7,
815 [IRQ_DA8XX_UHPI_INT1
] = 7,
816 [IRQ_DA8XX_USB_INT
] = 7,
817 [IRQ_DA8XX_IRQN
] = 7,
818 [IRQ_DA8XX_RWAKEUP
] = 7,
819 [IRQ_DA8XX_UARTINT2
] = 7,
820 [IRQ_DA8XX_DFTSSINT
] = 7,
821 [IRQ_DA8XX_EHRPWM0
] = 7,
822 [IRQ_DA8XX_EHRPWM0TZ
] = 7,
823 [IRQ_DA8XX_EHRPWM1
] = 7,
824 [IRQ_DA8XX_EHRPWM1TZ
] = 7,
825 [IRQ_DA850_SATAINT
] = 7,
826 [IRQ_DA850_TINTALL_2
] = 7,
827 [IRQ_DA8XX_ECAP0
] = 7,
828 [IRQ_DA8XX_ECAP1
] = 7,
829 [IRQ_DA8XX_ECAP2
] = 7,
830 [IRQ_DA850_MMCSDINT0_1
] = 7,
831 [IRQ_DA850_MMCSDINT1_1
] = 7,
832 [IRQ_DA850_T12CMPINT0_2
] = 7,
833 [IRQ_DA850_T12CMPINT1_2
] = 7,
834 [IRQ_DA850_T12CMPINT2_2
] = 7,
835 [IRQ_DA850_T12CMPINT3_2
] = 7,
836 [IRQ_DA850_T12CMPINT4_2
] = 7,
837 [IRQ_DA850_T12CMPINT5_2
] = 7,
838 [IRQ_DA850_T12CMPINT6_2
] = 7,
839 [IRQ_DA850_T12CMPINT7_2
] = 7,
840 [IRQ_DA850_T12CMPINT0_3
] = 7,
841 [IRQ_DA850_T12CMPINT1_3
] = 7,
842 [IRQ_DA850_T12CMPINT2_3
] = 7,
843 [IRQ_DA850_T12CMPINT3_3
] = 7,
844 [IRQ_DA850_T12CMPINT4_3
] = 7,
845 [IRQ_DA850_T12CMPINT5_3
] = 7,
846 [IRQ_DA850_T12CMPINT6_3
] = 7,
847 [IRQ_DA850_T12CMPINT7_3
] = 7,
848 [IRQ_DA850_RPIINT
] = 7,
849 [IRQ_DA850_VPIFINT
] = 7,
850 [IRQ_DA850_CCINT1
] = 7,
851 [IRQ_DA850_CCERRINT1
] = 7,
852 [IRQ_DA850_TCERRINT2
] = 7,
853 [IRQ_DA850_TINTALL_3
] = 7,
854 [IRQ_DA850_MCBSP0RINT
] = 7,
855 [IRQ_DA850_MCBSP0XINT
] = 7,
856 [IRQ_DA850_MCBSP1RINT
] = 7,
857 [IRQ_DA850_MCBSP1XINT
] = 7,
858 [IRQ_DA8XX_ARMCLKSTOPREQ
] = 7,
861 static struct map_desc da850_io_desc
[] = {
864 .pfn
= __phys_to_pfn(IO_PHYS
),
869 .virtual = DA8XX_CP_INTC_VIRT
,
870 .pfn
= __phys_to_pfn(DA8XX_CP_INTC_BASE
),
871 .length
= DA8XX_CP_INTC_SIZE
,
876 static u32 da850_psc_bases
[] = { DA8XX_PSC0_BASE
, DA8XX_PSC1_BASE
};
878 /* Contents of JTAG ID register used to identify exact cpu type */
879 static struct davinci_id da850_ids
[] = {
883 .manufacturer
= 0x017, /* 0x02f >> 1 */
884 .cpu_id
= DAVINCI_CPU_ID_DA850
,
885 .name
= "da850/omap-l138",
890 .manufacturer
= 0x017, /* 0x02f >> 1 */
891 .cpu_id
= DAVINCI_CPU_ID_DA850
,
892 .name
= "da850/omap-l138/am18x",
896 static struct davinci_timer_instance da850_timer_instance
[4] = {
898 .base
= DA8XX_TIMER64P0_BASE
,
899 .bottom_irq
= IRQ_DA8XX_TINT12_0
,
900 .top_irq
= IRQ_DA8XX_TINT34_0
,
903 .base
= DA8XX_TIMER64P1_BASE
,
904 .bottom_irq
= IRQ_DA8XX_TINT12_1
,
905 .top_irq
= IRQ_DA8XX_TINT34_1
,
908 .base
= DA850_TIMER64P2_BASE
,
909 .bottom_irq
= IRQ_DA850_TINT12_2
,
910 .top_irq
= IRQ_DA850_TINT34_2
,
913 .base
= DA850_TIMER64P3_BASE
,
914 .bottom_irq
= IRQ_DA850_TINT12_3
,
915 .top_irq
= IRQ_DA850_TINT34_3
,
920 * T0_BOT: Timer 0, bottom : Used for clock_event
921 * T0_TOP: Timer 0, top : Used for clocksource
922 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
924 static struct davinci_timer_info da850_timer_info
= {
925 .timers
= da850_timer_instance
,
926 .clockevent_id
= T0_BOT
,
927 .clocksource_id
= T0_TOP
,
930 #ifdef CONFIG_CPU_FREQ
933 * According to the TRM, minimum PLLM results in maximum power savings.
934 * The OPP definitions below should keep the PLLM as low as possible.
936 * The output of the PLLM must be between 300 to 600 MHz.
939 unsigned int freq
; /* in KHz */
942 unsigned int postdiv
;
943 unsigned int cvdd_min
; /* in uV */
944 unsigned int cvdd_max
; /* in uV */
947 static const struct da850_opp da850_opp_456
= {
956 static const struct da850_opp da850_opp_408
= {
965 static const struct da850_opp da850_opp_372
= {
974 static const struct da850_opp da850_opp_300
= {
983 static const struct da850_opp da850_opp_200
= {
992 static const struct da850_opp da850_opp_96
= {
1003 .driver_data = (unsigned int) &da850_opp_##freq, \
1004 .frequency = freq * 1000, \
1007 static struct cpufreq_frequency_table da850_freq_table
[] = {
1016 .frequency
= CPUFREQ_TABLE_END
,
1020 #ifdef CONFIG_REGULATOR
1021 static int da850_set_voltage(unsigned int index
);
1022 static int da850_regulator_init(void);
1025 static struct davinci_cpufreq_config cpufreq_info
= {
1026 .freq_table
= da850_freq_table
,
1027 #ifdef CONFIG_REGULATOR
1028 .init
= da850_regulator_init
,
1029 .set_voltage
= da850_set_voltage
,
1033 #ifdef CONFIG_REGULATOR
1034 static struct regulator
*cvdd
;
1036 static int da850_set_voltage(unsigned int index
)
1038 struct da850_opp
*opp
;
1043 opp
= (struct da850_opp
*) cpufreq_info
.freq_table
[index
].driver_data
;
1045 return regulator_set_voltage(cvdd
, opp
->cvdd_min
, opp
->cvdd_max
);
1048 static int da850_regulator_init(void)
1050 cvdd
= regulator_get(NULL
, "cvdd");
1051 if (WARN(IS_ERR(cvdd
), "Unable to obtain voltage regulator for CVDD;"
1052 " voltage scaling unsupported\n")) {
1053 return PTR_ERR(cvdd
);
1060 static struct platform_device da850_cpufreq_device
= {
1061 .name
= "cpufreq-davinci",
1063 .platform_data
= &cpufreq_info
,
1068 unsigned int da850_max_speed
= 300000;
1070 int da850_register_cpufreq(char *async_clk
)
1074 /* cpufreq driver can help keep an "async" clock constant */
1076 clk_add_alias("async", da850_cpufreq_device
.name
,
1078 for (i
= 0; i
< ARRAY_SIZE(da850_freq_table
); i
++) {
1079 if (da850_freq_table
[i
].frequency
<= da850_max_speed
) {
1080 cpufreq_info
.freq_table
= &da850_freq_table
[i
];
1085 return platform_device_register(&da850_cpufreq_device
);
1088 static int da850_round_armrate(struct clk
*clk
, unsigned long rate
)
1091 unsigned int best
= (unsigned int) -1;
1092 struct cpufreq_frequency_table
*table
= cpufreq_info
.freq_table
;
1093 struct cpufreq_frequency_table
*pos
;
1095 rate
/= 1000; /* convert to kHz */
1097 cpufreq_for_each_entry(pos
, table
) {
1098 diff
= pos
->frequency
- rate
;
1104 ret
= pos
->frequency
;
1111 static int da850_set_armrate(struct clk
*clk
, unsigned long index
)
1113 struct clk
*pllclk
= &pll0_clk
;
1115 return clk_set_rate(pllclk
, index
);
1118 static int da850_set_pll0rate(struct clk
*clk
, unsigned long index
)
1120 unsigned int prediv
, mult
, postdiv
;
1121 struct da850_opp
*opp
;
1122 struct pll_data
*pll
= clk
->pll_data
;
1125 opp
= (struct da850_opp
*) cpufreq_info
.freq_table
[index
].driver_data
;
1126 prediv
= opp
->prediv
;
1128 postdiv
= opp
->postdiv
;
1130 ret
= davinci_set_pllrate(pll
, prediv
, mult
, postdiv
);
1137 int __init
da850_register_cpufreq(char *async_clk
)
1142 static int da850_set_armrate(struct clk
*clk
, unsigned long rate
)
1147 static int da850_set_pll0rate(struct clk
*clk
, unsigned long armrate
)
1152 static int da850_round_armrate(struct clk
*clk
, unsigned long rate
)
1158 int __init
da850_register_pm(struct platform_device
*pdev
)
1161 struct davinci_pm_config
*pdata
= pdev
->dev
.platform_data
;
1163 ret
= davinci_cfg_reg(DA850_RTC_ALARM
);
1167 pdata
->ddr2_ctlr_base
= da8xx_get_mem_ctlr();
1168 pdata
->deepsleep_reg
= DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG
);
1169 pdata
->ddrpsc_num
= DA8XX_LPSC1_EMIF3C
;
1171 pdata
->cpupll_reg_base
= ioremap(DA8XX_PLL0_BASE
, SZ_4K
);
1172 if (!pdata
->cpupll_reg_base
)
1175 pdata
->ddrpll_reg_base
= ioremap(DA850_PLL1_BASE
, SZ_4K
);
1176 if (!pdata
->ddrpll_reg_base
) {
1181 pdata
->ddrpsc_reg_base
= ioremap(DA8XX_PSC1_BASE
, SZ_4K
);
1182 if (!pdata
->ddrpsc_reg_base
) {
1187 return platform_device_register(pdev
);
1190 iounmap(pdata
->ddrpll_reg_base
);
1192 iounmap(pdata
->cpupll_reg_base
);
1196 /* VPIF resource, platform data */
1197 static u64 da850_vpif_dma_mask
= DMA_BIT_MASK(32);
1199 static struct resource da850_vpif_resource
[] = {
1201 .start
= DA8XX_VPIF_BASE
,
1202 .end
= DA8XX_VPIF_BASE
+ 0xfff,
1203 .flags
= IORESOURCE_MEM
,
1207 static struct platform_device da850_vpif_dev
= {
1211 .dma_mask
= &da850_vpif_dma_mask
,
1212 .coherent_dma_mask
= DMA_BIT_MASK(32),
1214 .resource
= da850_vpif_resource
,
1215 .num_resources
= ARRAY_SIZE(da850_vpif_resource
),
1218 static struct resource da850_vpif_display_resource
[] = {
1220 .start
= IRQ_DA850_VPIFINT
,
1221 .end
= IRQ_DA850_VPIFINT
,
1222 .flags
= IORESOURCE_IRQ
,
1226 static struct platform_device da850_vpif_display_dev
= {
1227 .name
= "vpif_display",
1230 .dma_mask
= &da850_vpif_dma_mask
,
1231 .coherent_dma_mask
= DMA_BIT_MASK(32),
1233 .resource
= da850_vpif_display_resource
,
1234 .num_resources
= ARRAY_SIZE(da850_vpif_display_resource
),
1237 static struct resource da850_vpif_capture_resource
[] = {
1239 .start
= IRQ_DA850_VPIFINT
,
1240 .end
= IRQ_DA850_VPIFINT
,
1241 .flags
= IORESOURCE_IRQ
,
1244 .start
= IRQ_DA850_VPIFINT
,
1245 .end
= IRQ_DA850_VPIFINT
,
1246 .flags
= IORESOURCE_IRQ
,
1250 static struct platform_device da850_vpif_capture_dev
= {
1251 .name
= "vpif_capture",
1254 .dma_mask
= &da850_vpif_dma_mask
,
1255 .coherent_dma_mask
= DMA_BIT_MASK(32),
1257 .resource
= da850_vpif_capture_resource
,
1258 .num_resources
= ARRAY_SIZE(da850_vpif_capture_resource
),
1261 int __init
da850_register_vpif(void)
1263 return platform_device_register(&da850_vpif_dev
);
1266 int __init
da850_register_vpif_display(struct vpif_display_config
1269 da850_vpif_display_dev
.dev
.platform_data
= display_config
;
1270 return platform_device_register(&da850_vpif_display_dev
);
1273 int __init
da850_register_vpif_capture(struct vpif_capture_config
1276 da850_vpif_capture_dev
.dev
.platform_data
= capture_config
;
1277 return platform_device_register(&da850_vpif_capture_dev
);
1280 static struct davinci_gpio_platform_data da850_gpio_platform_data
= {
1284 int __init
da850_register_gpio(void)
1286 return da8xx_register_gpio(&da850_gpio_platform_data
);
1289 static struct davinci_soc_info davinci_soc_info_da850
= {
1290 .io_desc
= da850_io_desc
,
1291 .io_desc_num
= ARRAY_SIZE(da850_io_desc
),
1292 .jtag_id_reg
= DA8XX_SYSCFG0_BASE
+ DA8XX_JTAG_ID_REG
,
1294 .ids_num
= ARRAY_SIZE(da850_ids
),
1295 .cpu_clks
= da850_clks
,
1296 .psc_bases
= da850_psc_bases
,
1297 .psc_bases_num
= ARRAY_SIZE(da850_psc_bases
),
1298 .pinmux_base
= DA8XX_SYSCFG0_BASE
+ 0x120,
1299 .pinmux_pins
= da850_pins
,
1300 .pinmux_pins_num
= ARRAY_SIZE(da850_pins
),
1301 .intc_base
= DA8XX_CP_INTC_BASE
,
1302 .intc_type
= DAVINCI_INTC_TYPE_CP_INTC
,
1303 .intc_irq_prios
= da850_default_priorities
,
1304 .intc_irq_num
= DA850_N_CP_INTC_IRQ
,
1305 .timer_info
= &da850_timer_info
,
1306 .emac_pdata
= &da8xx_emac_pdata
,
1307 .sram_dma
= DA8XX_SHARED_RAM_BASE
,
1308 .sram_len
= SZ_128K
,
1311 void __init
da850_init(void)
1315 davinci_common_init(&davinci_soc_info_da850
);
1317 da8xx_syscfg0_base
= ioremap(DA8XX_SYSCFG0_BASE
, SZ_4K
);
1318 if (WARN(!da8xx_syscfg0_base
, "Unable to map syscfg0 module"))
1321 da8xx_syscfg1_base
= ioremap(DA8XX_SYSCFG1_BASE
, SZ_4K
);
1322 if (WARN(!da8xx_syscfg1_base
, "Unable to map syscfg1 module"))
1325 /* Unlock writing to PLL0 registers */
1326 v
= __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG
));
1327 v
&= ~CFGCHIP0_PLL_MASTER_LOCK
;
1328 __raw_writel(v
, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG
));
1330 /* Unlock writing to PLL1 registers */
1331 v
= __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG
));
1332 v
&= ~CFGCHIP3_PLL1_MASTER_LOCK
;
1333 __raw_writel(v
, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG
));
1335 davinci_clk_init(davinci_soc_info_da850
.cpu_clks
);