2 * TI DA850/OMAP-L138 chip specific setup
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
14 #include <linux/gpio.h>
15 #include <linux/init.h>
16 #include <linux/clk.h>
17 #include <linux/platform_device.h>
18 #include <linux/cpufreq.h>
19 #include <linux/regulator/consumer.h>
21 #include <asm/mach/map.h>
24 #include <mach/irqs.h>
25 #include <mach/cputype.h>
26 #include <mach/common.h>
27 #include <mach/time.h>
28 #include <mach/da8xx.h>
29 #include <mach/cpufreq.h>
31 #include <mach/gpio-davinci.h>
36 /* SoC specific clock flags */
37 #define DA850_CLK_ASYNC3 BIT(16)
39 #define DA850_PLL1_BASE 0x01e1a000
40 #define DA850_TIMER64P2_BASE 0x01f0c000
41 #define DA850_TIMER64P3_BASE 0x01f0d000
43 #define DA850_REF_FREQ 24000000
45 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
46 #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
47 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
49 static int da850_set_armrate(struct clk
*clk
, unsigned long rate
);
50 static int da850_round_armrate(struct clk
*clk
, unsigned long rate
);
51 static int da850_set_pll0rate(struct clk
*clk
, unsigned long armrate
);
53 static struct pll_data pll0_data
= {
55 .phys_base
= DA8XX_PLL0_BASE
,
56 .flags
= PLL_HAS_PREDIV
| PLL_HAS_POSTDIV
,
59 static struct clk ref_clk
= {
61 .rate
= DA850_REF_FREQ
,
62 .set_rate
= davinci_simple_set_rate
,
65 static struct clk pll0_clk
= {
68 .pll_data
= &pll0_data
,
70 .set_rate
= da850_set_pll0rate
,
73 static struct clk pll0_aux_clk
= {
74 .name
= "pll0_aux_clk",
76 .flags
= CLK_PLL
| PRE_PLL
,
79 static struct clk pll0_sysclk2
= {
80 .name
= "pll0_sysclk2",
86 static struct clk pll0_sysclk3
= {
87 .name
= "pll0_sysclk3",
91 .set_rate
= davinci_set_sysclk_rate
,
95 static struct clk pll0_sysclk4
= {
96 .name
= "pll0_sysclk4",
102 static struct clk pll0_sysclk5
= {
103 .name
= "pll0_sysclk5",
109 static struct clk pll0_sysclk6
= {
110 .name
= "pll0_sysclk6",
116 static struct clk pll0_sysclk7
= {
117 .name
= "pll0_sysclk7",
123 static struct pll_data pll1_data
= {
125 .phys_base
= DA850_PLL1_BASE
,
126 .flags
= PLL_HAS_POSTDIV
,
129 static struct clk pll1_clk
= {
132 .pll_data
= &pll1_data
,
136 static struct clk pll1_aux_clk
= {
137 .name
= "pll1_aux_clk",
139 .flags
= CLK_PLL
| PRE_PLL
,
142 static struct clk pll1_sysclk2
= {
143 .name
= "pll1_sysclk2",
149 static struct clk pll1_sysclk3
= {
150 .name
= "pll1_sysclk3",
156 static struct clk i2c0_clk
= {
158 .parent
= &pll0_aux_clk
,
161 static struct clk timerp64_0_clk
= {
163 .parent
= &pll0_aux_clk
,
166 static struct clk timerp64_1_clk
= {
168 .parent
= &pll0_aux_clk
,
171 static struct clk arm_rom_clk
= {
173 .parent
= &pll0_sysclk2
,
174 .lpsc
= DA8XX_LPSC0_ARM_RAM_ROM
,
175 .flags
= ALWAYS_ENABLED
,
178 static struct clk tpcc0_clk
= {
180 .parent
= &pll0_sysclk2
,
181 .lpsc
= DA8XX_LPSC0_TPCC
,
182 .flags
= ALWAYS_ENABLED
| CLK_PSC
,
185 static struct clk tptc0_clk
= {
187 .parent
= &pll0_sysclk2
,
188 .lpsc
= DA8XX_LPSC0_TPTC0
,
189 .flags
= ALWAYS_ENABLED
,
192 static struct clk tptc1_clk
= {
194 .parent
= &pll0_sysclk2
,
195 .lpsc
= DA8XX_LPSC0_TPTC1
,
196 .flags
= ALWAYS_ENABLED
,
199 static struct clk tpcc1_clk
= {
201 .parent
= &pll0_sysclk2
,
202 .lpsc
= DA850_LPSC1_TPCC1
,
204 .flags
= CLK_PSC
| ALWAYS_ENABLED
,
207 static struct clk tptc2_clk
= {
209 .parent
= &pll0_sysclk2
,
210 .lpsc
= DA850_LPSC1_TPTC2
,
212 .flags
= ALWAYS_ENABLED
,
215 static struct clk pruss_clk
= {
217 .parent
= &pll0_sysclk2
,
218 .lpsc
= DA8XX_LPSC0_PRUSS
,
221 static struct clk uart0_clk
= {
223 .parent
= &pll0_sysclk2
,
224 .lpsc
= DA8XX_LPSC0_UART0
,
227 static struct clk uart1_clk
= {
229 .parent
= &pll0_sysclk2
,
230 .lpsc
= DA8XX_LPSC1_UART1
,
232 .flags
= DA850_CLK_ASYNC3
,
235 static struct clk uart2_clk
= {
237 .parent
= &pll0_sysclk2
,
238 .lpsc
= DA8XX_LPSC1_UART2
,
240 .flags
= DA850_CLK_ASYNC3
,
243 static struct clk aintc_clk
= {
245 .parent
= &pll0_sysclk4
,
246 .lpsc
= DA8XX_LPSC0_AINTC
,
247 .flags
= ALWAYS_ENABLED
,
250 static struct clk gpio_clk
= {
252 .parent
= &pll0_sysclk4
,
253 .lpsc
= DA8XX_LPSC1_GPIO
,
257 static struct clk i2c1_clk
= {
259 .parent
= &pll0_sysclk4
,
260 .lpsc
= DA8XX_LPSC1_I2C
,
264 static struct clk emif3_clk
= {
266 .parent
= &pll0_sysclk5
,
267 .lpsc
= DA8XX_LPSC1_EMIF3C
,
269 .flags
= ALWAYS_ENABLED
,
272 static struct clk arm_clk
= {
274 .parent
= &pll0_sysclk6
,
275 .lpsc
= DA8XX_LPSC0_ARM
,
276 .flags
= ALWAYS_ENABLED
,
277 .set_rate
= da850_set_armrate
,
278 .round_rate
= da850_round_armrate
,
281 static struct clk rmii_clk
= {
283 .parent
= &pll0_sysclk7
,
286 static struct clk emac_clk
= {
288 .parent
= &pll0_sysclk4
,
289 .lpsc
= DA8XX_LPSC1_CPGMAC
,
293 static struct clk mcasp_clk
= {
295 .parent
= &pll0_sysclk2
,
296 .lpsc
= DA8XX_LPSC1_McASP0
,
298 .flags
= DA850_CLK_ASYNC3
,
301 static struct clk lcdc_clk
= {
303 .parent
= &pll0_sysclk2
,
304 .lpsc
= DA8XX_LPSC1_LCDC
,
308 static struct clk mmcsd0_clk
= {
310 .parent
= &pll0_sysclk2
,
311 .lpsc
= DA8XX_LPSC0_MMC_SD
,
314 static struct clk mmcsd1_clk
= {
316 .parent
= &pll0_sysclk2
,
317 .lpsc
= DA850_LPSC1_MMC_SD1
,
321 static struct clk aemif_clk
= {
323 .parent
= &pll0_sysclk3
,
324 .lpsc
= DA8XX_LPSC0_EMIF25
,
325 .flags
= ALWAYS_ENABLED
,
328 static struct clk usb11_clk
= {
330 .parent
= &pll0_sysclk4
,
331 .lpsc
= DA8XX_LPSC1_USB11
,
335 static struct clk usb20_clk
= {
337 .parent
= &pll0_sysclk2
,
338 .lpsc
= DA8XX_LPSC1_USB20
,
342 static struct clk spi0_clk
= {
344 .parent
= &pll0_sysclk2
,
345 .lpsc
= DA8XX_LPSC0_SPI0
,
348 static struct clk spi1_clk
= {
350 .parent
= &pll0_sysclk2
,
351 .lpsc
= DA8XX_LPSC1_SPI1
,
353 .flags
= DA850_CLK_ASYNC3
,
356 static struct clk vpif_clk
= {
358 .parent
= &pll0_sysclk2
,
359 .lpsc
= DA850_LPSC1_VPIF
,
363 static struct clk sata_clk
= {
365 .parent
= &pll0_sysclk2
,
366 .lpsc
= DA850_LPSC1_SATA
,
371 static struct clk_lookup da850_clks
[] = {
372 CLK(NULL
, "ref", &ref_clk
),
373 CLK(NULL
, "pll0", &pll0_clk
),
374 CLK(NULL
, "pll0_aux", &pll0_aux_clk
),
375 CLK(NULL
, "pll0_sysclk2", &pll0_sysclk2
),
376 CLK(NULL
, "pll0_sysclk3", &pll0_sysclk3
),
377 CLK(NULL
, "pll0_sysclk4", &pll0_sysclk4
),
378 CLK(NULL
, "pll0_sysclk5", &pll0_sysclk5
),
379 CLK(NULL
, "pll0_sysclk6", &pll0_sysclk6
),
380 CLK(NULL
, "pll0_sysclk7", &pll0_sysclk7
),
381 CLK(NULL
, "pll1", &pll1_clk
),
382 CLK(NULL
, "pll1_aux", &pll1_aux_clk
),
383 CLK(NULL
, "pll1_sysclk2", &pll1_sysclk2
),
384 CLK(NULL
, "pll1_sysclk3", &pll1_sysclk3
),
385 CLK("i2c_davinci.1", NULL
, &i2c0_clk
),
386 CLK(NULL
, "timer0", &timerp64_0_clk
),
387 CLK("watchdog", NULL
, &timerp64_1_clk
),
388 CLK(NULL
, "arm_rom", &arm_rom_clk
),
389 CLK(NULL
, "tpcc0", &tpcc0_clk
),
390 CLK(NULL
, "tptc0", &tptc0_clk
),
391 CLK(NULL
, "tptc1", &tptc1_clk
),
392 CLK(NULL
, "tpcc1", &tpcc1_clk
),
393 CLK(NULL
, "tptc2", &tptc2_clk
),
394 CLK("pruss_uio", "pruss", &pruss_clk
),
395 CLK(NULL
, "uart0", &uart0_clk
),
396 CLK(NULL
, "uart1", &uart1_clk
),
397 CLK(NULL
, "uart2", &uart2_clk
),
398 CLK(NULL
, "aintc", &aintc_clk
),
399 CLK(NULL
, "gpio", &gpio_clk
),
400 CLK("i2c_davinci.2", NULL
, &i2c1_clk
),
401 CLK(NULL
, "emif3", &emif3_clk
),
402 CLK(NULL
, "arm", &arm_clk
),
403 CLK(NULL
, "rmii", &rmii_clk
),
404 CLK("davinci_emac.1", NULL
, &emac_clk
),
405 CLK("davinci-mcasp.0", NULL
, &mcasp_clk
),
406 CLK("da8xx_lcdc.0", "fck", &lcdc_clk
),
407 CLK("davinci_mmc.0", NULL
, &mmcsd0_clk
),
408 CLK("davinci_mmc.1", NULL
, &mmcsd1_clk
),
409 CLK(NULL
, "aemif", &aemif_clk
),
410 CLK(NULL
, "usb11", &usb11_clk
),
411 CLK(NULL
, "usb20", &usb20_clk
),
412 CLK("spi_davinci.0", NULL
, &spi0_clk
),
413 CLK("spi_davinci.1", NULL
, &spi1_clk
),
414 CLK("vpif", NULL
, &vpif_clk
),
415 CLK("ahci", NULL
, &sata_clk
),
416 CLK(NULL
, NULL
, NULL
),
420 * Device specific mux setup
422 * soc description mux mode mode mux dbg
423 * reg offset mask mode
425 static const struct mux_config da850_pins
[] = {
426 #ifdef CONFIG_DAVINCI_MUX
428 MUX_CFG(DA850
, NUART0_CTS
, 3, 24, 15, 2, false)
429 MUX_CFG(DA850
, NUART0_RTS
, 3, 28, 15, 2, false)
430 MUX_CFG(DA850
, UART0_RXD
, 3, 16, 15, 2, false)
431 MUX_CFG(DA850
, UART0_TXD
, 3, 20, 15, 2, false)
433 MUX_CFG(DA850
, UART1_RXD
, 4, 24, 15, 2, false)
434 MUX_CFG(DA850
, UART1_TXD
, 4, 28, 15, 2, false)
436 MUX_CFG(DA850
, UART2_RXD
, 4, 16, 15, 2, false)
437 MUX_CFG(DA850
, UART2_TXD
, 4, 20, 15, 2, false)
439 MUX_CFG(DA850
, I2C1_SCL
, 4, 16, 15, 4, false)
440 MUX_CFG(DA850
, I2C1_SDA
, 4, 20, 15, 4, false)
442 MUX_CFG(DA850
, I2C0_SDA
, 4, 12, 15, 2, false)
443 MUX_CFG(DA850
, I2C0_SCL
, 4, 8, 15, 2, false)
445 MUX_CFG(DA850
, MII_TXEN
, 2, 4, 15, 8, false)
446 MUX_CFG(DA850
, MII_TXCLK
, 2, 8, 15, 8, false)
447 MUX_CFG(DA850
, MII_COL
, 2, 12, 15, 8, false)
448 MUX_CFG(DA850
, MII_TXD_3
, 2, 16, 15, 8, false)
449 MUX_CFG(DA850
, MII_TXD_2
, 2, 20, 15, 8, false)
450 MUX_CFG(DA850
, MII_TXD_1
, 2, 24, 15, 8, false)
451 MUX_CFG(DA850
, MII_TXD_0
, 2, 28, 15, 8, false)
452 MUX_CFG(DA850
, MII_RXCLK
, 3, 0, 15, 8, false)
453 MUX_CFG(DA850
, MII_RXDV
, 3, 4, 15, 8, false)
454 MUX_CFG(DA850
, MII_RXER
, 3, 8, 15, 8, false)
455 MUX_CFG(DA850
, MII_CRS
, 3, 12, 15, 8, false)
456 MUX_CFG(DA850
, MII_RXD_3
, 3, 16, 15, 8, false)
457 MUX_CFG(DA850
, MII_RXD_2
, 3, 20, 15, 8, false)
458 MUX_CFG(DA850
, MII_RXD_1
, 3, 24, 15, 8, false)
459 MUX_CFG(DA850
, MII_RXD_0
, 3, 28, 15, 8, false)
460 MUX_CFG(DA850
, MDIO_CLK
, 4, 0, 15, 8, false)
461 MUX_CFG(DA850
, MDIO_D
, 4, 4, 15, 8, false)
462 MUX_CFG(DA850
, RMII_TXD_0
, 14, 12, 15, 8, false)
463 MUX_CFG(DA850
, RMII_TXD_1
, 14, 8, 15, 8, false)
464 MUX_CFG(DA850
, RMII_TXEN
, 14, 16, 15, 8, false)
465 MUX_CFG(DA850
, RMII_CRS_DV
, 15, 4, 15, 8, false)
466 MUX_CFG(DA850
, RMII_RXD_0
, 14, 24, 15, 8, false)
467 MUX_CFG(DA850
, RMII_RXD_1
, 14, 20, 15, 8, false)
468 MUX_CFG(DA850
, RMII_RXER
, 14, 28, 15, 8, false)
469 MUX_CFG(DA850
, RMII_MHZ_50_CLK
, 15, 0, 15, 0, false)
471 MUX_CFG(DA850
, ACLKR
, 0, 0, 15, 1, false)
472 MUX_CFG(DA850
, ACLKX
, 0, 4, 15, 1, false)
473 MUX_CFG(DA850
, AFSR
, 0, 8, 15, 1, false)
474 MUX_CFG(DA850
, AFSX
, 0, 12, 15, 1, false)
475 MUX_CFG(DA850
, AHCLKR
, 0, 16, 15, 1, false)
476 MUX_CFG(DA850
, AHCLKX
, 0, 20, 15, 1, false)
477 MUX_CFG(DA850
, AMUTE
, 0, 24, 15, 1, false)
478 MUX_CFG(DA850
, AXR_15
, 1, 0, 15, 1, false)
479 MUX_CFG(DA850
, AXR_14
, 1, 4, 15, 1, false)
480 MUX_CFG(DA850
, AXR_13
, 1, 8, 15, 1, false)
481 MUX_CFG(DA850
, AXR_12
, 1, 12, 15, 1, false)
482 MUX_CFG(DA850
, AXR_11
, 1, 16, 15, 1, false)
483 MUX_CFG(DA850
, AXR_10
, 1, 20, 15, 1, false)
484 MUX_CFG(DA850
, AXR_9
, 1, 24, 15, 1, false)
485 MUX_CFG(DA850
, AXR_8
, 1, 28, 15, 1, false)
486 MUX_CFG(DA850
, AXR_7
, 2, 0, 15, 1, false)
487 MUX_CFG(DA850
, AXR_6
, 2, 4, 15, 1, false)
488 MUX_CFG(DA850
, AXR_5
, 2, 8, 15, 1, false)
489 MUX_CFG(DA850
, AXR_4
, 2, 12, 15, 1, false)
490 MUX_CFG(DA850
, AXR_3
, 2, 16, 15, 1, false)
491 MUX_CFG(DA850
, AXR_2
, 2, 20, 15, 1, false)
492 MUX_CFG(DA850
, AXR_1
, 2, 24, 15, 1, false)
493 MUX_CFG(DA850
, AXR_0
, 2, 28, 15, 1, false)
495 MUX_CFG(DA850
, LCD_D_7
, 16, 8, 15, 2, false)
496 MUX_CFG(DA850
, LCD_D_6
, 16, 12, 15, 2, false)
497 MUX_CFG(DA850
, LCD_D_5
, 16, 16, 15, 2, false)
498 MUX_CFG(DA850
, LCD_D_4
, 16, 20, 15, 2, false)
499 MUX_CFG(DA850
, LCD_D_3
, 16, 24, 15, 2, false)
500 MUX_CFG(DA850
, LCD_D_2
, 16, 28, 15, 2, false)
501 MUX_CFG(DA850
, LCD_D_1
, 17, 0, 15, 2, false)
502 MUX_CFG(DA850
, LCD_D_0
, 17, 4, 15, 2, false)
503 MUX_CFG(DA850
, LCD_D_15
, 17, 8, 15, 2, false)
504 MUX_CFG(DA850
, LCD_D_14
, 17, 12, 15, 2, false)
505 MUX_CFG(DA850
, LCD_D_13
, 17, 16, 15, 2, false)
506 MUX_CFG(DA850
, LCD_D_12
, 17, 20, 15, 2, false)
507 MUX_CFG(DA850
, LCD_D_11
, 17, 24, 15, 2, false)
508 MUX_CFG(DA850
, LCD_D_10
, 17, 28, 15, 2, false)
509 MUX_CFG(DA850
, LCD_D_9
, 18, 0, 15, 2, false)
510 MUX_CFG(DA850
, LCD_D_8
, 18, 4, 15, 2, false)
511 MUX_CFG(DA850
, LCD_PCLK
, 18, 24, 15, 2, false)
512 MUX_CFG(DA850
, LCD_HSYNC
, 19, 0, 15, 2, false)
513 MUX_CFG(DA850
, LCD_VSYNC
, 19, 4, 15, 2, false)
514 MUX_CFG(DA850
, NLCD_AC_ENB_CS
, 19, 24, 15, 2, false)
515 /* MMC/SD0 function */
516 MUX_CFG(DA850
, MMCSD0_DAT_0
, 10, 8, 15, 2, false)
517 MUX_CFG(DA850
, MMCSD0_DAT_1
, 10, 12, 15, 2, false)
518 MUX_CFG(DA850
, MMCSD0_DAT_2
, 10, 16, 15, 2, false)
519 MUX_CFG(DA850
, MMCSD0_DAT_3
, 10, 20, 15, 2, false)
520 MUX_CFG(DA850
, MMCSD0_CLK
, 10, 0, 15, 2, false)
521 MUX_CFG(DA850
, MMCSD0_CMD
, 10, 4, 15, 2, false)
522 /* MMC/SD1 function */
523 MUX_CFG(DA850
, MMCSD1_DAT_0
, 18, 8, 15, 2, false)
524 MUX_CFG(DA850
, MMCSD1_DAT_1
, 19, 16, 15, 2, false)
525 MUX_CFG(DA850
, MMCSD1_DAT_2
, 19, 12, 15, 2, false)
526 MUX_CFG(DA850
, MMCSD1_DAT_3
, 19, 8, 15, 2, false)
527 MUX_CFG(DA850
, MMCSD1_CLK
, 18, 12, 15, 2, false)
528 MUX_CFG(DA850
, MMCSD1_CMD
, 18, 16, 15, 2, false)
529 /* EMIF2.5/EMIFA function */
530 MUX_CFG(DA850
, EMA_D_7
, 9, 0, 15, 1, false)
531 MUX_CFG(DA850
, EMA_D_6
, 9, 4, 15, 1, false)
532 MUX_CFG(DA850
, EMA_D_5
, 9, 8, 15, 1, false)
533 MUX_CFG(DA850
, EMA_D_4
, 9, 12, 15, 1, false)
534 MUX_CFG(DA850
, EMA_D_3
, 9, 16, 15, 1, false)
535 MUX_CFG(DA850
, EMA_D_2
, 9, 20, 15, 1, false)
536 MUX_CFG(DA850
, EMA_D_1
, 9, 24, 15, 1, false)
537 MUX_CFG(DA850
, EMA_D_0
, 9, 28, 15, 1, false)
538 MUX_CFG(DA850
, EMA_A_1
, 12, 24, 15, 1, false)
539 MUX_CFG(DA850
, EMA_A_2
, 12, 20, 15, 1, false)
540 MUX_CFG(DA850
, NEMA_CS_3
, 7, 4, 15, 1, false)
541 MUX_CFG(DA850
, NEMA_CS_4
, 7, 8, 15, 1, false)
542 MUX_CFG(DA850
, NEMA_WE
, 7, 16, 15, 1, false)
543 MUX_CFG(DA850
, NEMA_OE
, 7, 20, 15, 1, false)
544 MUX_CFG(DA850
, EMA_A_0
, 12, 28, 15, 1, false)
545 MUX_CFG(DA850
, EMA_A_3
, 12, 16, 15, 1, false)
546 MUX_CFG(DA850
, EMA_A_4
, 12, 12, 15, 1, false)
547 MUX_CFG(DA850
, EMA_A_5
, 12, 8, 15, 1, false)
548 MUX_CFG(DA850
, EMA_A_6
, 12, 4, 15, 1, false)
549 MUX_CFG(DA850
, EMA_A_7
, 12, 0, 15, 1, false)
550 MUX_CFG(DA850
, EMA_A_8
, 11, 28, 15, 1, false)
551 MUX_CFG(DA850
, EMA_A_9
, 11, 24, 15, 1, false)
552 MUX_CFG(DA850
, EMA_A_10
, 11, 20, 15, 1, false)
553 MUX_CFG(DA850
, EMA_A_11
, 11, 16, 15, 1, false)
554 MUX_CFG(DA850
, EMA_A_12
, 11, 12, 15, 1, false)
555 MUX_CFG(DA850
, EMA_A_13
, 11, 8, 15, 1, false)
556 MUX_CFG(DA850
, EMA_A_14
, 11, 4, 15, 1, false)
557 MUX_CFG(DA850
, EMA_A_15
, 11, 0, 15, 1, false)
558 MUX_CFG(DA850
, EMA_A_16
, 10, 28, 15, 1, false)
559 MUX_CFG(DA850
, EMA_A_17
, 10, 24, 15, 1, false)
560 MUX_CFG(DA850
, EMA_A_18
, 10, 20, 15, 1, false)
561 MUX_CFG(DA850
, EMA_A_19
, 10, 16, 15, 1, false)
562 MUX_CFG(DA850
, EMA_A_20
, 10, 12, 15, 1, false)
563 MUX_CFG(DA850
, EMA_A_21
, 10, 8, 15, 1, false)
564 MUX_CFG(DA850
, EMA_A_22
, 10, 4, 15, 1, false)
565 MUX_CFG(DA850
, EMA_A_23
, 10, 0, 15, 1, false)
566 MUX_CFG(DA850
, EMA_D_8
, 8, 28, 15, 1, false)
567 MUX_CFG(DA850
, EMA_D_9
, 8, 24, 15, 1, false)
568 MUX_CFG(DA850
, EMA_D_10
, 8, 20, 15, 1, false)
569 MUX_CFG(DA850
, EMA_D_11
, 8, 16, 15, 1, false)
570 MUX_CFG(DA850
, EMA_D_12
, 8, 12, 15, 1, false)
571 MUX_CFG(DA850
, EMA_D_13
, 8, 8, 15, 1, false)
572 MUX_CFG(DA850
, EMA_D_14
, 8, 4, 15, 1, false)
573 MUX_CFG(DA850
, EMA_D_15
, 8, 0, 15, 1, false)
574 MUX_CFG(DA850
, EMA_BA_1
, 5, 24, 15, 1, false)
575 MUX_CFG(DA850
, EMA_CLK
, 6, 0, 15, 1, false)
576 MUX_CFG(DA850
, EMA_WAIT_1
, 6, 24, 15, 1, false)
577 MUX_CFG(DA850
, NEMA_CS_2
, 7, 0, 15, 1, false)
579 MUX_CFG(DA850
, GPIO2_4
, 6, 12, 15, 8, false)
580 MUX_CFG(DA850
, GPIO2_6
, 6, 4, 15, 8, false)
581 MUX_CFG(DA850
, GPIO2_8
, 5, 28, 15, 8, false)
582 MUX_CFG(DA850
, GPIO2_15
, 5, 0, 15, 8, false)
583 MUX_CFG(DA850
, GPIO3_12
, 7, 12, 15, 8, false)
584 MUX_CFG(DA850
, GPIO3_13
, 7, 8, 15, 8, false)
585 MUX_CFG(DA850
, GPIO4_0
, 10, 28, 15, 8, false)
586 MUX_CFG(DA850
, GPIO4_1
, 10, 24, 15, 8, false)
587 MUX_CFG(DA850
, GPIO6_9
, 13, 24, 15, 8, false)
588 MUX_CFG(DA850
, GPIO6_10
, 13, 20, 15, 8, false)
589 MUX_CFG(DA850
, GPIO6_13
, 13, 8, 15, 8, false)
590 MUX_CFG(DA850
, RTC_ALARM
, 0, 28, 15, 2, false)
592 MUX_CFG(DA850
, VPIF_DIN0
, 15, 4, 15, 1, false)
593 MUX_CFG(DA850
, VPIF_DIN1
, 15, 0, 15, 1, false)
594 MUX_CFG(DA850
, VPIF_DIN2
, 14, 28, 15, 1, false)
595 MUX_CFG(DA850
, VPIF_DIN3
, 14, 24, 15, 1, false)
596 MUX_CFG(DA850
, VPIF_DIN4
, 14, 20, 15, 1, false)
597 MUX_CFG(DA850
, VPIF_DIN5
, 14, 16, 15, 1, false)
598 MUX_CFG(DA850
, VPIF_DIN6
, 14, 12, 15, 1, false)
599 MUX_CFG(DA850
, VPIF_DIN7
, 14, 8, 15, 1, false)
600 MUX_CFG(DA850
, VPIF_DIN8
, 16, 4, 15, 1, false)
601 MUX_CFG(DA850
, VPIF_DIN9
, 16, 0, 15, 1, false)
602 MUX_CFG(DA850
, VPIF_DIN10
, 15, 28, 15, 1, false)
603 MUX_CFG(DA850
, VPIF_DIN11
, 15, 24, 15, 1, false)
604 MUX_CFG(DA850
, VPIF_DIN12
, 15, 20, 15, 1, false)
605 MUX_CFG(DA850
, VPIF_DIN13
, 15, 16, 15, 1, false)
606 MUX_CFG(DA850
, VPIF_DIN14
, 15, 12, 15, 1, false)
607 MUX_CFG(DA850
, VPIF_DIN15
, 15, 8, 15, 1, false)
608 MUX_CFG(DA850
, VPIF_CLKIN0
, 14, 0, 15, 1, false)
609 MUX_CFG(DA850
, VPIF_CLKIN1
, 14, 4, 15, 1, false)
610 MUX_CFG(DA850
, VPIF_CLKIN2
, 19, 8, 15, 1, false)
611 MUX_CFG(DA850
, VPIF_CLKIN3
, 19, 16, 15, 1, false)
613 MUX_CFG(DA850
, VPIF_DOUT0
, 17, 4, 15, 1, false)
614 MUX_CFG(DA850
, VPIF_DOUT1
, 17, 0, 15, 1, false)
615 MUX_CFG(DA850
, VPIF_DOUT2
, 16, 28, 15, 1, false)
616 MUX_CFG(DA850
, VPIF_DOUT3
, 16, 24, 15, 1, false)
617 MUX_CFG(DA850
, VPIF_DOUT4
, 16, 20, 15, 1, false)
618 MUX_CFG(DA850
, VPIF_DOUT5
, 16, 16, 15, 1, false)
619 MUX_CFG(DA850
, VPIF_DOUT6
, 16, 12, 15, 1, false)
620 MUX_CFG(DA850
, VPIF_DOUT7
, 16, 8, 15, 1, false)
621 MUX_CFG(DA850
, VPIF_DOUT8
, 18, 4, 15, 1, false)
622 MUX_CFG(DA850
, VPIF_DOUT9
, 18, 0, 15, 1, false)
623 MUX_CFG(DA850
, VPIF_DOUT10
, 17, 28, 15, 1, false)
624 MUX_CFG(DA850
, VPIF_DOUT11
, 17, 24, 15, 1, false)
625 MUX_CFG(DA850
, VPIF_DOUT12
, 17, 20, 15, 1, false)
626 MUX_CFG(DA850
, VPIF_DOUT13
, 17, 16, 15, 1, false)
627 MUX_CFG(DA850
, VPIF_DOUT14
, 17, 12, 15, 1, false)
628 MUX_CFG(DA850
, VPIF_DOUT15
, 17, 8, 15, 1, false)
629 MUX_CFG(DA850
, VPIF_CLKO2
, 19, 12, 15, 1, false)
630 MUX_CFG(DA850
, VPIF_CLKO3
, 19, 20, 15, 1, false)
634 const short da850_i2c0_pins
[] __initconst
= {
635 DA850_I2C0_SDA
, DA850_I2C0_SCL
,
639 const short da850_i2c1_pins
[] __initconst
= {
640 DA850_I2C1_SCL
, DA850_I2C1_SDA
,
644 const short da850_lcdcntl_pins
[] __initconst
= {
645 DA850_LCD_D_0
, DA850_LCD_D_1
, DA850_LCD_D_2
, DA850_LCD_D_3
,
646 DA850_LCD_D_4
, DA850_LCD_D_5
, DA850_LCD_D_6
, DA850_LCD_D_7
,
647 DA850_LCD_D_8
, DA850_LCD_D_9
, DA850_LCD_D_10
, DA850_LCD_D_11
,
648 DA850_LCD_D_12
, DA850_LCD_D_13
, DA850_LCD_D_14
, DA850_LCD_D_15
,
649 DA850_LCD_PCLK
, DA850_LCD_HSYNC
, DA850_LCD_VSYNC
, DA850_NLCD_AC_ENB_CS
,
653 const short da850_vpif_capture_pins
[] __initdata
= {
654 DA850_VPIF_DIN0
, DA850_VPIF_DIN1
, DA850_VPIF_DIN2
, DA850_VPIF_DIN3
,
655 DA850_VPIF_DIN4
, DA850_VPIF_DIN5
, DA850_VPIF_DIN6
, DA850_VPIF_DIN7
,
656 DA850_VPIF_DIN8
, DA850_VPIF_DIN9
, DA850_VPIF_DIN10
, DA850_VPIF_DIN11
,
657 DA850_VPIF_DIN12
, DA850_VPIF_DIN13
, DA850_VPIF_DIN14
, DA850_VPIF_DIN15
,
658 DA850_VPIF_CLKIN0
, DA850_VPIF_CLKIN1
, DA850_VPIF_CLKIN2
,
663 const short da850_vpif_display_pins
[] __initdata
= {
664 DA850_VPIF_DOUT0
, DA850_VPIF_DOUT1
, DA850_VPIF_DOUT2
, DA850_VPIF_DOUT3
,
665 DA850_VPIF_DOUT4
, DA850_VPIF_DOUT5
, DA850_VPIF_DOUT6
, DA850_VPIF_DOUT7
,
666 DA850_VPIF_DOUT8
, DA850_VPIF_DOUT9
, DA850_VPIF_DOUT10
,
667 DA850_VPIF_DOUT11
, DA850_VPIF_DOUT12
, DA850_VPIF_DOUT13
,
668 DA850_VPIF_DOUT14
, DA850_VPIF_DOUT15
, DA850_VPIF_CLKO2
,
673 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
674 static u8 da850_default_priorities
[DA850_N_CP_INTC_IRQ
] = {
675 [IRQ_DA8XX_COMMTX
] = 7,
676 [IRQ_DA8XX_COMMRX
] = 7,
677 [IRQ_DA8XX_NINT
] = 7,
678 [IRQ_DA8XX_EVTOUT0
] = 7,
679 [IRQ_DA8XX_EVTOUT1
] = 7,
680 [IRQ_DA8XX_EVTOUT2
] = 7,
681 [IRQ_DA8XX_EVTOUT3
] = 7,
682 [IRQ_DA8XX_EVTOUT4
] = 7,
683 [IRQ_DA8XX_EVTOUT5
] = 7,
684 [IRQ_DA8XX_EVTOUT6
] = 7,
685 [IRQ_DA8XX_EVTOUT7
] = 7,
686 [IRQ_DA8XX_CCINT0
] = 7,
687 [IRQ_DA8XX_CCERRINT
] = 7,
688 [IRQ_DA8XX_TCERRINT0
] = 7,
689 [IRQ_DA8XX_AEMIFINT
] = 7,
690 [IRQ_DA8XX_I2CINT0
] = 7,
691 [IRQ_DA8XX_MMCSDINT0
] = 7,
692 [IRQ_DA8XX_MMCSDINT1
] = 7,
693 [IRQ_DA8XX_ALLINT0
] = 7,
695 [IRQ_DA8XX_SPINT0
] = 7,
696 [IRQ_DA8XX_TINT12_0
] = 7,
697 [IRQ_DA8XX_TINT34_0
] = 7,
698 [IRQ_DA8XX_TINT12_1
] = 7,
699 [IRQ_DA8XX_TINT34_1
] = 7,
700 [IRQ_DA8XX_UARTINT0
] = 7,
701 [IRQ_DA8XX_KEYMGRINT
] = 7,
702 [IRQ_DA850_MPUADDRERR0
] = 7,
703 [IRQ_DA8XX_CHIPINT0
] = 7,
704 [IRQ_DA8XX_CHIPINT1
] = 7,
705 [IRQ_DA8XX_CHIPINT2
] = 7,
706 [IRQ_DA8XX_CHIPINT3
] = 7,
707 [IRQ_DA8XX_TCERRINT1
] = 7,
708 [IRQ_DA8XX_C0_RX_THRESH_PULSE
] = 7,
709 [IRQ_DA8XX_C0_RX_PULSE
] = 7,
710 [IRQ_DA8XX_C0_TX_PULSE
] = 7,
711 [IRQ_DA8XX_C0_MISC_PULSE
] = 7,
712 [IRQ_DA8XX_C1_RX_THRESH_PULSE
] = 7,
713 [IRQ_DA8XX_C1_RX_PULSE
] = 7,
714 [IRQ_DA8XX_C1_TX_PULSE
] = 7,
715 [IRQ_DA8XX_C1_MISC_PULSE
] = 7,
716 [IRQ_DA8XX_MEMERR
] = 7,
717 [IRQ_DA8XX_GPIO0
] = 7,
718 [IRQ_DA8XX_GPIO1
] = 7,
719 [IRQ_DA8XX_GPIO2
] = 7,
720 [IRQ_DA8XX_GPIO3
] = 7,
721 [IRQ_DA8XX_GPIO4
] = 7,
722 [IRQ_DA8XX_GPIO5
] = 7,
723 [IRQ_DA8XX_GPIO6
] = 7,
724 [IRQ_DA8XX_GPIO7
] = 7,
725 [IRQ_DA8XX_GPIO8
] = 7,
726 [IRQ_DA8XX_I2CINT1
] = 7,
727 [IRQ_DA8XX_LCDINT
] = 7,
728 [IRQ_DA8XX_UARTINT1
] = 7,
729 [IRQ_DA8XX_MCASPINT
] = 7,
730 [IRQ_DA8XX_ALLINT1
] = 7,
731 [IRQ_DA8XX_SPINT1
] = 7,
732 [IRQ_DA8XX_UHPI_INT1
] = 7,
733 [IRQ_DA8XX_USB_INT
] = 7,
734 [IRQ_DA8XX_IRQN
] = 7,
735 [IRQ_DA8XX_RWAKEUP
] = 7,
736 [IRQ_DA8XX_UARTINT2
] = 7,
737 [IRQ_DA8XX_DFTSSINT
] = 7,
738 [IRQ_DA8XX_EHRPWM0
] = 7,
739 [IRQ_DA8XX_EHRPWM0TZ
] = 7,
740 [IRQ_DA8XX_EHRPWM1
] = 7,
741 [IRQ_DA8XX_EHRPWM1TZ
] = 7,
742 [IRQ_DA850_SATAINT
] = 7,
743 [IRQ_DA850_TINTALL_2
] = 7,
744 [IRQ_DA8XX_ECAP0
] = 7,
745 [IRQ_DA8XX_ECAP1
] = 7,
746 [IRQ_DA8XX_ECAP2
] = 7,
747 [IRQ_DA850_MMCSDINT0_1
] = 7,
748 [IRQ_DA850_MMCSDINT1_1
] = 7,
749 [IRQ_DA850_T12CMPINT0_2
] = 7,
750 [IRQ_DA850_T12CMPINT1_2
] = 7,
751 [IRQ_DA850_T12CMPINT2_2
] = 7,
752 [IRQ_DA850_T12CMPINT3_2
] = 7,
753 [IRQ_DA850_T12CMPINT4_2
] = 7,
754 [IRQ_DA850_T12CMPINT5_2
] = 7,
755 [IRQ_DA850_T12CMPINT6_2
] = 7,
756 [IRQ_DA850_T12CMPINT7_2
] = 7,
757 [IRQ_DA850_T12CMPINT0_3
] = 7,
758 [IRQ_DA850_T12CMPINT1_3
] = 7,
759 [IRQ_DA850_T12CMPINT2_3
] = 7,
760 [IRQ_DA850_T12CMPINT3_3
] = 7,
761 [IRQ_DA850_T12CMPINT4_3
] = 7,
762 [IRQ_DA850_T12CMPINT5_3
] = 7,
763 [IRQ_DA850_T12CMPINT6_3
] = 7,
764 [IRQ_DA850_T12CMPINT7_3
] = 7,
765 [IRQ_DA850_RPIINT
] = 7,
766 [IRQ_DA850_VPIFINT
] = 7,
767 [IRQ_DA850_CCINT1
] = 7,
768 [IRQ_DA850_CCERRINT1
] = 7,
769 [IRQ_DA850_TCERRINT2
] = 7,
770 [IRQ_DA850_TINTALL_3
] = 7,
771 [IRQ_DA850_MCBSP0RINT
] = 7,
772 [IRQ_DA850_MCBSP0XINT
] = 7,
773 [IRQ_DA850_MCBSP1RINT
] = 7,
774 [IRQ_DA850_MCBSP1XINT
] = 7,
775 [IRQ_DA8XX_ARMCLKSTOPREQ
] = 7,
778 static struct map_desc da850_io_desc
[] = {
781 .pfn
= __phys_to_pfn(IO_PHYS
),
786 .virtual = DA8XX_CP_INTC_VIRT
,
787 .pfn
= __phys_to_pfn(DA8XX_CP_INTC_BASE
),
788 .length
= DA8XX_CP_INTC_SIZE
,
793 static u32 da850_psc_bases
[] = { DA8XX_PSC0_BASE
, DA8XX_PSC1_BASE
};
795 /* Contents of JTAG ID register used to identify exact cpu type */
796 static struct davinci_id da850_ids
[] = {
800 .manufacturer
= 0x017, /* 0x02f >> 1 */
801 .cpu_id
= DAVINCI_CPU_ID_DA850
,
802 .name
= "da850/omap-l138",
807 .manufacturer
= 0x017, /* 0x02f >> 1 */
808 .cpu_id
= DAVINCI_CPU_ID_DA850
,
809 .name
= "da850/omap-l138/am18x",
813 static struct davinci_timer_instance da850_timer_instance
[4] = {
815 .base
= DA8XX_TIMER64P0_BASE
,
816 .bottom_irq
= IRQ_DA8XX_TINT12_0
,
817 .top_irq
= IRQ_DA8XX_TINT34_0
,
820 .base
= DA8XX_TIMER64P1_BASE
,
821 .bottom_irq
= IRQ_DA8XX_TINT12_1
,
822 .top_irq
= IRQ_DA8XX_TINT34_1
,
825 .base
= DA850_TIMER64P2_BASE
,
826 .bottom_irq
= IRQ_DA850_TINT12_2
,
827 .top_irq
= IRQ_DA850_TINT34_2
,
830 .base
= DA850_TIMER64P3_BASE
,
831 .bottom_irq
= IRQ_DA850_TINT12_3
,
832 .top_irq
= IRQ_DA850_TINT34_3
,
837 * T0_BOT: Timer 0, bottom : Used for clock_event
838 * T0_TOP: Timer 0, top : Used for clocksource
839 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
841 static struct davinci_timer_info da850_timer_info
= {
842 .timers
= da850_timer_instance
,
843 .clockevent_id
= T0_BOT
,
844 .clocksource_id
= T0_TOP
,
847 static void da850_set_async3_src(int pllnum
)
849 struct clk
*clk
, *newparent
= pllnum
? &pll1_sysclk2
: &pll0_sysclk2
;
850 struct clk_lookup
*c
;
854 for (c
= da850_clks
; c
->clk
; c
++) {
856 if (clk
->flags
& DA850_CLK_ASYNC3
) {
857 ret
= clk_set_parent(clk
, newparent
);
858 WARN(ret
, "DA850: unable to re-parent clock %s",
863 v
= __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG
));
865 v
|= CFGCHIP3_ASYNC3_CLKSRC
;
867 v
&= ~CFGCHIP3_ASYNC3_CLKSRC
;
868 __raw_writel(v
, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG
));
871 #ifdef CONFIG_CPU_FREQ
874 * According to the TRM, minimum PLLM results in maximum power savings.
875 * The OPP definitions below should keep the PLLM as low as possible.
877 * The output of the PLLM must be between 300 to 600 MHz.
880 unsigned int freq
; /* in KHz */
883 unsigned int postdiv
;
884 unsigned int cvdd_min
; /* in uV */
885 unsigned int cvdd_max
; /* in uV */
888 static const struct da850_opp da850_opp_456
= {
897 static const struct da850_opp da850_opp_408
= {
906 static const struct da850_opp da850_opp_372
= {
915 static const struct da850_opp da850_opp_300
= {
924 static const struct da850_opp da850_opp_200
= {
933 static const struct da850_opp da850_opp_96
= {
944 .index = (unsigned int) &da850_opp_##freq, \
945 .frequency = freq * 1000, \
948 static struct cpufreq_frequency_table da850_freq_table
[] = {
957 .frequency
= CPUFREQ_TABLE_END
,
961 #ifdef CONFIG_REGULATOR
962 static int da850_set_voltage(unsigned int index
);
963 static int da850_regulator_init(void);
966 static struct davinci_cpufreq_config cpufreq_info
= {
967 .freq_table
= da850_freq_table
,
968 #ifdef CONFIG_REGULATOR
969 .init
= da850_regulator_init
,
970 .set_voltage
= da850_set_voltage
,
974 #ifdef CONFIG_REGULATOR
975 static struct regulator
*cvdd
;
977 static int da850_set_voltage(unsigned int index
)
979 struct da850_opp
*opp
;
984 opp
= (struct da850_opp
*) cpufreq_info
.freq_table
[index
].index
;
986 return regulator_set_voltage(cvdd
, opp
->cvdd_min
, opp
->cvdd_max
);
989 static int da850_regulator_init(void)
991 cvdd
= regulator_get(NULL
, "cvdd");
992 if (WARN(IS_ERR(cvdd
), "Unable to obtain voltage regulator for CVDD;"
993 " voltage scaling unsupported\n")) {
994 return PTR_ERR(cvdd
);
1001 static struct platform_device da850_cpufreq_device
= {
1002 .name
= "cpufreq-davinci",
1004 .platform_data
= &cpufreq_info
,
1009 unsigned int da850_max_speed
= 300000;
1011 int da850_register_cpufreq(char *async_clk
)
1015 /* cpufreq driver can help keep an "async" clock constant */
1017 clk_add_alias("async", da850_cpufreq_device
.name
,
1019 for (i
= 0; i
< ARRAY_SIZE(da850_freq_table
); i
++) {
1020 if (da850_freq_table
[i
].frequency
<= da850_max_speed
) {
1021 cpufreq_info
.freq_table
= &da850_freq_table
[i
];
1026 return platform_device_register(&da850_cpufreq_device
);
1029 static int da850_round_armrate(struct clk
*clk
, unsigned long rate
)
1031 int i
, ret
= 0, diff
;
1032 unsigned int best
= (unsigned int) -1;
1033 struct cpufreq_frequency_table
*table
= cpufreq_info
.freq_table
;
1035 rate
/= 1000; /* convert to kHz */
1037 for (i
= 0; table
[i
].frequency
!= CPUFREQ_TABLE_END
; i
++) {
1038 diff
= table
[i
].frequency
- rate
;
1044 ret
= table
[i
].frequency
;
1051 static int da850_set_armrate(struct clk
*clk
, unsigned long index
)
1053 struct clk
*pllclk
= &pll0_clk
;
1055 return clk_set_rate(pllclk
, index
);
1058 static int da850_set_pll0rate(struct clk
*clk
, unsigned long index
)
1060 unsigned int prediv
, mult
, postdiv
;
1061 struct da850_opp
*opp
;
1062 struct pll_data
*pll
= clk
->pll_data
;
1065 opp
= (struct da850_opp
*) cpufreq_info
.freq_table
[index
].index
;
1066 prediv
= opp
->prediv
;
1068 postdiv
= opp
->postdiv
;
1070 ret
= davinci_set_pllrate(pll
, prediv
, mult
, postdiv
);
1077 int __init
da850_register_cpufreq(char *async_clk
)
1082 static int da850_set_armrate(struct clk
*clk
, unsigned long rate
)
1087 static int da850_set_pll0rate(struct clk
*clk
, unsigned long armrate
)
1092 static int da850_round_armrate(struct clk
*clk
, unsigned long rate
)
1098 int __init
da850_register_pm(struct platform_device
*pdev
)
1101 struct davinci_pm_config
*pdata
= pdev
->dev
.platform_data
;
1103 ret
= davinci_cfg_reg(DA850_RTC_ALARM
);
1107 pdata
->ddr2_ctlr_base
= da8xx_get_mem_ctlr();
1108 pdata
->deepsleep_reg
= DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG
);
1109 pdata
->ddrpsc_num
= DA8XX_LPSC1_EMIF3C
;
1111 pdata
->cpupll_reg_base
= ioremap(DA8XX_PLL0_BASE
, SZ_4K
);
1112 if (!pdata
->cpupll_reg_base
)
1115 pdata
->ddrpll_reg_base
= ioremap(DA850_PLL1_BASE
, SZ_4K
);
1116 if (!pdata
->ddrpll_reg_base
) {
1121 pdata
->ddrpsc_reg_base
= ioremap(DA8XX_PSC1_BASE
, SZ_4K
);
1122 if (!pdata
->ddrpsc_reg_base
) {
1127 return platform_device_register(pdev
);
1130 iounmap(pdata
->ddrpll_reg_base
);
1132 iounmap(pdata
->cpupll_reg_base
);
1136 /* VPIF resource, platform data */
1137 static u64 da850_vpif_dma_mask
= DMA_BIT_MASK(32);
1139 static struct resource da850_vpif_resource
[] = {
1141 .start
= DA8XX_VPIF_BASE
,
1142 .end
= DA8XX_VPIF_BASE
+ 0xfff,
1143 .flags
= IORESOURCE_MEM
,
1147 static struct platform_device da850_vpif_dev
= {
1151 .dma_mask
= &da850_vpif_dma_mask
,
1152 .coherent_dma_mask
= DMA_BIT_MASK(32),
1154 .resource
= da850_vpif_resource
,
1155 .num_resources
= ARRAY_SIZE(da850_vpif_resource
),
1158 static struct resource da850_vpif_display_resource
[] = {
1160 .start
= IRQ_DA850_VPIFINT
,
1161 .end
= IRQ_DA850_VPIFINT
,
1162 .flags
= IORESOURCE_IRQ
,
1166 static struct platform_device da850_vpif_display_dev
= {
1167 .name
= "vpif_display",
1170 .dma_mask
= &da850_vpif_dma_mask
,
1171 .coherent_dma_mask
= DMA_BIT_MASK(32),
1173 .resource
= da850_vpif_display_resource
,
1174 .num_resources
= ARRAY_SIZE(da850_vpif_display_resource
),
1177 static struct resource da850_vpif_capture_resource
[] = {
1179 .start
= IRQ_DA850_VPIFINT
,
1180 .end
= IRQ_DA850_VPIFINT
,
1181 .flags
= IORESOURCE_IRQ
,
1184 .start
= IRQ_DA850_VPIFINT
,
1185 .end
= IRQ_DA850_VPIFINT
,
1186 .flags
= IORESOURCE_IRQ
,
1190 static struct platform_device da850_vpif_capture_dev
= {
1191 .name
= "vpif_capture",
1194 .dma_mask
= &da850_vpif_dma_mask
,
1195 .coherent_dma_mask
= DMA_BIT_MASK(32),
1197 .resource
= da850_vpif_capture_resource
,
1198 .num_resources
= ARRAY_SIZE(da850_vpif_capture_resource
),
1201 int __init
da850_register_vpif(void)
1203 return platform_device_register(&da850_vpif_dev
);
1206 int __init
da850_register_vpif_display(struct vpif_display_config
1209 da850_vpif_display_dev
.dev
.platform_data
= display_config
;
1210 return platform_device_register(&da850_vpif_display_dev
);
1213 int __init
da850_register_vpif_capture(struct vpif_capture_config
1216 da850_vpif_capture_dev
.dev
.platform_data
= capture_config
;
1217 return platform_device_register(&da850_vpif_capture_dev
);
1220 static struct davinci_soc_info davinci_soc_info_da850
= {
1221 .io_desc
= da850_io_desc
,
1222 .io_desc_num
= ARRAY_SIZE(da850_io_desc
),
1223 .jtag_id_reg
= DA8XX_SYSCFG0_BASE
+ DA8XX_JTAG_ID_REG
,
1225 .ids_num
= ARRAY_SIZE(da850_ids
),
1226 .cpu_clks
= da850_clks
,
1227 .psc_bases
= da850_psc_bases
,
1228 .psc_bases_num
= ARRAY_SIZE(da850_psc_bases
),
1229 .pinmux_base
= DA8XX_SYSCFG0_BASE
+ 0x120,
1230 .pinmux_pins
= da850_pins
,
1231 .pinmux_pins_num
= ARRAY_SIZE(da850_pins
),
1232 .intc_base
= DA8XX_CP_INTC_BASE
,
1233 .intc_type
= DAVINCI_INTC_TYPE_CP_INTC
,
1234 .intc_irq_prios
= da850_default_priorities
,
1235 .intc_irq_num
= DA850_N_CP_INTC_IRQ
,
1236 .timer_info
= &da850_timer_info
,
1237 .gpio_type
= GPIO_TYPE_DAVINCI
,
1238 .gpio_base
= DA8XX_GPIO_BASE
,
1240 .gpio_irq
= IRQ_DA8XX_GPIO0
,
1241 .serial_dev
= &da8xx_serial_device
,
1242 .emac_pdata
= &da8xx_emac_pdata
,
1243 .sram_dma
= DA8XX_SHARED_RAM_BASE
,
1244 .sram_len
= SZ_128K
,
1247 void __init
da850_init(void)
1251 davinci_common_init(&davinci_soc_info_da850
);
1253 da8xx_syscfg0_base
= ioremap(DA8XX_SYSCFG0_BASE
, SZ_4K
);
1254 if (WARN(!da8xx_syscfg0_base
, "Unable to map syscfg0 module"))
1257 da8xx_syscfg1_base
= ioremap(DA8XX_SYSCFG1_BASE
, SZ_4K
);
1258 if (WARN(!da8xx_syscfg1_base
, "Unable to map syscfg1 module"))
1262 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1263 * This helps keeping the peripherals on this domain insulated
1264 * from CPU frequency changes caused by DVFS. The firmware sets
1265 * both PLL0 and PLL1 to the same frequency so, there should not
1266 * be any noticeable change even in non-DVFS use cases.
1268 da850_set_async3_src(1);
1270 /* Unlock writing to PLL0 registers */
1271 v
= __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG
));
1272 v
&= ~CFGCHIP0_PLL_MASTER_LOCK
;
1273 __raw_writel(v
, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG
));
1275 /* Unlock writing to PLL1 registers */
1276 v
= __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG
));
1277 v
&= ~CFGCHIP3_PLL1_MASTER_LOCK
;
1278 __raw_writel(v
, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG
));