arch/arm/mach-davinci/gpio.c

   1 /*
   2  * TI DaVinci GPIO Support
   3  *
   4  * Copyright (c) 2006-2007 David Brownell
   5  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/errno.h>
  14 #include <linux/kernel.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18
  19 #include <mach/gpio.h>
  20
  21 #include <asm/mach/irq.h>
  22
  23 struct davinci_gpio_regs {
  24         u32     dir;
  25         u32     out_data;
  26         u32     set_data;
  27         u32     clr_data;
  28         u32     in_data;
  29         u32     set_rising;
  30         u32     clr_rising;
  31         u32     set_falling;
  32         u32     clr_falling;
  33         u32     intstat;
  34 };
  35
  36 static DEFINE_SPINLOCK(gpio_lock);
  37
  38 #define chip2controller(chip)   \
  39         container_of(chip, struct davinci_gpio_controller, chip)
  40
  41 static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
  42
  43 static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
  44 {
  45         void __iomem *ptr;
  46         void __iomem *base = davinci_soc_info.gpio_base;
  47
  48         if (gpio < 32 * 1)
  49                 ptr = base + 0x10;
  50         else if (gpio < 32 * 2)
  51                 ptr = base + 0x38;
  52         else if (gpio < 32 * 3)
  53                 ptr = base + 0x60;
  54         else if (gpio < 32 * 4)
  55                 ptr = base + 0x88;
  56         else if (gpio < 32 * 5)
  57                 ptr = base + 0xb0;
  58         else
  59                 ptr = NULL;
  60         return ptr;
  61 }
  62
  63 static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
  64 {
  65         struct davinci_gpio_regs __iomem *g;
  66
  67         g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
  68
  69         return g;
  70 }
  71
  72 static int __init davinci_gpio_irq_setup(void);
  73
  74 /*--------------------------------------------------------------------------*/
  75
  76 /*
  77  * board setup code *MUST* set PINMUX0 and PINMUX1 as
  78  * needed, and enable the GPIO clock.
  79  */
  80
  81 static inline int __davinci_direction(struct gpio_chip *chip,
  82                         unsigned offset, bool out, int value)
  83 {
  84         struct davinci_gpio_controller *d = chip2controller(chip);
  85         struct davinci_gpio_regs __iomem *g = d->regs;
  86         u32 temp;
  87         u32 mask = 1 << offset;
  88
  89         spin_lock(&gpio_lock);
  90         temp = __raw_readl(&g->dir);
  91         if (out) {
  92                 temp &= ~mask;
  93                 __raw_writel(mask, value ? &g->set_data : &g->clr_data);
  94         } else {
  95                 temp |= mask;
  96         }
  97         __raw_writel(temp, &g->dir);
  98         spin_unlock(&gpio_lock);
  99
 100         return 0;
 101 }
 102
 103 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
 104 {
 105         return __davinci_direction(chip, offset, false, 0);
 106 }
 107
 108 static int
 109 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
 110 {
 111         return __davinci_direction(chip, offset, true, value);
 112 }
 113
 114 /*
 115  * Read the pin's value (works even if it's set up as output);
 116  * returns zero/nonzero.
 117  *
 118  * Note that changes are synched to the GPIO clock, so reading values back
 119  * right after you've set them may give old values.
 120  */
 121 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 122 {
 123         struct davinci_gpio_controller *d = chip2controller(chip);
 124         struct davinci_gpio_regs __iomem *g = d->regs;
 125
 126         return (1 << offset) & __raw_readl(&g->in_data);
 127 }
 128
 129 /*
 130  * Assuming the pin is muxed as a gpio output, set its output value.
 131  */
 132 static void
 133 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 134 {
 135         struct davinci_gpio_controller *d = chip2controller(chip);
 136         struct davinci_gpio_regs __iomem *g = d->regs;
 137
 138         __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
 139 }
 140
 141 static int __init davinci_gpio_setup(void)
 142 {
 143         int i, base;
 144         unsigned ngpio;
 145         struct davinci_soc_info *soc_info = &davinci_soc_info;
 146         struct davinci_gpio_regs *regs;
 147
 148         if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
 149                 return 0;
 150
 151         /*
 152          * The gpio banks conceptually expose a segmented bitmap,
 153          * and "ngpio" is one more than the largest zero-based
 154          * bit index that's valid.
 155          */
 156         ngpio = soc_info->gpio_num;
 157         if (ngpio == 0) {
 158                 pr_err("GPIO setup:  how many GPIOs?\n");
 159                 return -EINVAL;
 160         }
 161
 162         if (WARN_ON(DAVINCI_N_GPIO < ngpio))
 163                 ngpio = DAVINCI_N_GPIO;
 164
 165         for (i = 0, base = 0; base < ngpio; i++, base += 32) {
 166                 chips[i].chip.label = "DaVinci";
 167
 168                 chips[i].chip.direction_input = davinci_direction_in;
 169                 chips[i].chip.get = davinci_gpio_get;
 170                 chips[i].chip.direction_output = davinci_direction_out;
 171                 chips[i].chip.set = davinci_gpio_set;
 172
 173                 chips[i].chip.base = base;
 174                 chips[i].chip.ngpio = ngpio - base;
 175                 if (chips[i].chip.ngpio > 32)
 176                         chips[i].chip.ngpio = 32;
 177
 178                 regs = gpio2regs(base);
 179                 chips[i].regs = regs;
 180                 chips[i].set_data = &regs->set_data;
 181                 chips[i].clr_data = &regs->clr_data;
 182                 chips[i].in_data = &regs->in_data;
 183
 184                 gpiochip_add(&chips[i].chip);
 185         }
 186
 187         soc_info->gpio_ctlrs = chips;
 188         soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
 189
 190         davinci_gpio_irq_setup();
 191         return 0;
 192 }
 193 pure_initcall(davinci_gpio_setup);
 194
 195 /*--------------------------------------------------------------------------*/
 196 /*
 197  * We expect irqs will normally be set up as input pins, but they can also be
 198  * used as output pins ... which is convenient for testing.
 199  *
 200  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 201  * to their GPIOBNK0 irq, with a bit less overhead.
 202  *
 203  * All those INTC hookups (direct, plus several IRQ banks) can also
 204  * serve as EDMA event triggers.
 205  */
 206
 207 static void gpio_irq_disable(unsigned irq)
 208 {
 209         struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 210         u32 mask = (u32) get_irq_data(irq);
 211
 212         __raw_writel(mask, &g->clr_falling);
 213         __raw_writel(mask, &g->clr_rising);
 214 }
 215
 216 static void gpio_irq_enable(unsigned irq)
 217 {
 218         struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 219         u32 mask = (u32) get_irq_data(irq);
 220         unsigned status = irq_desc[irq].status;
 221
 222         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 223         if (!status)
 224                 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
 225
 226         if (status & IRQ_TYPE_EDGE_FALLING)
 227                 __raw_writel(mask, &g->set_falling);
 228         if (status & IRQ_TYPE_EDGE_RISING)
 229                 __raw_writel(mask, &g->set_rising);
 230 }
 231
 232 static int gpio_irq_type(unsigned irq, unsigned trigger)
 233 {
 234         struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 235         u32 mask = (u32) get_irq_data(irq);
 236
 237         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 238                 return -EINVAL;
 239
 240         irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
 241         irq_desc[irq].status |= trigger;
 242
 243         /* don't enable the IRQ if it's currently disabled */
 244         if (irq_desc[irq].depth == 0) {
 245                 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
 246                              ? &g->set_falling : &g->clr_falling);
 247                 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
 248                              ? &g->set_rising : &g->clr_rising);
 249         }
 250         return 0;
 251 }
 252
 253 static struct irq_chip gpio_irqchip = {
 254         .name           = "GPIO",
 255         .enable         = gpio_irq_enable,
 256         .disable        = gpio_irq_disable,
 257         .set_type       = gpio_irq_type,
 258 };
 259
 260 static void
 261 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 262 {
 263         struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 264         u32 mask = 0xffff;
 265
 266         /* we only care about one bank */
 267         if (irq & 1)
 268                 mask <<= 16;
 269
 270         /* temporarily mask (level sensitive) parent IRQ */
 271         desc->chip->mask(irq);
 272         desc->chip->ack(irq);
 273         while (1) {
 274                 u32             status;
 275                 int             n;
 276                 int             res;
 277
 278                 /* ack any irqs */
 279                 status = __raw_readl(&g->intstat) & mask;
 280                 if (!status)
 281                         break;
 282                 __raw_writel(status, &g->intstat);
 283                 if (irq & 1)
 284                         status >>= 16;
 285
 286                 /* now demux them to the right lowlevel handler */
 287                 n = (int)get_irq_data(irq);
 288                 while (status) {
 289                         res = ffs(status);
 290                         n += res;
 291                         generic_handle_irq(n - 1);
 292                         status >>= res;
 293                 }
 294         }
 295         desc->chip->unmask(irq);
 296         /* now it may re-trigger */
 297 }
 298
 299 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
 300 {
 301         struct davinci_gpio_controller *d = chip2controller(chip);
 302
 303         if (d->irq_base >= 0)
 304                 return d->irq_base + offset;
 305         else
 306                 return -ENODEV;
 307 }
 308
 309 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 310 {
 311         struct davinci_soc_info *soc_info = &davinci_soc_info;
 312
 313         /* NOTE:  we assume for now that only irqs in the first gpio_chip
 314          * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
 315          */
 316         if (offset < soc_info->gpio_unbanked)
 317                 return soc_info->gpio_irq + offset;
 318         else
 319                 return -ENODEV;
 320 }
 321
 322 static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
 323 {
 324         struct davinci_gpio_regs __iomem *g = irq2regs(irq);
 325         u32 mask = (u32) get_irq_data(irq);
 326
 327         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 328                 return -EINVAL;
 329
 330         __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
 331                      ? &g->set_falling : &g->clr_falling);
 332         __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
 333                      ? &g->set_rising : &g->clr_rising);
 334
 335         return 0;
 336 }
 337
 338 /*
 339  * NOTE:  for suspend/resume, probably best to make a platform_device with
 340  * suspend_late/resume_resume calls hooking into results of the set_wake()
 341  * calls ... so if no gpios are wakeup events the clock can be disabled,
 342  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 343  * (dm6446) can be set appropriately for GPIOV33 pins.
 344  */
 345
 346 static int __init davinci_gpio_irq_setup(void)
 347 {
 348         unsigned        gpio, irq, bank;
 349         struct clk      *clk;
 350         u32             binten = 0;
 351         unsigned        ngpio, bank_irq;
 352         struct davinci_soc_info *soc_info = &davinci_soc_info;
 353         struct davinci_gpio_regs        __iomem *g;
 354
 355         ngpio = soc_info->gpio_num;
 356
 357         bank_irq = soc_info->gpio_irq;
 358         if (bank_irq == 0) {
 359                 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
 360                 return -EINVAL;
 361         }
 362
 363         clk = clk_get(NULL, "gpio");
 364         if (IS_ERR(clk)) {
 365                 printk(KERN_ERR "Error %ld getting gpio clock?\n",
 366                        PTR_ERR(clk));
 367                 return PTR_ERR(clk);
 368         }
 369         clk_enable(clk);
 370
 371         /* Arrange gpio_to_irq() support, handling either direct IRQs or
 372          * banked IRQs.  Having GPIOs in the first GPIO bank use direct
 373          * IRQs, while the others use banked IRQs, would need some setup
 374          * tweaks to recognize hardware which can do that.
 375          */
 376         for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
 377                 chips[bank].chip.to_irq = gpio_to_irq_banked;
 378                 chips[bank].irq_base = soc_info->gpio_unbanked
 379                         ? -EINVAL
 380                         : (soc_info->intc_irq_num + gpio);
 381         }
 382
 383         /*
 384          * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
 385          * controller only handling trigger modes.  We currently assume no
 386          * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
 387          */
 388         if (soc_info->gpio_unbanked) {
 389                 static struct irq_chip gpio_irqchip_unbanked;
 390
 391                 /* pass "bank 0" GPIO IRQs to AINTC */
 392                 chips[0].chip.to_irq = gpio_to_irq_unbanked;
 393                 binten = BIT(0);
 394
 395                 /* AINTC handles mask/unmask; GPIO handles triggering */
 396                 irq = bank_irq;
 397                 gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
 398                 gpio_irqchip_unbanked.name = "GPIO-AINTC";
 399                 gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
 400
 401                 /* default trigger: both edges */
 402                 g = gpio2regs(0);
 403                 __raw_writel(~0, &g->set_falling);
 404                 __raw_writel(~0, &g->set_rising);
 405
 406                 /* set the direct IRQs up to use that irqchip */
 407                 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
 408                         set_irq_chip(irq, &gpio_irqchip_unbanked);
 409                         set_irq_data(irq, (void *) __gpio_mask(gpio));
 410                         set_irq_chip_data(irq, (__force void *) g);
 411                         irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
 412                 }
 413
 414                 goto done;
 415         }
 416
 417         /*
 418          * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
 419          * then chain through our own handler.
 420          */
 421         for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
 422                         gpio < ngpio;
 423                         bank++, bank_irq++) {
 424                 unsigned                i;
 425
 426                 /* disabled by default, enabled only as needed */
 427                 g = gpio2regs(gpio);
 428                 __raw_writel(~0, &g->clr_falling);
 429                 __raw_writel(~0, &g->clr_rising);
 430
 431                 /* set up all irqs in this bank */
 432                 set_irq_chained_handler(bank_irq, gpio_irq_handler);
 433                 set_irq_chip_data(bank_irq, (__force void *) g);
 434                 set_irq_data(bank_irq, (void *) irq);
 435
 436                 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
 437                         set_irq_chip(irq, &gpio_irqchip);
 438                         set_irq_chip_data(irq, (__force void *) g);
 439                         set_irq_data(irq, (void *) __gpio_mask(gpio));
 440                         set_irq_handler(irq, handle_simple_irq);
 441                         set_irq_flags(irq, IRQF_VALID);
 442                 }
 443
 444                 binten |= BIT(bank);
 445         }
 446
 447 done:
 448         /* BINTEN -- per-bank interrupt enable. genirq would also let these
 449          * bits be set/cleared dynamically.
 450          */
 451         __raw_writel(binten, soc_info->gpio_base + 0x08);
 452
 453         printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
 454
 455         return 0;
 456 }