arch/arm/mach-dove/common.c

   1 /*
   2  * arch/arm/mach-dove/common.c
   3  *
   4  * Core functions for Marvell Dove 88AP510 System On Chip
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/init.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pci.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/ata_platform.h>
  18 #include <linux/gpio.h>
  19 #include <linux/of.h>
  20 #include <linux/of_platform.h>
  21 #include <asm/page.h>
  22 #include <asm/setup.h>
  23 #include <asm/timex.h>
  24 #include <asm/hardware/cache-tauros2.h>
  25 #include <asm/mach/map.h>
  26 #include <asm/mach/time.h>
  27 #include <asm/mach/pci.h>
  28 #include <mach/dove.h>
  29 #include <mach/pm.h>
  30 #include <mach/bridge-regs.h>
  31 #include <asm/mach/arch.h>
  32 #include <linux/irq.h>
  33 #include <plat/time.h>
  34 #include <plat/irq.h>
  35 #include <plat/ehci-orion.h>
  36 #include <plat/common.h>
  37 #include <plat/addr-map.h>
  38 #include "common.h"
  39
  40 /*****************************************************************************
  41  * I/O Address Mapping
  42  ****************************************************************************/
  43 static struct map_desc dove_io_desc[] __initdata = {
  44         {
  45                 .virtual        = DOVE_SB_REGS_VIRT_BASE,
  46                 .pfn            = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
  47                 .length         = DOVE_SB_REGS_SIZE,
  48                 .type           = MT_DEVICE,
  49         }, {
  50                 .virtual        = DOVE_NB_REGS_VIRT_BASE,
  51                 .pfn            = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
  52                 .length         = DOVE_NB_REGS_SIZE,
  53                 .type           = MT_DEVICE,
  54         }, {
  55                 .virtual        = DOVE_PCIE0_IO_VIRT_BASE,
  56                 .pfn            = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
  57                 .length         = DOVE_PCIE0_IO_SIZE,
  58                 .type           = MT_DEVICE,
  59         }, {
  60                 .virtual        = DOVE_PCIE1_IO_VIRT_BASE,
  61                 .pfn            = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
  62                 .length         = DOVE_PCIE1_IO_SIZE,
  63                 .type           = MT_DEVICE,
  64         },
  65 };
  66
  67 void __init dove_map_io(void)
  68 {
  69         iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
  70 }
  71
  72 /*****************************************************************************
  73  * CLK tree
  74  ****************************************************************************/
  75 static int dove_tclk;
  76
  77 static DEFINE_SPINLOCK(gating_lock);
  78 static struct clk *tclk;
  79
  80 static struct clk __init *dove_register_gate(const char *name,
  81                                              const char *parent, u8 bit_idx)
  82 {
  83         return clk_register_gate(NULL, name, parent, 0,
  84                                  (void __iomem *)CLOCK_GATING_CONTROL,
  85                                  bit_idx, 0, &gating_lock);
  86 }
  87
  88 static void __init dove_clk_init(void)
  89 {
  90         struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
  91         struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
  92         struct clk *xor0, *xor1, *ge, *gephy;
  93
  94         tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
  95                                        dove_tclk);
  96
  97         usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
  98         usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
  99         sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
 100         pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
 101         pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
 102         sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
 103         sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
 104         nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
 105         camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
 106         i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
 107         i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
 108         crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
 109         ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
 110         pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
 111         xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
 112         xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
 113         gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
 114         ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
 115
 116         orion_clkdev_add(NULL, "orion_spi.0", tclk);
 117         orion_clkdev_add(NULL, "orion_spi.1", tclk);
 118         orion_clkdev_add(NULL, "orion_wdt", tclk);
 119         orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
 120
 121         orion_clkdev_add(NULL, "orion-ehci.0", usb0);
 122         orion_clkdev_add(NULL, "orion-ehci.1", usb1);
 123         orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
 124         orion_clkdev_add("0", "sata_mv.0", sata);
 125         orion_clkdev_add("0", "pcie", pex0);
 126         orion_clkdev_add("1", "pcie", pex1);
 127         orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
 128         orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
 129         orion_clkdev_add(NULL, "orion_nand", nand);
 130         orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
 131         orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
 132         orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
 133         orion_clkdev_add(NULL, "mv_crypto", crypto);
 134         orion_clkdev_add(NULL, "dove-ac97", ac97);
 135         orion_clkdev_add(NULL, "dove-pdma", pdma);
 136         orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
 137         orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
 138 }
 139
 140 /*****************************************************************************
 141  * EHCI0
 142  ****************************************************************************/
 143 void __init dove_ehci0_init(void)
 144 {
 145         orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
 146 }
 147
 148 /*****************************************************************************
 149  * EHCI1
 150  ****************************************************************************/
 151 void __init dove_ehci1_init(void)
 152 {
 153         orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
 154 }
 155
 156 /*****************************************************************************
 157  * GE00
 158  ****************************************************************************/
 159 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 160 {
 161         orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
 162                         IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
 163                         1600);
 164 }
 165
 166 /*****************************************************************************
 167  * SoC RTC
 168  ****************************************************************************/
 169 void __init dove_rtc_init(void)
 170 {
 171         orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
 172 }
 173
 174 /*****************************************************************************
 175  * SATA
 176  ****************************************************************************/
 177 void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
 178 {
 179         orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
 180
 181 }
 182
 183 /*****************************************************************************
 184  * UART0
 185  ****************************************************************************/
 186 void __init dove_uart0_init(void)
 187 {
 188         orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
 189                          IRQ_DOVE_UART_0, tclk);
 190 }
 191
 192 /*****************************************************************************
 193  * UART1
 194  ****************************************************************************/
 195 void __init dove_uart1_init(void)
 196 {
 197         orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
 198                          IRQ_DOVE_UART_1, tclk);
 199 }
 200
 201 /*****************************************************************************
 202  * UART2
 203  ****************************************************************************/
 204 void __init dove_uart2_init(void)
 205 {
 206         orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
 207                          IRQ_DOVE_UART_2, tclk);
 208 }
 209
 210 /*****************************************************************************
 211  * UART3
 212  ****************************************************************************/
 213 void __init dove_uart3_init(void)
 214 {
 215         orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
 216                          IRQ_DOVE_UART_3, tclk);
 217 }
 218
 219 /*****************************************************************************
 220  * SPI
 221  ****************************************************************************/
 222 void __init dove_spi0_init(void)
 223 {
 224         orion_spi_init(DOVE_SPI0_PHYS_BASE);
 225 }
 226
 227 void __init dove_spi1_init(void)
 228 {
 229         orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
 230 }
 231
 232 /*****************************************************************************
 233  * I2C
 234  ****************************************************************************/
 235 void __init dove_i2c_init(void)
 236 {
 237         orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
 238 }
 239
 240 /*****************************************************************************
 241  * Time handling
 242  ****************************************************************************/
 243 void __init dove_init_early(void)
 244 {
 245         orion_time_set_base(TIMER_VIRT_BASE);
 246 }
 247
 248 static int __init dove_find_tclk(void)
 249 {
 250         return 166666667;
 251 }
 252
 253 static void __init dove_timer_init(void)
 254 {
 255         dove_tclk = dove_find_tclk();
 256         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 257                         IRQ_DOVE_BRIDGE, dove_tclk);
 258 }
 259
 260 struct sys_timer dove_timer = {
 261         .init = dove_timer_init,
 262 };
 263
 264 /*****************************************************************************
 265  * Cryptographic Engines and Security Accelerator (CESA)
 266  ****************************************************************************/
 267 void __init dove_crypto_init(void)
 268 {
 269         orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
 270                           DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
 271 }
 272
 273 /*****************************************************************************
 274  * XOR 0
 275  ****************************************************************************/
 276 void __init dove_xor0_init(void)
 277 {
 278         orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
 279                         IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
 280 }
 281
 282 /*****************************************************************************
 283  * XOR 1
 284  ****************************************************************************/
 285 void __init dove_xor1_init(void)
 286 {
 287         orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
 288                         IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
 289 }
 290
 291 /*****************************************************************************
 292  * SDIO
 293  ****************************************************************************/
 294 static u64 sdio_dmamask = DMA_BIT_MASK(32);
 295
 296 static struct resource dove_sdio0_resources[] = {
 297         {
 298                 .start  = DOVE_SDIO0_PHYS_BASE,
 299                 .end    = DOVE_SDIO0_PHYS_BASE + 0xff,
 300                 .flags  = IORESOURCE_MEM,
 301         }, {
 302                 .start  = IRQ_DOVE_SDIO0,
 303                 .end    = IRQ_DOVE_SDIO0,
 304                 .flags  = IORESOURCE_IRQ,
 305         },
 306 };
 307
 308 static struct platform_device dove_sdio0 = {
 309         .name           = "sdhci-dove",
 310         .id             = 0,
 311         .dev            = {
 312                 .dma_mask               = &sdio_dmamask,
 313                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 314         },
 315         .resource       = dove_sdio0_resources,
 316         .num_resources  = ARRAY_SIZE(dove_sdio0_resources),
 317 };
 318
 319 void __init dove_sdio0_init(void)
 320 {
 321         platform_device_register(&dove_sdio0);
 322 }
 323
 324 static struct resource dove_sdio1_resources[] = {
 325         {
 326                 .start  = DOVE_SDIO1_PHYS_BASE,
 327                 .end    = DOVE_SDIO1_PHYS_BASE + 0xff,
 328                 .flags  = IORESOURCE_MEM,
 329         }, {
 330                 .start  = IRQ_DOVE_SDIO1,
 331                 .end    = IRQ_DOVE_SDIO1,
 332                 .flags  = IORESOURCE_IRQ,
 333         },
 334 };
 335
 336 static struct platform_device dove_sdio1 = {
 337         .name           = "sdhci-dove",
 338         .id             = 1,
 339         .dev            = {
 340                 .dma_mask               = &sdio_dmamask,
 341                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 342         },
 343         .resource       = dove_sdio1_resources,
 344         .num_resources  = ARRAY_SIZE(dove_sdio1_resources),
 345 };
 346
 347 void __init dove_sdio1_init(void)
 348 {
 349         platform_device_register(&dove_sdio1);
 350 }
 351
 352 void __init dove_init(void)
 353 {
 354         pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
 355                 (dove_tclk + 499999) / 1000000);
 356
 357 #ifdef CONFIG_CACHE_TAUROS2
 358         tauros2_init();
 359 #endif
 360         dove_setup_cpu_mbus();
 361
 362         /* Setup root of clk tree */
 363         dove_clk_init();
 364
 365         /* internal devices that every board has */
 366         dove_rtc_init();
 367         dove_xor0_init();
 368         dove_xor1_init();
 369 }
 370
 371 void dove_restart(char mode, const char *cmd)
 372 {
 373         /*
 374          * Enable soft reset to assert RSTOUTn.
 375          */
 376         writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
 377
 378         /*
 379          * Assert soft reset.
 380          */
 381         writel(SOFT_RESET, SYSTEM_SOFT_RESET);
 382
 383         while (1)
 384                 ;
 385 }
 386
 387 #if defined(CONFIG_MACH_DOVE_DT)
 388 /*
 389  * Auxdata required until real OF clock provider
 390  */
 391 struct of_dev_auxdata dove_auxdata_lookup[] __initdata = {
 392         OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
 393         OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL),
 394         OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
 395         OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
 396                        NULL),
 397         OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL),
 398         OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL),
 399         OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL),
 400         {},
 401 };
 402
 403 static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
 404         .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
 405 };
 406
 407 static void __init dove_dt_init(void)
 408 {
 409         pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
 410                 (dove_tclk + 499999) / 1000000);
 411
 412 #ifdef CONFIG_CACHE_TAUROS2
 413         tauros2_init();
 414 #endif
 415         dove_setup_cpu_mbus();
 416
 417         /* Setup root of clk tree */
 418         dove_clk_init();
 419
 420         /* Internal devices not ported to DT yet */
 421         dove_rtc_init();
 422         dove_xor0_init();
 423         dove_xor1_init();
 424
 425         dove_ge00_init(&dove_dt_ge00_data);
 426         dove_ehci0_init();
 427         dove_ehci1_init();
 428         dove_pcie_init(1, 1);
 429         dove_crypto_init();
 430
 431         of_platform_populate(NULL, of_default_bus_match_table,
 432                              dove_auxdata_lookup, NULL);
 433 }
 434
 435 static const char * const dove_dt_board_compat[] = {
 436         "marvell,dove",
 437         NULL
 438 };
 439
 440 DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
 441         .map_io         = dove_map_io,
 442         .init_early     = dove_init_early,
 443         .init_irq       = orion_dt_init_irq,
 444         .timer          = &dove_timer,
 445         .init_machine   = dove_dt_init,
 446         .restart        = dove_restart,
 447         .dt_compat      = dove_dt_board_compat,
 448 MACHINE_END
 449 #endif