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[ARM] 5577/2: ep93xx: syscon locked register functions
[deliverable/linux.git] / arch / arm / mach-ep93xx / core.c
1 /*
2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
7 *
8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9 * role in the ep93xx linux community.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/spinlock.h>
20 #include <linux/sched.h>
21 #include <linux/interrupt.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/bitops.h>
25 #include <linux/serial_8250.h>
26 #include <linux/serial_core.h>
27 #include <linux/device.h>
28 #include <linux/mm.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/time.h>
31 #include <linux/timex.h>
32 #include <linux/delay.h>
33 #include <linux/termios.h>
34 #include <linux/amba/bus.h>
35 #include <linux/amba/serial.h>
36 #include <linux/io.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-gpio.h>
39
40 #include <asm/types.h>
41 #include <asm/setup.h>
42 #include <asm/memory.h>
43 #include <mach/hardware.h>
44 #include <asm/irq.h>
45 #include <asm/system.h>
46 #include <asm/tlbflush.h>
47 #include <asm/pgtable.h>
48
49 #include <asm/mach/map.h>
50 #include <asm/mach/time.h>
51 #include <asm/mach/irq.h>
52 #include <mach/gpio.h>
53
54 #include <asm/hardware/vic.h>
55
56
57 /*************************************************************************
58 * Static I/O mappings that are needed for all EP93xx platforms
59 *************************************************************************/
60 static struct map_desc ep93xx_io_desc[] __initdata = {
61 {
62 .virtual = EP93XX_AHB_VIRT_BASE,
63 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
64 .length = EP93XX_AHB_SIZE,
65 .type = MT_DEVICE,
66 }, {
67 .virtual = EP93XX_APB_VIRT_BASE,
68 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
69 .length = EP93XX_APB_SIZE,
70 .type = MT_DEVICE,
71 },
72 };
73
74 void __init ep93xx_map_io(void)
75 {
76 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
77 }
78
79
80 /*************************************************************************
81 * Timer handling for EP93xx
82 *************************************************************************
83 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
84 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
85 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
86 * is free-running, and can't generate interrupts.
87 *
88 * The 508 kHz timers are ideal for use for the timer interrupt, as the
89 * most common values of HZ divide 508 kHz nicely. We pick one of the 16
90 * bit timers (timer 1) since we don't need more than 16 bits of reload
91 * value as long as HZ >= 8.
92 *
93 * The higher clock rate of timer 4 makes it a better choice than the
94 * other timers for use in gettimeoffset(), while the fact that it can't
95 * generate interrupts means we don't have to worry about not being able
96 * to use this timer for something else. We also use timer 4 for keeping
97 * track of lost jiffies.
98 */
99 static unsigned int last_jiffy_time;
100
101 #define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
102
103 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
104 {
105 __raw_writel(1, EP93XX_TIMER1_CLEAR);
106 while ((signed long)
107 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
108 >= TIMER4_TICKS_PER_JIFFY) {
109 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
110 timer_tick();
111 }
112
113 return IRQ_HANDLED;
114 }
115
116 static struct irqaction ep93xx_timer_irq = {
117 .name = "ep93xx timer",
118 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
119 .handler = ep93xx_timer_interrupt,
120 };
121
122 static void __init ep93xx_timer_init(void)
123 {
124 /* Enable periodic HZ timer. */
125 __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
126 __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
127 __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
128
129 /* Enable lost jiffy timer. */
130 __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
131
132 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
133 }
134
135 static unsigned long ep93xx_gettimeoffset(void)
136 {
137 int offset;
138
139 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
140
141 /* Calculate (1000000 / 983040) * offset. */
142 return offset + (53 * offset / 3072);
143 }
144
145 struct sys_timer ep93xx_timer = {
146 .init = ep93xx_timer_init,
147 .offset = ep93xx_gettimeoffset,
148 };
149
150
151 /*************************************************************************
152 * GPIO handling for EP93xx
153 *************************************************************************/
154 static unsigned char gpio_int_unmasked[3];
155 static unsigned char gpio_int_enabled[3];
156 static unsigned char gpio_int_type1[3];
157 static unsigned char gpio_int_type2[3];
158 static unsigned char gpio_int_debounce[3];
159
160 /* Port ordering is: A B F */
161 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
162 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
163 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
164 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
165 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
166
167 void ep93xx_gpio_update_int_params(unsigned port)
168 {
169 BUG_ON(port > 2);
170
171 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
172
173 __raw_writeb(gpio_int_type2[port],
174 EP93XX_GPIO_REG(int_type2_register_offset[port]));
175
176 __raw_writeb(gpio_int_type1[port],
177 EP93XX_GPIO_REG(int_type1_register_offset[port]));
178
179 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
180 EP93XX_GPIO_REG(int_en_register_offset[port]));
181 }
182
183 void ep93xx_gpio_int_mask(unsigned line)
184 {
185 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
186 }
187
188 void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
189 {
190 int line = irq_to_gpio(irq);
191 int port = line >> 3;
192 int port_mask = 1 << (line & 7);
193
194 if (enable)
195 gpio_int_debounce[port] |= port_mask;
196 else
197 gpio_int_debounce[port] &= ~port_mask;
198
199 __raw_writeb(gpio_int_debounce[port],
200 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
201 }
202 EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
203
204 /*************************************************************************
205 * EP93xx IRQ handling
206 *************************************************************************/
207 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
208 {
209 unsigned char status;
210 int i;
211
212 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
213 for (i = 0; i < 8; i++) {
214 if (status & (1 << i)) {
215 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
216 generic_handle_irq(gpio_irq);
217 }
218 }
219
220 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
221 for (i = 0; i < 8; i++) {
222 if (status & (1 << i)) {
223 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
224 desc = irq_desc + gpio_irq;
225 generic_handle_irq(gpio_irq);
226 }
227 }
228 }
229
230 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
231 {
232 /*
233 * map discontiguous hw irq range to continous sw irq range:
234 *
235 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
236 */
237 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
238 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
239
240 generic_handle_irq(gpio_irq);
241 }
242
243 static void ep93xx_gpio_irq_ack(unsigned int irq)
244 {
245 int line = irq_to_gpio(irq);
246 int port = line >> 3;
247 int port_mask = 1 << (line & 7);
248
249 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
250 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
251 ep93xx_gpio_update_int_params(port);
252 }
253
254 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
255 }
256
257 static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
258 {
259 int line = irq_to_gpio(irq);
260 int port = line >> 3;
261 int port_mask = 1 << (line & 7);
262
263 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
264 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
265
266 gpio_int_unmasked[port] &= ~port_mask;
267 ep93xx_gpio_update_int_params(port);
268
269 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
270 }
271
272 static void ep93xx_gpio_irq_mask(unsigned int irq)
273 {
274 int line = irq_to_gpio(irq);
275 int port = line >> 3;
276
277 gpio_int_unmasked[port] &= ~(1 << (line & 7));
278 ep93xx_gpio_update_int_params(port);
279 }
280
281 static void ep93xx_gpio_irq_unmask(unsigned int irq)
282 {
283 int line = irq_to_gpio(irq);
284 int port = line >> 3;
285
286 gpio_int_unmasked[port] |= 1 << (line & 7);
287 ep93xx_gpio_update_int_params(port);
288 }
289
290
291 /*
292 * gpio_int_type1 controls whether the interrupt is level (0) or
293 * edge (1) triggered, while gpio_int_type2 controls whether it
294 * triggers on low/falling (0) or high/rising (1).
295 */
296 static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
297 {
298 struct irq_desc *desc = irq_desc + irq;
299 const int gpio = irq_to_gpio(irq);
300 const int port = gpio >> 3;
301 const int port_mask = 1 << (gpio & 7);
302
303 gpio_direction_input(gpio);
304
305 switch (type) {
306 case IRQ_TYPE_EDGE_RISING:
307 gpio_int_type1[port] |= port_mask;
308 gpio_int_type2[port] |= port_mask;
309 desc->handle_irq = handle_edge_irq;
310 break;
311 case IRQ_TYPE_EDGE_FALLING:
312 gpio_int_type1[port] |= port_mask;
313 gpio_int_type2[port] &= ~port_mask;
314 desc->handle_irq = handle_edge_irq;
315 break;
316 case IRQ_TYPE_LEVEL_HIGH:
317 gpio_int_type1[port] &= ~port_mask;
318 gpio_int_type2[port] |= port_mask;
319 desc->handle_irq = handle_level_irq;
320 break;
321 case IRQ_TYPE_LEVEL_LOW:
322 gpio_int_type1[port] &= ~port_mask;
323 gpio_int_type2[port] &= ~port_mask;
324 desc->handle_irq = handle_level_irq;
325 break;
326 case IRQ_TYPE_EDGE_BOTH:
327 gpio_int_type1[port] |= port_mask;
328 /* set initial polarity based on current input level */
329 if (gpio_get_value(gpio))
330 gpio_int_type2[port] &= ~port_mask; /* falling */
331 else
332 gpio_int_type2[port] |= port_mask; /* rising */
333 desc->handle_irq = handle_edge_irq;
334 break;
335 default:
336 pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
337 type, gpio);
338 return -EINVAL;
339 }
340
341 gpio_int_enabled[port] |= port_mask;
342
343 desc->status &= ~IRQ_TYPE_SENSE_MASK;
344 desc->status |= type & IRQ_TYPE_SENSE_MASK;
345
346 ep93xx_gpio_update_int_params(port);
347
348 return 0;
349 }
350
351 static struct irq_chip ep93xx_gpio_irq_chip = {
352 .name = "GPIO",
353 .ack = ep93xx_gpio_irq_ack,
354 .mask_ack = ep93xx_gpio_irq_mask_ack,
355 .mask = ep93xx_gpio_irq_mask,
356 .unmask = ep93xx_gpio_irq_unmask,
357 .set_type = ep93xx_gpio_irq_type,
358 };
359
360
361 void __init ep93xx_init_irq(void)
362 {
363 int gpio_irq;
364
365 vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
366 vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
367
368 for (gpio_irq = gpio_to_irq(0);
369 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
370 set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
371 set_irq_handler(gpio_irq, handle_level_irq);
372 set_irq_flags(gpio_irq, IRQF_VALID);
373 }
374
375 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
376 set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
377 set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
378 set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
379 set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
380 set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
381 set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
382 set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
383 set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
384 }
385
386
387 /*************************************************************************
388 * EP93xx System Controller Software Locked register handling
389 *************************************************************************/
390
391 /*
392 * syscon_swlock prevents anything else from writing to the syscon
393 * block while a software locked register is being written.
394 */
395 static DEFINE_SPINLOCK(syscon_swlock);
396
397 void ep93xx_syscon_swlocked_write(unsigned int val, unsigned int reg)
398 {
399 unsigned long flags;
400
401 spin_lock_irqsave(&syscon_swlock, flags);
402
403 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
404 __raw_writel(val, reg);
405
406 spin_unlock_irqrestore(&syscon_swlock, flags);
407 }
408 EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
409
410 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
411 {
412 unsigned long flags;
413 unsigned int val;
414
415 spin_lock_irqsave(&syscon_swlock, flags);
416
417 val = __raw_readl(EP93XX_SYSCON_DEVCFG);
418 val |= set_bits;
419 val &= ~clear_bits;
420 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
421 __raw_writel(val, EP93XX_SYSCON_DEVCFG);
422
423 spin_unlock_irqrestore(&syscon_swlock, flags);
424 }
425 EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
426
427
428 /*************************************************************************
429 * EP93xx peripheral handling
430 *************************************************************************/
431 #define EP93XX_UART_MCR_OFFSET (0x0100)
432
433 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
434 void __iomem *base, unsigned int mctrl)
435 {
436 unsigned int mcr;
437
438 mcr = 0;
439 if (!(mctrl & TIOCM_RTS))
440 mcr |= 2;
441 if (!(mctrl & TIOCM_DTR))
442 mcr |= 1;
443
444 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
445 }
446
447 static struct amba_pl010_data ep93xx_uart_data = {
448 .set_mctrl = ep93xx_uart_set_mctrl,
449 };
450
451 static struct amba_device uart1_device = {
452 .dev = {
453 .init_name = "apb:uart1",
454 .platform_data = &ep93xx_uart_data,
455 },
456 .res = {
457 .start = EP93XX_UART1_PHYS_BASE,
458 .end = EP93XX_UART1_PHYS_BASE + 0x0fff,
459 .flags = IORESOURCE_MEM,
460 },
461 .irq = { IRQ_EP93XX_UART1, NO_IRQ },
462 .periphid = 0x00041010,
463 };
464
465 static struct amba_device uart2_device = {
466 .dev = {
467 .init_name = "apb:uart2",
468 .platform_data = &ep93xx_uart_data,
469 },
470 .res = {
471 .start = EP93XX_UART2_PHYS_BASE,
472 .end = EP93XX_UART2_PHYS_BASE + 0x0fff,
473 .flags = IORESOURCE_MEM,
474 },
475 .irq = { IRQ_EP93XX_UART2, NO_IRQ },
476 .periphid = 0x00041010,
477 };
478
479 static struct amba_device uart3_device = {
480 .dev = {
481 .init_name = "apb:uart3",
482 .platform_data = &ep93xx_uart_data,
483 },
484 .res = {
485 .start = EP93XX_UART3_PHYS_BASE,
486 .end = EP93XX_UART3_PHYS_BASE + 0x0fff,
487 .flags = IORESOURCE_MEM,
488 },
489 .irq = { IRQ_EP93XX_UART3, NO_IRQ },
490 .periphid = 0x00041010,
491 };
492
493
494 static struct resource ep93xx_rtc_resource[] = {
495 {
496 .start = EP93XX_RTC_PHYS_BASE,
497 .end = EP93XX_RTC_PHYS_BASE + 0x10c - 1,
498 .flags = IORESOURCE_MEM,
499 },
500 };
501
502 static struct platform_device ep93xx_rtc_device = {
503 .name = "ep93xx-rtc",
504 .id = -1,
505 .num_resources = ARRAY_SIZE(ep93xx_rtc_resource),
506 .resource = ep93xx_rtc_resource,
507 };
508
509
510 static struct resource ep93xx_ohci_resources[] = {
511 [0] = {
512 .start = EP93XX_USB_PHYS_BASE,
513 .end = EP93XX_USB_PHYS_BASE + 0x0fff,
514 .flags = IORESOURCE_MEM,
515 },
516 [1] = {
517 .start = IRQ_EP93XX_USB,
518 .end = IRQ_EP93XX_USB,
519 .flags = IORESOURCE_IRQ,
520 },
521 };
522
523
524 static struct platform_device ep93xx_ohci_device = {
525 .name = "ep93xx-ohci",
526 .id = -1,
527 .dev = {
528 .dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask,
529 .coherent_dma_mask = DMA_BIT_MASK(32),
530 },
531 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
532 .resource = ep93xx_ohci_resources,
533 };
534
535 static struct ep93xx_eth_data ep93xx_eth_data;
536
537 static struct resource ep93xx_eth_resource[] = {
538 {
539 .start = EP93XX_ETHERNET_PHYS_BASE,
540 .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
541 .flags = IORESOURCE_MEM,
542 }, {
543 .start = IRQ_EP93XX_ETHERNET,
544 .end = IRQ_EP93XX_ETHERNET,
545 .flags = IORESOURCE_IRQ,
546 }
547 };
548
549 static struct platform_device ep93xx_eth_device = {
550 .name = "ep93xx-eth",
551 .id = -1,
552 .dev = {
553 .platform_data = &ep93xx_eth_data,
554 },
555 .num_resources = ARRAY_SIZE(ep93xx_eth_resource),
556 .resource = ep93xx_eth_resource,
557 };
558
559 void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
560 {
561 if (copy_addr) {
562 memcpy(data->dev_addr,
563 (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
564 }
565
566 ep93xx_eth_data = *data;
567 platform_device_register(&ep93xx_eth_device);
568 }
569
570 static struct i2c_gpio_platform_data ep93xx_i2c_data = {
571 .sda_pin = EP93XX_GPIO_LINE_EEDAT,
572 .sda_is_open_drain = 0,
573 .scl_pin = EP93XX_GPIO_LINE_EECLK,
574 .scl_is_open_drain = 0,
575 .udelay = 2,
576 };
577
578 static struct platform_device ep93xx_i2c_device = {
579 .name = "i2c-gpio",
580 .id = 0,
581 .dev.platform_data = &ep93xx_i2c_data,
582 };
583
584 void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
585 {
586 i2c_register_board_info(0, devices, num);
587 platform_device_register(&ep93xx_i2c_device);
588 }
589
590 extern void ep93xx_gpio_init(void);
591
592 void __init ep93xx_init_devices(void)
593 {
594 /* Disallow access to MaverickCrunch initially */
595 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
596
597 ep93xx_gpio_init();
598
599 amba_device_register(&uart1_device, &iomem_resource);
600 amba_device_register(&uart2_device, &iomem_resource);
601 amba_device_register(&uart3_device, &iomem_resource);
602
603 platform_device_register(&ep93xx_rtc_device);
604 platform_device_register(&ep93xx_ohci_device);
605 }
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