arch/arm/mach-ep93xx/timer-ep93xx.c

   1 #include <linux/kernel.h>
   2 #include <linux/init.h>
   3 #include <linux/clocksource.h>
   4 #include <linux/clockchips.h>
   5 #include <linux/sched_clock.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/irq.h>
   8 #include <linux/io.h>
   9 #include <asm/mach/time.h>
  10 #include "soc.h"
  11
  12 /*************************************************************************
  13  * Timer handling for EP93xx
  14  *************************************************************************
  15  * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
  16  * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
  17  * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
  18  * is free-running, and can't generate interrupts.
  19  *
  20  * The 508 kHz timers are ideal for use for the timer interrupt, as the
  21  * most common values of HZ divide 508 kHz nicely.  We pick one of the 16
  22  * bit timers (timer 1) since we don't need more than 16 bits of reload
  23  * value as long as HZ >= 8.
  24  *
  25  * The higher clock rate of timer 4 makes it a better choice than the
  26  * other timers for use in gettimeoffset(), while the fact that it can't
  27  * generate interrupts means we don't have to worry about not being able
  28  * to use this timer for something else.  We also use timer 4 for keeping
  29  * track of lost jiffies.
  30  */
  31 #define EP93XX_TIMER_REG(x)             (EP93XX_TIMER_BASE + (x))
  32 #define EP93XX_TIMER1_LOAD              EP93XX_TIMER_REG(0x00)
  33 #define EP93XX_TIMER1_VALUE             EP93XX_TIMER_REG(0x04)
  34 #define EP93XX_TIMER1_CONTROL           EP93XX_TIMER_REG(0x08)
  35 #define EP93XX_TIMER123_CONTROL_ENABLE  (1 << 7)
  36 #define EP93XX_TIMER123_CONTROL_MODE    (1 << 6)
  37 #define EP93XX_TIMER123_CONTROL_CLKSEL  (1 << 3)
  38 #define EP93XX_TIMER1_CLEAR             EP93XX_TIMER_REG(0x0c)
  39 #define EP93XX_TIMER2_LOAD              EP93XX_TIMER_REG(0x20)
  40 #define EP93XX_TIMER2_VALUE             EP93XX_TIMER_REG(0x24)
  41 #define EP93XX_TIMER2_CONTROL           EP93XX_TIMER_REG(0x28)
  42 #define EP93XX_TIMER2_CLEAR             EP93XX_TIMER_REG(0x2c)
  43 #define EP93XX_TIMER4_VALUE_LOW         EP93XX_TIMER_REG(0x60)
  44 #define EP93XX_TIMER4_VALUE_HIGH        EP93XX_TIMER_REG(0x64)
  45 #define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
  46 #define EP93XX_TIMER3_LOAD              EP93XX_TIMER_REG(0x80)
  47 #define EP93XX_TIMER3_VALUE             EP93XX_TIMER_REG(0x84)
  48 #define EP93XX_TIMER3_CONTROL           EP93XX_TIMER_REG(0x88)
  49 #define EP93XX_TIMER3_CLEAR             EP93XX_TIMER_REG(0x8c)
  50
  51 #define EP93XX_TIMER123_RATE            508469
  52 #define EP93XX_TIMER4_RATE              983040
  53
  54 static u64 notrace ep93xx_read_sched_clock(void)
  55 {
  56         u64 ret;
  57
  58         ret = __raw_readl(EP93XX_TIMER4_VALUE_LOW);
  59         ret |= ((u64) (__raw_readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
  60         return ret;
  61 }
  62
  63 cycle_t ep93xx_clocksource_read(struct clocksource *c)
  64 {
  65         u64 ret;
  66
  67         ret = __raw_readl(EP93XX_TIMER4_VALUE_LOW);
  68         ret |= ((u64) (__raw_readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
  69         return (cycle_t) ret;
  70 }
  71
  72 static int ep93xx_clkevt_set_next_event(unsigned long next,
  73                                         struct clock_event_device *evt)
  74 {
  75         /* Default mode: periodic, off, 508 kHz */
  76         u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
  77                     EP93XX_TIMER123_CONTROL_CLKSEL;
  78
  79         /* Clear timer */
  80         __raw_writel(tmode, EP93XX_TIMER1_CONTROL);
  81
  82         /* Set next event */
  83         __raw_writel(next, EP93XX_TIMER1_LOAD);
  84         __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
  85                      EP93XX_TIMER1_CONTROL);
  86         return 0;
  87 }
  88
  89
  90 static void ep93xx_clkevt_set_mode(enum clock_event_mode mode,
  91                                    struct clock_event_device *evt)
  92 {
  93         /* Disable timer */
  94         __raw_writel(0, EP93XX_TIMER1_CONTROL);
  95 }
  96
  97 static struct clock_event_device ep93xx_clockevent = {
  98         .name           = "timer1",
  99         .features       = CLOCK_EVT_FEAT_ONESHOT,
 100         .set_mode       = ep93xx_clkevt_set_mode,
 101         .set_next_event = ep93xx_clkevt_set_next_event,
 102         .rating         = 300,
 103 };
 104
 105 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
 106 {
 107         struct clock_event_device *evt = dev_id;
 108
 109         /* Writing any value clears the timer interrupt */
 110         __raw_writel(1, EP93XX_TIMER1_CLEAR);
 111
 112         evt->event_handler(evt);
 113
 114         return IRQ_HANDLED;
 115 }
 116
 117 static struct irqaction ep93xx_timer_irq = {
 118         .name           = "ep93xx timer",
 119         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 120         .handler        = ep93xx_timer_interrupt,
 121         .dev_id         = &ep93xx_clockevent,
 122 };
 123
 124 void __init ep93xx_timer_init(void)
 125 {
 126         /* Enable and register clocksource and sched_clock on timer 4 */
 127         __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
 128                         EP93XX_TIMER4_VALUE_HIGH);
 129         clocksource_mmio_init(NULL, "timer4",
 130                               EP93XX_TIMER4_RATE, 200, 40,
 131                               ep93xx_clocksource_read);
 132         sched_clock_register(ep93xx_read_sched_clock, 40,
 133                              EP93XX_TIMER4_RATE);
 134
 135         /* Set up clockevent on timer 1 */
 136         setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
 137         // FIXME: timer one is 16 bits 1-ffff use timer 3 1-ffffffff */
 138         clockevents_config_and_register(&ep93xx_clockevent,
 139                                         EP93XX_TIMER123_RATE,
 140                                         1,
 141                                         0xffffU);
 142 }