2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS4 - Clock support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/err.h>
15 #include <linux/syscore_ops.h>
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
26 #include <mach/regs-clock.h>
27 #include <mach/sysmmu.h>
30 #include "clock-exynos4.h"
32 #ifdef CONFIG_PM_SLEEP
33 static struct sleep_save exynos4_clock_save
[] = {
34 SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS
),
35 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS
),
36 SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS
),
37 SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS
),
38 SAVE_ITEM(EXYNOS4_CLKSRC_TOP0
),
39 SAVE_ITEM(EXYNOS4_CLKSRC_TOP1
),
40 SAVE_ITEM(EXYNOS4_CLKSRC_CAM
),
41 SAVE_ITEM(EXYNOS4_CLKSRC_TV
),
42 SAVE_ITEM(EXYNOS4_CLKSRC_MFC
),
43 SAVE_ITEM(EXYNOS4_CLKSRC_G3D
),
44 SAVE_ITEM(EXYNOS4_CLKSRC_LCD0
),
45 SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO
),
46 SAVE_ITEM(EXYNOS4_CLKSRC_FSYS
),
47 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0
),
48 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1
),
49 SAVE_ITEM(EXYNOS4_CLKDIV_CAM
),
50 SAVE_ITEM(EXYNOS4_CLKDIV_TV
),
51 SAVE_ITEM(EXYNOS4_CLKDIV_MFC
),
52 SAVE_ITEM(EXYNOS4_CLKDIV_G3D
),
53 SAVE_ITEM(EXYNOS4_CLKDIV_LCD0
),
54 SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO
),
55 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0
),
56 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1
),
57 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2
),
58 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3
),
59 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0
),
60 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1
),
61 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2
),
62 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3
),
63 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4
),
64 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5
),
65 SAVE_ITEM(EXYNOS4_CLKDIV_TOP
),
66 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP
),
67 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM
),
68 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV
),
69 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0
),
70 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO
),
71 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS
),
72 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0
),
73 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1
),
74 SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO
),
75 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM
),
76 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM
),
77 SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV
),
78 SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC
),
79 SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D
),
80 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0
),
81 SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS
),
82 SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS
),
83 SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL
),
84 SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK
),
85 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC
),
86 SAVE_ITEM(EXYNOS4_CLKSRC_DMC
),
87 SAVE_ITEM(EXYNOS4_CLKDIV_DMC0
),
88 SAVE_ITEM(EXYNOS4_CLKDIV_DMC1
),
89 SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC
),
90 SAVE_ITEM(EXYNOS4_CLKSRC_CPU
),
91 SAVE_ITEM(EXYNOS4_CLKDIV_CPU
),
92 SAVE_ITEM(EXYNOS4_CLKDIV_CPU
+ 0x4),
93 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU
),
94 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU
),
98 static struct clk exynos4_clk_sclk_hdmi27m
= {
99 .name
= "sclk_hdmi27m",
103 static struct clk exynos4_clk_sclk_hdmiphy
= {
104 .name
= "sclk_hdmiphy",
107 static struct clk exynos4_clk_sclk_usbphy0
= {
108 .name
= "sclk_usbphy0",
112 static struct clk exynos4_clk_sclk_usbphy1
= {
113 .name
= "sclk_usbphy1",
116 static struct clk dummy_apb_pclk
= {
121 static int exynos4_clksrc_mask_top_ctrl(struct clk
*clk
, int enable
)
123 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP
, clk
, enable
);
126 static int exynos4_clksrc_mask_cam_ctrl(struct clk
*clk
, int enable
)
128 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM
, clk
, enable
);
131 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk
*clk
, int enable
)
133 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0
, clk
, enable
);
136 int exynos4_clksrc_mask_fsys_ctrl(struct clk
*clk
, int enable
)
138 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS
, clk
, enable
);
141 static int exynos4_clksrc_mask_peril0_ctrl(struct clk
*clk
, int enable
)
143 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0
, clk
, enable
);
146 static int exynos4_clksrc_mask_peril1_ctrl(struct clk
*clk
, int enable
)
148 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1
, clk
, enable
);
151 static int exynos4_clk_ip_mfc_ctrl(struct clk
*clk
, int enable
)
153 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC
, clk
, enable
);
156 static int exynos4_clksrc_mask_tv_ctrl(struct clk
*clk
, int enable
)
158 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV
, clk
, enable
);
161 static int exynos4_clk_ip_cam_ctrl(struct clk
*clk
, int enable
)
163 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM
, clk
, enable
);
166 static int exynos4_clk_ip_tv_ctrl(struct clk
*clk
, int enable
)
168 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV
, clk
, enable
);
171 static int exynos4_clk_ip_image_ctrl(struct clk
*clk
, int enable
)
173 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE
, clk
, enable
);
176 static int exynos4_clk_ip_lcd0_ctrl(struct clk
*clk
, int enable
)
178 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0
, clk
, enable
);
181 int exynos4_clk_ip_lcd1_ctrl(struct clk
*clk
, int enable
)
183 return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1
, clk
, enable
);
186 int exynos4_clk_ip_fsys_ctrl(struct clk
*clk
, int enable
)
188 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS
, clk
, enable
);
191 static int exynos4_clk_ip_peril_ctrl(struct clk
*clk
, int enable
)
193 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL
, clk
, enable
);
196 static int exynos4_clk_ip_perir_ctrl(struct clk
*clk
, int enable
)
198 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR
, clk
, enable
);
201 static int exynos4_clk_hdmiphy_ctrl(struct clk
*clk
, int enable
)
203 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL
, clk
, enable
);
206 static int exynos4_clk_dac_ctrl(struct clk
*clk
, int enable
)
208 return s5p_gatectrl(S5P_DAC_PHY_CONTROL
, clk
, enable
);
211 /* Core list of CMU_CPU side */
213 static struct clksrc_clk exynos4_clk_mout_apll
= {
217 .sources
= &clk_src_apll
,
218 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CPU
, .shift
= 0, .size
= 1 },
221 static struct clksrc_clk exynos4_clk_sclk_apll
= {
224 .parent
= &exynos4_clk_mout_apll
.clk
,
226 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CPU
, .shift
= 24, .size
= 3 },
229 static struct clksrc_clk exynos4_clk_mout_epll
= {
233 .sources
= &clk_src_epll
,
234 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP0
, .shift
= 4, .size
= 1 },
237 struct clksrc_clk exynos4_clk_mout_mpll
= {
241 .sources
= &clk_src_mpll
,
243 /* reg_src will be added in each SoCs' clock */
246 static struct clk
*exynos4_clkset_moutcore_list
[] = {
247 [0] = &exynos4_clk_mout_apll
.clk
,
248 [1] = &exynos4_clk_mout_mpll
.clk
,
251 static struct clksrc_sources exynos4_clkset_moutcore
= {
252 .sources
= exynos4_clkset_moutcore_list
,
253 .nr_sources
= ARRAY_SIZE(exynos4_clkset_moutcore_list
),
256 static struct clksrc_clk exynos4_clk_moutcore
= {
260 .sources
= &exynos4_clkset_moutcore
,
261 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CPU
, .shift
= 16, .size
= 1 },
264 static struct clksrc_clk exynos4_clk_coreclk
= {
267 .parent
= &exynos4_clk_moutcore
.clk
,
269 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CPU
, .shift
= 0, .size
= 3 },
272 static struct clksrc_clk exynos4_clk_armclk
= {
275 .parent
= &exynos4_clk_coreclk
.clk
,
279 static struct clksrc_clk exynos4_clk_aclk_corem0
= {
281 .name
= "aclk_corem0",
282 .parent
= &exynos4_clk_coreclk
.clk
,
284 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CPU
, .shift
= 4, .size
= 3 },
287 static struct clksrc_clk exynos4_clk_aclk_cores
= {
289 .name
= "aclk_cores",
290 .parent
= &exynos4_clk_coreclk
.clk
,
292 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CPU
, .shift
= 4, .size
= 3 },
295 static struct clksrc_clk exynos4_clk_aclk_corem1
= {
297 .name
= "aclk_corem1",
298 .parent
= &exynos4_clk_coreclk
.clk
,
300 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CPU
, .shift
= 8, .size
= 3 },
303 static struct clksrc_clk exynos4_clk_periphclk
= {
306 .parent
= &exynos4_clk_coreclk
.clk
,
308 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CPU
, .shift
= 12, .size
= 3 },
311 /* Core list of CMU_CORE side */
313 static struct clk
*exynos4_clkset_corebus_list
[] = {
314 [0] = &exynos4_clk_mout_mpll
.clk
,
315 [1] = &exynos4_clk_sclk_apll
.clk
,
318 struct clksrc_sources exynos4_clkset_mout_corebus
= {
319 .sources
= exynos4_clkset_corebus_list
,
320 .nr_sources
= ARRAY_SIZE(exynos4_clkset_corebus_list
),
323 static struct clksrc_clk exynos4_clk_mout_corebus
= {
325 .name
= "mout_corebus",
327 .sources
= &exynos4_clkset_mout_corebus
,
328 .reg_src
= { .reg
= EXYNOS4_CLKSRC_DMC
, .shift
= 4, .size
= 1 },
331 static struct clksrc_clk exynos4_clk_sclk_dmc
= {
334 .parent
= &exynos4_clk_mout_corebus
.clk
,
336 .reg_div
= { .reg
= EXYNOS4_CLKDIV_DMC0
, .shift
= 12, .size
= 3 },
339 static struct clksrc_clk exynos4_clk_aclk_cored
= {
341 .name
= "aclk_cored",
342 .parent
= &exynos4_clk_sclk_dmc
.clk
,
344 .reg_div
= { .reg
= EXYNOS4_CLKDIV_DMC0
, .shift
= 16, .size
= 3 },
347 static struct clksrc_clk exynos4_clk_aclk_corep
= {
349 .name
= "aclk_corep",
350 .parent
= &exynos4_clk_aclk_cored
.clk
,
352 .reg_div
= { .reg
= EXYNOS4_CLKDIV_DMC0
, .shift
= 20, .size
= 3 },
355 static struct clksrc_clk exynos4_clk_aclk_acp
= {
358 .parent
= &exynos4_clk_mout_corebus
.clk
,
360 .reg_div
= { .reg
= EXYNOS4_CLKDIV_DMC0
, .shift
= 0, .size
= 3 },
363 static struct clksrc_clk exynos4_clk_pclk_acp
= {
366 .parent
= &exynos4_clk_aclk_acp
.clk
,
368 .reg_div
= { .reg
= EXYNOS4_CLKDIV_DMC0
, .shift
= 4, .size
= 3 },
371 /* Core list of CMU_TOP side */
373 struct clk
*exynos4_clkset_aclk_top_list
[] = {
374 [0] = &exynos4_clk_mout_mpll
.clk
,
375 [1] = &exynos4_clk_sclk_apll
.clk
,
378 static struct clksrc_sources exynos4_clkset_aclk
= {
379 .sources
= exynos4_clkset_aclk_top_list
,
380 .nr_sources
= ARRAY_SIZE(exynos4_clkset_aclk_top_list
),
383 static struct clksrc_clk exynos4_clk_aclk_200
= {
387 .sources
= &exynos4_clkset_aclk
,
388 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP0
, .shift
= 12, .size
= 1 },
389 .reg_div
= { .reg
= EXYNOS4_CLKDIV_TOP
, .shift
= 0, .size
= 3 },
392 static struct clksrc_clk exynos4_clk_aclk_100
= {
396 .sources
= &exynos4_clkset_aclk
,
397 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP0
, .shift
= 16, .size
= 1 },
398 .reg_div
= { .reg
= EXYNOS4_CLKDIV_TOP
, .shift
= 4, .size
= 4 },
401 static struct clksrc_clk exynos4_clk_aclk_160
= {
405 .sources
= &exynos4_clkset_aclk
,
406 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP0
, .shift
= 20, .size
= 1 },
407 .reg_div
= { .reg
= EXYNOS4_CLKDIV_TOP
, .shift
= 8, .size
= 3 },
410 struct clksrc_clk exynos4_clk_aclk_133
= {
414 .sources
= &exynos4_clkset_aclk
,
415 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP0
, .shift
= 24, .size
= 1 },
416 .reg_div
= { .reg
= EXYNOS4_CLKDIV_TOP
, .shift
= 12, .size
= 3 },
419 static struct clk
*exynos4_clkset_vpllsrc_list
[] = {
421 [1] = &exynos4_clk_sclk_hdmi27m
,
424 static struct clksrc_sources exynos4_clkset_vpllsrc
= {
425 .sources
= exynos4_clkset_vpllsrc_list
,
426 .nr_sources
= ARRAY_SIZE(exynos4_clkset_vpllsrc_list
),
429 static struct clksrc_clk exynos4_clk_vpllsrc
= {
432 .enable
= exynos4_clksrc_mask_top_ctrl
,
435 .sources
= &exynos4_clkset_vpllsrc
,
436 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP1
, .shift
= 0, .size
= 1 },
439 static struct clk
*exynos4_clkset_sclk_vpll_list
[] = {
440 [0] = &exynos4_clk_vpllsrc
.clk
,
441 [1] = &clk_fout_vpll
,
444 static struct clksrc_sources exynos4_clkset_sclk_vpll
= {
445 .sources
= exynos4_clkset_sclk_vpll_list
,
446 .nr_sources
= ARRAY_SIZE(exynos4_clkset_sclk_vpll_list
),
449 static struct clksrc_clk exynos4_clk_sclk_vpll
= {
453 .sources
= &exynos4_clkset_sclk_vpll
,
454 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP0
, .shift
= 8, .size
= 1 },
457 static struct clk exynos4_init_clocks_off
[] = {
460 .parent
= &exynos4_clk_aclk_100
.clk
,
461 .enable
= exynos4_clk_ip_peril_ctrl
,
465 .devname
= "s5p-mipi-csis.0",
466 .enable
= exynos4_clk_ip_cam_ctrl
,
470 .devname
= "s5p-mipi-csis.1",
471 .enable
= exynos4_clk_ip_cam_ctrl
,
476 .enable
= exynos4_clk_ip_cam_ctrl
,
480 .devname
= "exynos4-fimc.0",
481 .enable
= exynos4_clk_ip_cam_ctrl
,
485 .devname
= "exynos4-fimc.1",
486 .enable
= exynos4_clk_ip_cam_ctrl
,
490 .devname
= "exynos4-fimc.2",
491 .enable
= exynos4_clk_ip_cam_ctrl
,
495 .devname
= "exynos4-fimc.3",
496 .enable
= exynos4_clk_ip_cam_ctrl
,
500 .devname
= "s3c-sdhci.0",
501 .parent
= &exynos4_clk_aclk_133
.clk
,
502 .enable
= exynos4_clk_ip_fsys_ctrl
,
506 .devname
= "s3c-sdhci.1",
507 .parent
= &exynos4_clk_aclk_133
.clk
,
508 .enable
= exynos4_clk_ip_fsys_ctrl
,
512 .devname
= "s3c-sdhci.2",
513 .parent
= &exynos4_clk_aclk_133
.clk
,
514 .enable
= exynos4_clk_ip_fsys_ctrl
,
518 .devname
= "s3c-sdhci.3",
519 .parent
= &exynos4_clk_aclk_133
.clk
,
520 .enable
= exynos4_clk_ip_fsys_ctrl
,
524 .parent
= &exynos4_clk_aclk_133
.clk
,
525 .enable
= exynos4_clk_ip_fsys_ctrl
,
529 .devname
= "s5p-sdo",
530 .enable
= exynos4_clk_ip_tv_ctrl
,
534 .devname
= "s5p-mixer",
535 .enable
= exynos4_clk_ip_tv_ctrl
,
539 .devname
= "s5p-mixer",
540 .enable
= exynos4_clk_ip_tv_ctrl
,
544 .devname
= "exynos4-hdmi",
545 .enable
= exynos4_clk_ip_tv_ctrl
,
549 .devname
= "exynos4-hdmi",
550 .enable
= exynos4_clk_hdmiphy_ctrl
,
554 .devname
= "s5p-sdo",
555 .enable
= exynos4_clk_dac_ctrl
,
559 .enable
= exynos4_clk_ip_peril_ctrl
,
560 .ctrlbit
= (1 << 15),
563 .enable
= exynos4_clk_ip_perir_ctrl
,
564 .ctrlbit
= (1 << 16),
567 .enable
= exynos4_clk_ip_perir_ctrl
,
568 .ctrlbit
= (1 << 15),
571 .parent
= &exynos4_clk_aclk_100
.clk
,
572 .enable
= exynos4_clk_ip_perir_ctrl
,
573 .ctrlbit
= (1 << 14),
576 .enable
= exynos4_clk_ip_fsys_ctrl
,
577 .ctrlbit
= (1 << 12),
580 .enable
= exynos4_clk_ip_fsys_ctrl
,
581 .ctrlbit
= (1 << 13),
584 .devname
= "s3c64xx-spi.0",
585 .enable
= exynos4_clk_ip_peril_ctrl
,
586 .ctrlbit
= (1 << 16),
589 .devname
= "s3c64xx-spi.1",
590 .enable
= exynos4_clk_ip_peril_ctrl
,
591 .ctrlbit
= (1 << 17),
594 .devname
= "s3c64xx-spi.2",
595 .enable
= exynos4_clk_ip_peril_ctrl
,
596 .ctrlbit
= (1 << 18),
599 .devname
= "samsung-i2s.0",
600 .enable
= exynos4_clk_ip_peril_ctrl
,
601 .ctrlbit
= (1 << 19),
604 .devname
= "samsung-i2s.1",
605 .enable
= exynos4_clk_ip_peril_ctrl
,
606 .ctrlbit
= (1 << 20),
609 .devname
= "samsung-i2s.2",
610 .enable
= exynos4_clk_ip_peril_ctrl
,
611 .ctrlbit
= (1 << 21),
614 .devname
= "samsung-ac97",
615 .enable
= exynos4_clk_ip_peril_ctrl
,
616 .ctrlbit
= (1 << 27),
619 .enable
= exynos4_clk_ip_image_ctrl
,
623 .devname
= "s5p-mfc",
624 .enable
= exynos4_clk_ip_mfc_ctrl
,
628 .devname
= "s3c2440-i2c.0",
629 .parent
= &exynos4_clk_aclk_100
.clk
,
630 .enable
= exynos4_clk_ip_peril_ctrl
,
634 .devname
= "s3c2440-i2c.1",
635 .parent
= &exynos4_clk_aclk_100
.clk
,
636 .enable
= exynos4_clk_ip_peril_ctrl
,
640 .devname
= "s3c2440-i2c.2",
641 .parent
= &exynos4_clk_aclk_100
.clk
,
642 .enable
= exynos4_clk_ip_peril_ctrl
,
646 .devname
= "s3c2440-i2c.3",
647 .parent
= &exynos4_clk_aclk_100
.clk
,
648 .enable
= exynos4_clk_ip_peril_ctrl
,
652 .devname
= "s3c2440-i2c.4",
653 .parent
= &exynos4_clk_aclk_100
.clk
,
654 .enable
= exynos4_clk_ip_peril_ctrl
,
655 .ctrlbit
= (1 << 10),
658 .devname
= "s3c2440-i2c.5",
659 .parent
= &exynos4_clk_aclk_100
.clk
,
660 .enable
= exynos4_clk_ip_peril_ctrl
,
661 .ctrlbit
= (1 << 11),
664 .devname
= "s3c2440-i2c.6",
665 .parent
= &exynos4_clk_aclk_100
.clk
,
666 .enable
= exynos4_clk_ip_peril_ctrl
,
667 .ctrlbit
= (1 << 12),
670 .devname
= "s3c2440-i2c.7",
671 .parent
= &exynos4_clk_aclk_100
.clk
,
672 .enable
= exynos4_clk_ip_peril_ctrl
,
673 .ctrlbit
= (1 << 13),
676 .devname
= "s3c2440-hdmiphy-i2c",
677 .parent
= &exynos4_clk_aclk_100
.clk
,
678 .enable
= exynos4_clk_ip_peril_ctrl
,
679 .ctrlbit
= (1 << 14),
681 .name
= "SYSMMU_MDMA",
682 .enable
= exynos4_clk_ip_image_ctrl
,
685 .name
= "SYSMMU_FIMC0",
686 .enable
= exynos4_clk_ip_cam_ctrl
,
689 .name
= "SYSMMU_FIMC1",
690 .enable
= exynos4_clk_ip_cam_ctrl
,
693 .name
= "SYSMMU_FIMC2",
694 .enable
= exynos4_clk_ip_cam_ctrl
,
697 .name
= "SYSMMU_FIMC3",
698 .enable
= exynos4_clk_ip_cam_ctrl
,
699 .ctrlbit
= (1 << 10),
701 .name
= "SYSMMU_JPEG",
702 .enable
= exynos4_clk_ip_cam_ctrl
,
703 .ctrlbit
= (1 << 11),
705 .name
= "SYSMMU_FIMD0",
706 .enable
= exynos4_clk_ip_lcd0_ctrl
,
709 .name
= "SYSMMU_FIMD1",
710 .enable
= exynos4_clk_ip_lcd1_ctrl
,
713 .name
= "SYSMMU_PCIe",
714 .enable
= exynos4_clk_ip_fsys_ctrl
,
715 .ctrlbit
= (1 << 18),
717 .name
= "SYSMMU_G2D",
718 .enable
= exynos4_clk_ip_image_ctrl
,
721 .name
= "SYSMMU_ROTATOR",
722 .enable
= exynos4_clk_ip_image_ctrl
,
726 .enable
= exynos4_clk_ip_tv_ctrl
,
729 .name
= "SYSMMU_MFC_L",
730 .enable
= exynos4_clk_ip_mfc_ctrl
,
733 .name
= "SYSMMU_MFC_R",
734 .enable
= exynos4_clk_ip_mfc_ctrl
,
739 static struct clk exynos4_init_clocks_on
[] = {
742 .devname
= "s5pv210-uart.0",
743 .enable
= exynos4_clk_ip_peril_ctrl
,
747 .devname
= "s5pv210-uart.1",
748 .enable
= exynos4_clk_ip_peril_ctrl
,
752 .devname
= "s5pv210-uart.2",
753 .enable
= exynos4_clk_ip_peril_ctrl
,
757 .devname
= "s5pv210-uart.3",
758 .enable
= exynos4_clk_ip_peril_ctrl
,
762 .devname
= "s5pv210-uart.4",
763 .enable
= exynos4_clk_ip_peril_ctrl
,
767 .devname
= "s5pv210-uart.5",
768 .enable
= exynos4_clk_ip_peril_ctrl
,
773 static struct clk exynos4_clk_pdma0
= {
775 .devname
= "dma-pl330.0",
776 .enable
= exynos4_clk_ip_fsys_ctrl
,
780 static struct clk exynos4_clk_pdma1
= {
782 .devname
= "dma-pl330.1",
783 .enable
= exynos4_clk_ip_fsys_ctrl
,
787 static struct clk exynos4_clk_mdma1
= {
789 .devname
= "dma-pl330.2",
790 .enable
= exynos4_clk_ip_image_ctrl
,
791 .ctrlbit
= ((1 << 8) | (1 << 5) | (1 << 2)),
794 static struct clk exynos4_clk_fimd0
= {
796 .devname
= "exynos4-fb.0",
797 .enable
= exynos4_clk_ip_lcd0_ctrl
,
801 struct clk
*exynos4_clkset_group_list
[] = {
802 [0] = &clk_ext_xtal_mux
,
804 [2] = &exynos4_clk_sclk_hdmi27m
,
805 [3] = &exynos4_clk_sclk_usbphy0
,
806 [4] = &exynos4_clk_sclk_usbphy1
,
807 [5] = &exynos4_clk_sclk_hdmiphy
,
808 [6] = &exynos4_clk_mout_mpll
.clk
,
809 [7] = &exynos4_clk_mout_epll
.clk
,
810 [8] = &exynos4_clk_sclk_vpll
.clk
,
813 struct clksrc_sources exynos4_clkset_group
= {
814 .sources
= exynos4_clkset_group_list
,
815 .nr_sources
= ARRAY_SIZE(exynos4_clkset_group_list
),
818 static struct clk
*exynos4_clkset_mout_g2d0_list
[] = {
819 [0] = &exynos4_clk_mout_mpll
.clk
,
820 [1] = &exynos4_clk_sclk_apll
.clk
,
823 static struct clksrc_sources exynos4_clkset_mout_g2d0
= {
824 .sources
= exynos4_clkset_mout_g2d0_list
,
825 .nr_sources
= ARRAY_SIZE(exynos4_clkset_mout_g2d0_list
),
828 static struct clksrc_clk exynos4_clk_mout_g2d0
= {
832 .sources
= &exynos4_clkset_mout_g2d0
,
833 .reg_src
= { .reg
= EXYNOS4_CLKSRC_IMAGE
, .shift
= 0, .size
= 1 },
836 static struct clk
*exynos4_clkset_mout_g2d1_list
[] = {
837 [0] = &exynos4_clk_mout_epll
.clk
,
838 [1] = &exynos4_clk_sclk_vpll
.clk
,
841 static struct clksrc_sources exynos4_clkset_mout_g2d1
= {
842 .sources
= exynos4_clkset_mout_g2d1_list
,
843 .nr_sources
= ARRAY_SIZE(exynos4_clkset_mout_g2d1_list
),
846 static struct clksrc_clk exynos4_clk_mout_g2d1
= {
850 .sources
= &exynos4_clkset_mout_g2d1
,
851 .reg_src
= { .reg
= EXYNOS4_CLKSRC_IMAGE
, .shift
= 4, .size
= 1 },
854 static struct clk
*exynos4_clkset_mout_g2d_list
[] = {
855 [0] = &exynos4_clk_mout_g2d0
.clk
,
856 [1] = &exynos4_clk_mout_g2d1
.clk
,
859 static struct clksrc_sources exynos4_clkset_mout_g2d
= {
860 .sources
= exynos4_clkset_mout_g2d_list
,
861 .nr_sources
= ARRAY_SIZE(exynos4_clkset_mout_g2d_list
),
864 static struct clk
*exynos4_clkset_mout_mfc0_list
[] = {
865 [0] = &exynos4_clk_mout_mpll
.clk
,
866 [1] = &exynos4_clk_sclk_apll
.clk
,
869 static struct clksrc_sources exynos4_clkset_mout_mfc0
= {
870 .sources
= exynos4_clkset_mout_mfc0_list
,
871 .nr_sources
= ARRAY_SIZE(exynos4_clkset_mout_mfc0_list
),
874 static struct clksrc_clk exynos4_clk_mout_mfc0
= {
878 .sources
= &exynos4_clkset_mout_mfc0
,
879 .reg_src
= { .reg
= EXYNOS4_CLKSRC_MFC
, .shift
= 0, .size
= 1 },
882 static struct clk
*exynos4_clkset_mout_mfc1_list
[] = {
883 [0] = &exynos4_clk_mout_epll
.clk
,
884 [1] = &exynos4_clk_sclk_vpll
.clk
,
887 static struct clksrc_sources exynos4_clkset_mout_mfc1
= {
888 .sources
= exynos4_clkset_mout_mfc1_list
,
889 .nr_sources
= ARRAY_SIZE(exynos4_clkset_mout_mfc1_list
),
892 static struct clksrc_clk exynos4_clk_mout_mfc1
= {
896 .sources
= &exynos4_clkset_mout_mfc1
,
897 .reg_src
= { .reg
= EXYNOS4_CLKSRC_MFC
, .shift
= 4, .size
= 1 },
900 static struct clk
*exynos4_clkset_mout_mfc_list
[] = {
901 [0] = &exynos4_clk_mout_mfc0
.clk
,
902 [1] = &exynos4_clk_mout_mfc1
.clk
,
905 static struct clksrc_sources exynos4_clkset_mout_mfc
= {
906 .sources
= exynos4_clkset_mout_mfc_list
,
907 .nr_sources
= ARRAY_SIZE(exynos4_clkset_mout_mfc_list
),
910 static struct clk
*exynos4_clkset_sclk_dac_list
[] = {
911 [0] = &exynos4_clk_sclk_vpll
.clk
,
912 [1] = &exynos4_clk_sclk_hdmiphy
,
915 static struct clksrc_sources exynos4_clkset_sclk_dac
= {
916 .sources
= exynos4_clkset_sclk_dac_list
,
917 .nr_sources
= ARRAY_SIZE(exynos4_clkset_sclk_dac_list
),
920 static struct clksrc_clk exynos4_clk_sclk_dac
= {
923 .enable
= exynos4_clksrc_mask_tv_ctrl
,
926 .sources
= &exynos4_clkset_sclk_dac
,
927 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TV
, .shift
= 8, .size
= 1 },
930 static struct clksrc_clk exynos4_clk_sclk_pixel
= {
932 .name
= "sclk_pixel",
933 .parent
= &exynos4_clk_sclk_vpll
.clk
,
935 .reg_div
= { .reg
= EXYNOS4_CLKDIV_TV
, .shift
= 0, .size
= 4 },
938 static struct clk
*exynos4_clkset_sclk_hdmi_list
[] = {
939 [0] = &exynos4_clk_sclk_pixel
.clk
,
940 [1] = &exynos4_clk_sclk_hdmiphy
,
943 static struct clksrc_sources exynos4_clkset_sclk_hdmi
= {
944 .sources
= exynos4_clkset_sclk_hdmi_list
,
945 .nr_sources
= ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list
),
948 static struct clksrc_clk exynos4_clk_sclk_hdmi
= {
951 .enable
= exynos4_clksrc_mask_tv_ctrl
,
954 .sources
= &exynos4_clkset_sclk_hdmi
,
955 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TV
, .shift
= 0, .size
= 1 },
958 static struct clk
*exynos4_clkset_sclk_mixer_list
[] = {
959 [0] = &exynos4_clk_sclk_dac
.clk
,
960 [1] = &exynos4_clk_sclk_hdmi
.clk
,
963 static struct clksrc_sources exynos4_clkset_sclk_mixer
= {
964 .sources
= exynos4_clkset_sclk_mixer_list
,
965 .nr_sources
= ARRAY_SIZE(exynos4_clkset_sclk_mixer_list
),
968 static struct clksrc_clk exynos4_clk_sclk_mixer
= {
970 .name
= "sclk_mixer",
971 .enable
= exynos4_clksrc_mask_tv_ctrl
,
974 .sources
= &exynos4_clkset_sclk_mixer
,
975 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TV
, .shift
= 4, .size
= 1 },
978 static struct clksrc_clk
*exynos4_sclk_tv
[] = {
979 &exynos4_clk_sclk_dac
,
980 &exynos4_clk_sclk_pixel
,
981 &exynos4_clk_sclk_hdmi
,
982 &exynos4_clk_sclk_mixer
,
985 static struct clksrc_clk exynos4_clk_dout_mmc0
= {
989 .sources
= &exynos4_clkset_group
,
990 .reg_src
= { .reg
= EXYNOS4_CLKSRC_FSYS
, .shift
= 0, .size
= 4 },
991 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS1
, .shift
= 0, .size
= 4 },
994 static struct clksrc_clk exynos4_clk_dout_mmc1
= {
998 .sources
= &exynos4_clkset_group
,
999 .reg_src
= { .reg
= EXYNOS4_CLKSRC_FSYS
, .shift
= 4, .size
= 4 },
1000 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS1
, .shift
= 16, .size
= 4 },
1003 static struct clksrc_clk exynos4_clk_dout_mmc2
= {
1005 .name
= "dout_mmc2",
1007 .sources
= &exynos4_clkset_group
,
1008 .reg_src
= { .reg
= EXYNOS4_CLKSRC_FSYS
, .shift
= 8, .size
= 4 },
1009 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS2
, .shift
= 0, .size
= 4 },
1012 static struct clksrc_clk exynos4_clk_dout_mmc3
= {
1014 .name
= "dout_mmc3",
1016 .sources
= &exynos4_clkset_group
,
1017 .reg_src
= { .reg
= EXYNOS4_CLKSRC_FSYS
, .shift
= 12, .size
= 4 },
1018 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS2
, .shift
= 16, .size
= 4 },
1021 static struct clksrc_clk exynos4_clk_dout_mmc4
= {
1023 .name
= "dout_mmc4",
1025 .sources
= &exynos4_clkset_group
,
1026 .reg_src
= { .reg
= EXYNOS4_CLKSRC_FSYS
, .shift
= 16, .size
= 4 },
1027 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS3
, .shift
= 0, .size
= 4 },
1030 static struct clksrc_clk exynos4_clksrcs
[] = {
1034 .enable
= exynos4_clksrc_mask_peril0_ctrl
,
1035 .ctrlbit
= (1 << 24),
1037 .sources
= &exynos4_clkset_group
,
1038 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL0
, .shift
= 24, .size
= 4 },
1039 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL3
, .shift
= 0, .size
= 4 },
1042 .name
= "sclk_csis",
1043 .devname
= "s5p-mipi-csis.0",
1044 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1045 .ctrlbit
= (1 << 24),
1047 .sources
= &exynos4_clkset_group
,
1048 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 24, .size
= 4 },
1049 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 24, .size
= 4 },
1052 .name
= "sclk_csis",
1053 .devname
= "s5p-mipi-csis.1",
1054 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1055 .ctrlbit
= (1 << 28),
1057 .sources
= &exynos4_clkset_group
,
1058 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 28, .size
= 4 },
1059 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 28, .size
= 4 },
1062 .name
= "sclk_cam0",
1063 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1064 .ctrlbit
= (1 << 16),
1066 .sources
= &exynos4_clkset_group
,
1067 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 16, .size
= 4 },
1068 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 16, .size
= 4 },
1071 .name
= "sclk_cam1",
1072 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1073 .ctrlbit
= (1 << 20),
1075 .sources
= &exynos4_clkset_group
,
1076 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 20, .size
= 4 },
1077 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 20, .size
= 4 },
1080 .name
= "sclk_fimc",
1081 .devname
= "exynos4-fimc.0",
1082 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1083 .ctrlbit
= (1 << 0),
1085 .sources
= &exynos4_clkset_group
,
1086 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 0, .size
= 4 },
1087 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 0, .size
= 4 },
1090 .name
= "sclk_fimc",
1091 .devname
= "exynos4-fimc.1",
1092 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1093 .ctrlbit
= (1 << 4),
1095 .sources
= &exynos4_clkset_group
,
1096 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 4, .size
= 4 },
1097 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 4, .size
= 4 },
1100 .name
= "sclk_fimc",
1101 .devname
= "exynos4-fimc.2",
1102 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1103 .ctrlbit
= (1 << 8),
1105 .sources
= &exynos4_clkset_group
,
1106 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 8, .size
= 4 },
1107 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 8, .size
= 4 },
1110 .name
= "sclk_fimc",
1111 .devname
= "exynos4-fimc.3",
1112 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1113 .ctrlbit
= (1 << 12),
1115 .sources
= &exynos4_clkset_group
,
1116 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 12, .size
= 4 },
1117 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 12, .size
= 4 },
1120 .name
= "sclk_fimd",
1121 .devname
= "exynos4-fb.0",
1122 .enable
= exynos4_clksrc_mask_lcd0_ctrl
,
1123 .ctrlbit
= (1 << 0),
1125 .sources
= &exynos4_clkset_group
,
1126 .reg_src
= { .reg
= EXYNOS4_CLKSRC_LCD0
, .shift
= 0, .size
= 4 },
1127 .reg_div
= { .reg
= EXYNOS4_CLKDIV_LCD0
, .shift
= 0, .size
= 4 },
1130 .name
= "sclk_fimg2d",
1132 .sources
= &exynos4_clkset_mout_g2d
,
1133 .reg_src
= { .reg
= EXYNOS4_CLKSRC_IMAGE
, .shift
= 8, .size
= 1 },
1134 .reg_div
= { .reg
= EXYNOS4_CLKDIV_IMAGE
, .shift
= 0, .size
= 4 },
1138 .devname
= "s5p-mfc",
1140 .sources
= &exynos4_clkset_mout_mfc
,
1141 .reg_src
= { .reg
= EXYNOS4_CLKSRC_MFC
, .shift
= 8, .size
= 1 },
1142 .reg_div
= { .reg
= EXYNOS4_CLKDIV_MFC
, .shift
= 0, .size
= 4 },
1145 .name
= "sclk_dwmmc",
1146 .parent
= &exynos4_clk_dout_mmc4
.clk
,
1147 .enable
= exynos4_clksrc_mask_fsys_ctrl
,
1148 .ctrlbit
= (1 << 16),
1150 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS3
, .shift
= 8, .size
= 8 },
1154 static struct clksrc_clk exynos4_clk_sclk_uart0
= {
1157 .devname
= "exynos4210-uart.0",
1158 .enable
= exynos4_clksrc_mask_peril0_ctrl
,
1159 .ctrlbit
= (1 << 0),
1161 .sources
= &exynos4_clkset_group
,
1162 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL0
, .shift
= 0, .size
= 4 },
1163 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL0
, .shift
= 0, .size
= 4 },
1166 static struct clksrc_clk exynos4_clk_sclk_uart1
= {
1169 .devname
= "exynos4210-uart.1",
1170 .enable
= exynos4_clksrc_mask_peril0_ctrl
,
1171 .ctrlbit
= (1 << 4),
1173 .sources
= &exynos4_clkset_group
,
1174 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL0
, .shift
= 4, .size
= 4 },
1175 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL0
, .shift
= 4, .size
= 4 },
1178 static struct clksrc_clk exynos4_clk_sclk_uart2
= {
1181 .devname
= "exynos4210-uart.2",
1182 .enable
= exynos4_clksrc_mask_peril0_ctrl
,
1183 .ctrlbit
= (1 << 8),
1185 .sources
= &exynos4_clkset_group
,
1186 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL0
, .shift
= 8, .size
= 4 },
1187 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL0
, .shift
= 8, .size
= 4 },
1190 static struct clksrc_clk exynos4_clk_sclk_uart3
= {
1193 .devname
= "exynos4210-uart.3",
1194 .enable
= exynos4_clksrc_mask_peril0_ctrl
,
1195 .ctrlbit
= (1 << 12),
1197 .sources
= &exynos4_clkset_group
,
1198 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL0
, .shift
= 12, .size
= 4 },
1199 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL0
, .shift
= 12, .size
= 4 },
1202 static struct clksrc_clk exynos4_clk_sclk_mmc0
= {
1205 .devname
= "s3c-sdhci.0",
1206 .parent
= &exynos4_clk_dout_mmc0
.clk
,
1207 .enable
= exynos4_clksrc_mask_fsys_ctrl
,
1208 .ctrlbit
= (1 << 0),
1210 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS1
, .shift
= 8, .size
= 8 },
1213 static struct clksrc_clk exynos4_clk_sclk_mmc1
= {
1216 .devname
= "s3c-sdhci.1",
1217 .parent
= &exynos4_clk_dout_mmc1
.clk
,
1218 .enable
= exynos4_clksrc_mask_fsys_ctrl
,
1219 .ctrlbit
= (1 << 4),
1221 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS1
, .shift
= 24, .size
= 8 },
1224 static struct clksrc_clk exynos4_clk_sclk_mmc2
= {
1227 .devname
= "s3c-sdhci.2",
1228 .parent
= &exynos4_clk_dout_mmc2
.clk
,
1229 .enable
= exynos4_clksrc_mask_fsys_ctrl
,
1230 .ctrlbit
= (1 << 8),
1232 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS2
, .shift
= 8, .size
= 8 },
1235 static struct clksrc_clk exynos4_clk_sclk_mmc3
= {
1238 .devname
= "s3c-sdhci.3",
1239 .parent
= &exynos4_clk_dout_mmc3
.clk
,
1240 .enable
= exynos4_clksrc_mask_fsys_ctrl
,
1241 .ctrlbit
= (1 << 12),
1243 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS2
, .shift
= 24, .size
= 8 },
1246 static struct clksrc_clk exynos4_clk_sclk_spi0
= {
1249 .devname
= "s3c64xx-spi.0",
1250 .enable
= exynos4_clksrc_mask_peril1_ctrl
,
1251 .ctrlbit
= (1 << 16),
1253 .sources
= &exynos4_clkset_group
,
1254 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL1
, .shift
= 16, .size
= 4 },
1255 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL1
, .shift
= 0, .size
= 4 },
1258 static struct clksrc_clk exynos4_clk_sclk_spi1
= {
1261 .devname
= "s3c64xx-spi.1",
1262 .enable
= exynos4_clksrc_mask_peril1_ctrl
,
1263 .ctrlbit
= (1 << 20),
1265 .sources
= &exynos4_clkset_group
,
1266 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL1
, .shift
= 20, .size
= 4 },
1267 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL1
, .shift
= 16, .size
= 4 },
1270 static struct clksrc_clk exynos4_clk_sclk_spi2
= {
1273 .devname
= "s3c64xx-spi.2",
1274 .enable
= exynos4_clksrc_mask_peril1_ctrl
,
1275 .ctrlbit
= (1 << 24),
1277 .sources
= &exynos4_clkset_group
,
1278 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL1
, .shift
= 24, .size
= 4 },
1279 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL2
, .shift
= 0, .size
= 4 },
1282 /* Clock initialization code */
1283 static struct clksrc_clk
*exynos4_sysclks
[] = {
1284 &exynos4_clk_mout_apll
,
1285 &exynos4_clk_sclk_apll
,
1286 &exynos4_clk_mout_epll
,
1287 &exynos4_clk_mout_mpll
,
1288 &exynos4_clk_moutcore
,
1289 &exynos4_clk_coreclk
,
1290 &exynos4_clk_armclk
,
1291 &exynos4_clk_aclk_corem0
,
1292 &exynos4_clk_aclk_cores
,
1293 &exynos4_clk_aclk_corem1
,
1294 &exynos4_clk_periphclk
,
1295 &exynos4_clk_mout_corebus
,
1296 &exynos4_clk_sclk_dmc
,
1297 &exynos4_clk_aclk_cored
,
1298 &exynos4_clk_aclk_corep
,
1299 &exynos4_clk_aclk_acp
,
1300 &exynos4_clk_pclk_acp
,
1301 &exynos4_clk_vpllsrc
,
1302 &exynos4_clk_sclk_vpll
,
1303 &exynos4_clk_aclk_200
,
1304 &exynos4_clk_aclk_100
,
1305 &exynos4_clk_aclk_160
,
1306 &exynos4_clk_aclk_133
,
1307 &exynos4_clk_dout_mmc0
,
1308 &exynos4_clk_dout_mmc1
,
1309 &exynos4_clk_dout_mmc2
,
1310 &exynos4_clk_dout_mmc3
,
1311 &exynos4_clk_dout_mmc4
,
1312 &exynos4_clk_mout_mfc0
,
1313 &exynos4_clk_mout_mfc1
,
1316 static struct clk
*exynos4_clk_cdev
[] = {
1323 static struct clksrc_clk
*exynos4_clksrc_cdev
[] = {
1324 &exynos4_clk_sclk_uart0
,
1325 &exynos4_clk_sclk_uart1
,
1326 &exynos4_clk_sclk_uart2
,
1327 &exynos4_clk_sclk_uart3
,
1328 &exynos4_clk_sclk_mmc0
,
1329 &exynos4_clk_sclk_mmc1
,
1330 &exynos4_clk_sclk_mmc2
,
1331 &exynos4_clk_sclk_mmc3
,
1332 &exynos4_clk_sclk_spi0
,
1333 &exynos4_clk_sclk_spi1
,
1334 &exynos4_clk_sclk_spi2
,
1338 static struct clk_lookup exynos4_clk_lookup
[] = {
1339 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0
.clk
),
1340 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1
.clk
),
1341 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2
.clk
),
1342 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3
.clk
),
1343 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0
.clk
),
1344 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1
.clk
),
1345 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2
.clk
),
1346 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3
.clk
),
1347 CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0
),
1348 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0
),
1349 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1
),
1350 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1
),
1351 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0
.clk
),
1352 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1
.clk
),
1353 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2
.clk
),
1356 static int xtal_rate
;
1358 static unsigned long exynos4_fout_apll_get_rate(struct clk
*clk
)
1360 if (soc_is_exynos4210())
1361 return s5p_get_pll45xx(xtal_rate
, __raw_readl(EXYNOS4_APLL_CON0
),
1363 else if (soc_is_exynos4212() || soc_is_exynos4412())
1364 return s5p_get_pll35xx(xtal_rate
, __raw_readl(EXYNOS4_APLL_CON0
));
1369 static struct clk_ops exynos4_fout_apll_ops
= {
1370 .get_rate
= exynos4_fout_apll_get_rate
,
1373 static u32 exynos4_vpll_div
[][8] = {
1374 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1375 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1378 static unsigned long exynos4_vpll_get_rate(struct clk
*clk
)
1383 static int exynos4_vpll_set_rate(struct clk
*clk
, unsigned long rate
)
1385 unsigned int vpll_con0
, vpll_con1
= 0;
1388 /* Return if nothing changed */
1389 if (clk
->rate
== rate
)
1392 vpll_con0
= __raw_readl(EXYNOS4_VPLL_CON0
);
1393 vpll_con0
&= ~(0x1 << 27 | \
1394 PLL90XX_MDIV_MASK
<< PLL46XX_MDIV_SHIFT
| \
1395 PLL90XX_PDIV_MASK
<< PLL46XX_PDIV_SHIFT
| \
1396 PLL90XX_SDIV_MASK
<< PLL46XX_SDIV_SHIFT
);
1398 vpll_con1
= __raw_readl(EXYNOS4_VPLL_CON1
);
1399 vpll_con1
&= ~(PLL46XX_MRR_MASK
<< PLL46XX_MRR_SHIFT
| \
1400 PLL46XX_MFR_MASK
<< PLL46XX_MFR_SHIFT
| \
1401 PLL4650C_KDIV_MASK
<< PLL46XX_KDIV_SHIFT
);
1403 for (i
= 0; i
< ARRAY_SIZE(exynos4_vpll_div
); i
++) {
1404 if (exynos4_vpll_div
[i
][0] == rate
) {
1405 vpll_con0
|= exynos4_vpll_div
[i
][1] << PLL46XX_PDIV_SHIFT
;
1406 vpll_con0
|= exynos4_vpll_div
[i
][2] << PLL46XX_MDIV_SHIFT
;
1407 vpll_con0
|= exynos4_vpll_div
[i
][3] << PLL46XX_SDIV_SHIFT
;
1408 vpll_con1
|= exynos4_vpll_div
[i
][4] << PLL46XX_KDIV_SHIFT
;
1409 vpll_con1
|= exynos4_vpll_div
[i
][5] << PLL46XX_MFR_SHIFT
;
1410 vpll_con1
|= exynos4_vpll_div
[i
][6] << PLL46XX_MRR_SHIFT
;
1411 vpll_con0
|= exynos4_vpll_div
[i
][7] << 27;
1416 if (i
== ARRAY_SIZE(exynos4_vpll_div
)) {
1417 printk(KERN_ERR
"%s: Invalid Clock VPLL Frequency\n",
1422 __raw_writel(vpll_con0
, EXYNOS4_VPLL_CON0
);
1423 __raw_writel(vpll_con1
, EXYNOS4_VPLL_CON1
);
1425 /* Wait for VPLL lock */
1426 while (!(__raw_readl(EXYNOS4_VPLL_CON0
) & (1 << PLL46XX_LOCKED_SHIFT
)))
1433 static struct clk_ops exynos4_vpll_ops
= {
1434 .get_rate
= exynos4_vpll_get_rate
,
1435 .set_rate
= exynos4_vpll_set_rate
,
1438 void __init_or_cpufreq
exynos4_setup_clocks(void)
1440 struct clk
*xtal_clk
;
1441 unsigned long apll
= 0;
1442 unsigned long mpll
= 0;
1443 unsigned long epll
= 0;
1444 unsigned long vpll
= 0;
1445 unsigned long vpllsrc
;
1447 unsigned long armclk
;
1448 unsigned long sclk_dmc
;
1449 unsigned long aclk_200
;
1450 unsigned long aclk_100
;
1451 unsigned long aclk_160
;
1452 unsigned long aclk_133
;
1455 printk(KERN_DEBUG
"%s: registering clocks\n", __func__
);
1457 xtal_clk
= clk_get(NULL
, "xtal");
1458 BUG_ON(IS_ERR(xtal_clk
));
1460 xtal
= clk_get_rate(xtal_clk
);
1466 printk(KERN_DEBUG
"%s: xtal is %ld\n", __func__
, xtal
);
1468 if (soc_is_exynos4210()) {
1469 apll
= s5p_get_pll45xx(xtal
, __raw_readl(EXYNOS4_APLL_CON0
),
1471 mpll
= s5p_get_pll45xx(xtal
, __raw_readl(EXYNOS4_MPLL_CON0
),
1473 epll
= s5p_get_pll46xx(xtal
, __raw_readl(EXYNOS4_EPLL_CON0
),
1474 __raw_readl(EXYNOS4_EPLL_CON1
), pll_4600
);
1476 vpllsrc
= clk_get_rate(&exynos4_clk_vpllsrc
.clk
);
1477 vpll
= s5p_get_pll46xx(vpllsrc
, __raw_readl(EXYNOS4_VPLL_CON0
),
1478 __raw_readl(EXYNOS4_VPLL_CON1
), pll_4650c
);
1479 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1480 apll
= s5p_get_pll35xx(xtal
, __raw_readl(EXYNOS4_APLL_CON0
));
1481 mpll
= s5p_get_pll35xx(xtal
, __raw_readl(EXYNOS4_MPLL_CON0
));
1482 epll
= s5p_get_pll36xx(xtal
, __raw_readl(EXYNOS4_EPLL_CON0
),
1483 __raw_readl(EXYNOS4_EPLL_CON1
));
1485 vpllsrc
= clk_get_rate(&exynos4_clk_vpllsrc
.clk
);
1486 vpll
= s5p_get_pll36xx(vpllsrc
, __raw_readl(EXYNOS4_VPLL_CON0
),
1487 __raw_readl(EXYNOS4_VPLL_CON1
));
1492 clk_fout_apll
.ops
= &exynos4_fout_apll_ops
;
1493 clk_fout_mpll
.rate
= mpll
;
1494 clk_fout_epll
.rate
= epll
;
1495 clk_fout_vpll
.ops
= &exynos4_vpll_ops
;
1496 clk_fout_vpll
.rate
= vpll
;
1498 printk(KERN_INFO
"EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1499 apll
, mpll
, epll
, vpll
);
1501 armclk
= clk_get_rate(&exynos4_clk_armclk
.clk
);
1502 sclk_dmc
= clk_get_rate(&exynos4_clk_sclk_dmc
.clk
);
1504 aclk_200
= clk_get_rate(&exynos4_clk_aclk_200
.clk
);
1505 aclk_100
= clk_get_rate(&exynos4_clk_aclk_100
.clk
);
1506 aclk_160
= clk_get_rate(&exynos4_clk_aclk_160
.clk
);
1507 aclk_133
= clk_get_rate(&exynos4_clk_aclk_133
.clk
);
1509 printk(KERN_INFO
"EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1510 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1511 armclk
, sclk_dmc
, aclk_200
,
1512 aclk_100
, aclk_160
, aclk_133
);
1514 clk_f
.rate
= armclk
;
1515 clk_h
.rate
= sclk_dmc
;
1516 clk_p
.rate
= aclk_100
;
1518 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos4_clksrcs
); ptr
++)
1519 s3c_set_clksrc(&exynos4_clksrcs
[ptr
], true);
1522 static struct clk
*exynos4_clks
[] __initdata
= {
1523 &exynos4_clk_sclk_hdmi27m
,
1524 &exynos4_clk_sclk_hdmiphy
,
1525 &exynos4_clk_sclk_usbphy0
,
1526 &exynos4_clk_sclk_usbphy1
,
1529 #ifdef CONFIG_PM_SLEEP
1530 static int exynos4_clock_suspend(void)
1532 s3c_pm_do_save(exynos4_clock_save
, ARRAY_SIZE(exynos4_clock_save
));
1536 static void exynos4_clock_resume(void)
1538 s3c_pm_do_restore_core(exynos4_clock_save
, ARRAY_SIZE(exynos4_clock_save
));
1542 #define exynos4_clock_suspend NULL
1543 #define exynos4_clock_resume NULL
1546 static struct syscore_ops exynos4_clock_syscore_ops
= {
1547 .suspend
= exynos4_clock_suspend
,
1548 .resume
= exynos4_clock_resume
,
1551 void __init
exynos4_register_clocks(void)
1555 s3c24xx_register_clocks(exynos4_clks
, ARRAY_SIZE(exynos4_clks
));
1557 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos4_sysclks
); ptr
++)
1558 s3c_register_clksrc(exynos4_sysclks
[ptr
], 1);
1560 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos4_sclk_tv
); ptr
++)
1561 s3c_register_clksrc(exynos4_sclk_tv
[ptr
], 1);
1563 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos4_clksrc_cdev
); ptr
++)
1564 s3c_register_clksrc(exynos4_clksrc_cdev
[ptr
], 1);
1566 s3c_register_clksrc(exynos4_clksrcs
, ARRAY_SIZE(exynos4_clksrcs
));
1567 s3c_register_clocks(exynos4_init_clocks_on
, ARRAY_SIZE(exynos4_init_clocks_on
));
1569 s3c24xx_register_clocks(exynos4_clk_cdev
, ARRAY_SIZE(exynos4_clk_cdev
));
1570 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos4_clk_cdev
); ptr
++)
1571 s3c_disable_clocks(exynos4_clk_cdev
[ptr
], 1);
1573 s3c_register_clocks(exynos4_init_clocks_off
, ARRAY_SIZE(exynos4_init_clocks_off
));
1574 s3c_disable_clocks(exynos4_init_clocks_off
, ARRAY_SIZE(exynos4_init_clocks_off
));
1575 clkdev_add_table(exynos4_clk_lookup
, ARRAY_SIZE(exynos4_clk_lookup
));
1577 register_syscore_ops(&exynos4_clock_syscore_ops
);
1578 s3c24xx_register_clock(&dummy_apb_pclk
);