2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS4 - Clock support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/err.h>
15 #include <linux/syscore_ops.h>
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
26 #include <mach/regs-clock.h>
27 #include <mach/sysmmu.h>
30 #include "clock-exynos4.h"
32 #ifdef CONFIG_PM_SLEEP
33 static struct sleep_save exynos4_clock_save
[] = {
34 SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS
),
35 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS
),
36 SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS
),
37 SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS
),
38 SAVE_ITEM(EXYNOS4_CLKSRC_TOP0
),
39 SAVE_ITEM(EXYNOS4_CLKSRC_TOP1
),
40 SAVE_ITEM(EXYNOS4_CLKSRC_CAM
),
41 SAVE_ITEM(EXYNOS4_CLKSRC_TV
),
42 SAVE_ITEM(EXYNOS4_CLKSRC_MFC
),
43 SAVE_ITEM(EXYNOS4_CLKSRC_G3D
),
44 SAVE_ITEM(EXYNOS4_CLKSRC_LCD0
),
45 SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO
),
46 SAVE_ITEM(EXYNOS4_CLKSRC_FSYS
),
47 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0
),
48 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1
),
49 SAVE_ITEM(EXYNOS4_CLKDIV_CAM
),
50 SAVE_ITEM(EXYNOS4_CLKDIV_TV
),
51 SAVE_ITEM(EXYNOS4_CLKDIV_MFC
),
52 SAVE_ITEM(EXYNOS4_CLKDIV_G3D
),
53 SAVE_ITEM(EXYNOS4_CLKDIV_LCD0
),
54 SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO
),
55 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0
),
56 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1
),
57 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2
),
58 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3
),
59 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0
),
60 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1
),
61 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2
),
62 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3
),
63 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4
),
64 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5
),
65 SAVE_ITEM(EXYNOS4_CLKDIV_TOP
),
66 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP
),
67 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM
),
68 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV
),
69 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0
),
70 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO
),
71 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS
),
72 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0
),
73 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1
),
74 SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO
),
75 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM
),
76 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM
),
77 SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV
),
78 SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC
),
79 SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D
),
80 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0
),
81 SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS
),
82 SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS
),
83 SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL
),
84 SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK
),
85 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC
),
86 SAVE_ITEM(EXYNOS4_CLKSRC_DMC
),
87 SAVE_ITEM(EXYNOS4_CLKDIV_DMC0
),
88 SAVE_ITEM(EXYNOS4_CLKDIV_DMC1
),
89 SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC
),
90 SAVE_ITEM(EXYNOS4_CLKSRC_CPU
),
91 SAVE_ITEM(EXYNOS4_CLKDIV_CPU
),
92 SAVE_ITEM(EXYNOS4_CLKDIV_CPU
+ 0x4),
93 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU
),
94 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU
),
98 static struct clk exynos4_clk_sclk_hdmi27m
= {
99 .name
= "sclk_hdmi27m",
103 static struct clk exynos4_clk_sclk_hdmiphy
= {
104 .name
= "sclk_hdmiphy",
107 static struct clk exynos4_clk_sclk_usbphy0
= {
108 .name
= "sclk_usbphy0",
112 static struct clk exynos4_clk_sclk_usbphy1
= {
113 .name
= "sclk_usbphy1",
116 static struct clk dummy_apb_pclk
= {
121 static int exynos4_clksrc_mask_top_ctrl(struct clk
*clk
, int enable
)
123 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP
, clk
, enable
);
126 static int exynos4_clksrc_mask_cam_ctrl(struct clk
*clk
, int enable
)
128 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM
, clk
, enable
);
131 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk
*clk
, int enable
)
133 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0
, clk
, enable
);
136 int exynos4_clksrc_mask_fsys_ctrl(struct clk
*clk
, int enable
)
138 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS
, clk
, enable
);
141 static int exynos4_clksrc_mask_peril0_ctrl(struct clk
*clk
, int enable
)
143 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0
, clk
, enable
);
146 static int exynos4_clksrc_mask_peril1_ctrl(struct clk
*clk
, int enable
)
148 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1
, clk
, enable
);
151 static int exynos4_clk_ip_mfc_ctrl(struct clk
*clk
, int enable
)
153 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC
, clk
, enable
);
156 static int exynos4_clksrc_mask_tv_ctrl(struct clk
*clk
, int enable
)
158 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV
, clk
, enable
);
161 static int exynos4_clk_ip_cam_ctrl(struct clk
*clk
, int enable
)
163 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM
, clk
, enable
);
166 static int exynos4_clk_ip_tv_ctrl(struct clk
*clk
, int enable
)
168 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV
, clk
, enable
);
171 int exynos4_clk_ip_image_ctrl(struct clk
*clk
, int enable
)
173 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE
, clk
, enable
);
176 static int exynos4_clk_ip_lcd0_ctrl(struct clk
*clk
, int enable
)
178 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0
, clk
, enable
);
181 int exynos4_clk_ip_lcd1_ctrl(struct clk
*clk
, int enable
)
183 return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1
, clk
, enable
);
186 int exynos4_clk_ip_fsys_ctrl(struct clk
*clk
, int enable
)
188 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS
, clk
, enable
);
191 static int exynos4_clk_ip_peril_ctrl(struct clk
*clk
, int enable
)
193 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL
, clk
, enable
);
196 static int exynos4_clk_ip_perir_ctrl(struct clk
*clk
, int enable
)
198 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR
, clk
, enable
);
201 int exynos4_clk_ip_dmc_ctrl(struct clk
*clk
, int enable
)
203 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC
, clk
, enable
);
206 static int exynos4_clk_hdmiphy_ctrl(struct clk
*clk
, int enable
)
208 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL
, clk
, enable
);
211 static int exynos4_clk_dac_ctrl(struct clk
*clk
, int enable
)
213 return s5p_gatectrl(S5P_DAC_PHY_CONTROL
, clk
, enable
);
216 /* Core list of CMU_CPU side */
218 static struct clksrc_clk exynos4_clk_mout_apll
= {
222 .sources
= &clk_src_apll
,
223 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CPU
, .shift
= 0, .size
= 1 },
226 static struct clksrc_clk exynos4_clk_sclk_apll
= {
229 .parent
= &exynos4_clk_mout_apll
.clk
,
231 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CPU
, .shift
= 24, .size
= 3 },
234 static struct clksrc_clk exynos4_clk_mout_epll
= {
238 .sources
= &clk_src_epll
,
239 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP0
, .shift
= 4, .size
= 1 },
242 struct clksrc_clk exynos4_clk_mout_mpll
= {
246 .sources
= &clk_src_mpll
,
248 /* reg_src will be added in each SoCs' clock */
251 static struct clk
*exynos4_clkset_moutcore_list
[] = {
252 [0] = &exynos4_clk_mout_apll
.clk
,
253 [1] = &exynos4_clk_mout_mpll
.clk
,
256 static struct clksrc_sources exynos4_clkset_moutcore
= {
257 .sources
= exynos4_clkset_moutcore_list
,
258 .nr_sources
= ARRAY_SIZE(exynos4_clkset_moutcore_list
),
261 static struct clksrc_clk exynos4_clk_moutcore
= {
265 .sources
= &exynos4_clkset_moutcore
,
266 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CPU
, .shift
= 16, .size
= 1 },
269 static struct clksrc_clk exynos4_clk_coreclk
= {
272 .parent
= &exynos4_clk_moutcore
.clk
,
274 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CPU
, .shift
= 0, .size
= 3 },
277 static struct clksrc_clk exynos4_clk_armclk
= {
280 .parent
= &exynos4_clk_coreclk
.clk
,
284 static struct clksrc_clk exynos4_clk_aclk_corem0
= {
286 .name
= "aclk_corem0",
287 .parent
= &exynos4_clk_coreclk
.clk
,
289 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CPU
, .shift
= 4, .size
= 3 },
292 static struct clksrc_clk exynos4_clk_aclk_cores
= {
294 .name
= "aclk_cores",
295 .parent
= &exynos4_clk_coreclk
.clk
,
297 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CPU
, .shift
= 4, .size
= 3 },
300 static struct clksrc_clk exynos4_clk_aclk_corem1
= {
302 .name
= "aclk_corem1",
303 .parent
= &exynos4_clk_coreclk
.clk
,
305 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CPU
, .shift
= 8, .size
= 3 },
308 static struct clksrc_clk exynos4_clk_periphclk
= {
311 .parent
= &exynos4_clk_coreclk
.clk
,
313 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CPU
, .shift
= 12, .size
= 3 },
316 /* Core list of CMU_CORE side */
318 static struct clk
*exynos4_clkset_corebus_list
[] = {
319 [0] = &exynos4_clk_mout_mpll
.clk
,
320 [1] = &exynos4_clk_sclk_apll
.clk
,
323 struct clksrc_sources exynos4_clkset_mout_corebus
= {
324 .sources
= exynos4_clkset_corebus_list
,
325 .nr_sources
= ARRAY_SIZE(exynos4_clkset_corebus_list
),
328 static struct clksrc_clk exynos4_clk_mout_corebus
= {
330 .name
= "mout_corebus",
332 .sources
= &exynos4_clkset_mout_corebus
,
333 .reg_src
= { .reg
= EXYNOS4_CLKSRC_DMC
, .shift
= 4, .size
= 1 },
336 static struct clksrc_clk exynos4_clk_sclk_dmc
= {
339 .parent
= &exynos4_clk_mout_corebus
.clk
,
341 .reg_div
= { .reg
= EXYNOS4_CLKDIV_DMC0
, .shift
= 12, .size
= 3 },
344 static struct clksrc_clk exynos4_clk_aclk_cored
= {
346 .name
= "aclk_cored",
347 .parent
= &exynos4_clk_sclk_dmc
.clk
,
349 .reg_div
= { .reg
= EXYNOS4_CLKDIV_DMC0
, .shift
= 16, .size
= 3 },
352 static struct clksrc_clk exynos4_clk_aclk_corep
= {
354 .name
= "aclk_corep",
355 .parent
= &exynos4_clk_aclk_cored
.clk
,
357 .reg_div
= { .reg
= EXYNOS4_CLKDIV_DMC0
, .shift
= 20, .size
= 3 },
360 static struct clksrc_clk exynos4_clk_aclk_acp
= {
363 .parent
= &exynos4_clk_mout_corebus
.clk
,
365 .reg_div
= { .reg
= EXYNOS4_CLKDIV_DMC0
, .shift
= 0, .size
= 3 },
368 static struct clksrc_clk exynos4_clk_pclk_acp
= {
371 .parent
= &exynos4_clk_aclk_acp
.clk
,
373 .reg_div
= { .reg
= EXYNOS4_CLKDIV_DMC0
, .shift
= 4, .size
= 3 },
376 /* Core list of CMU_TOP side */
378 struct clk
*exynos4_clkset_aclk_top_list
[] = {
379 [0] = &exynos4_clk_mout_mpll
.clk
,
380 [1] = &exynos4_clk_sclk_apll
.clk
,
383 static struct clksrc_sources exynos4_clkset_aclk
= {
384 .sources
= exynos4_clkset_aclk_top_list
,
385 .nr_sources
= ARRAY_SIZE(exynos4_clkset_aclk_top_list
),
388 static struct clksrc_clk exynos4_clk_aclk_200
= {
392 .sources
= &exynos4_clkset_aclk
,
393 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP0
, .shift
= 12, .size
= 1 },
394 .reg_div
= { .reg
= EXYNOS4_CLKDIV_TOP
, .shift
= 0, .size
= 3 },
397 static struct clksrc_clk exynos4_clk_aclk_100
= {
401 .sources
= &exynos4_clkset_aclk
,
402 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP0
, .shift
= 16, .size
= 1 },
403 .reg_div
= { .reg
= EXYNOS4_CLKDIV_TOP
, .shift
= 4, .size
= 4 },
406 static struct clksrc_clk exynos4_clk_aclk_160
= {
410 .sources
= &exynos4_clkset_aclk
,
411 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP0
, .shift
= 20, .size
= 1 },
412 .reg_div
= { .reg
= EXYNOS4_CLKDIV_TOP
, .shift
= 8, .size
= 3 },
415 struct clksrc_clk exynos4_clk_aclk_133
= {
419 .sources
= &exynos4_clkset_aclk
,
420 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP0
, .shift
= 24, .size
= 1 },
421 .reg_div
= { .reg
= EXYNOS4_CLKDIV_TOP
, .shift
= 12, .size
= 3 },
424 static struct clk
*exynos4_clkset_vpllsrc_list
[] = {
426 [1] = &exynos4_clk_sclk_hdmi27m
,
429 static struct clksrc_sources exynos4_clkset_vpllsrc
= {
430 .sources
= exynos4_clkset_vpllsrc_list
,
431 .nr_sources
= ARRAY_SIZE(exynos4_clkset_vpllsrc_list
),
434 static struct clksrc_clk exynos4_clk_vpllsrc
= {
437 .enable
= exynos4_clksrc_mask_top_ctrl
,
440 .sources
= &exynos4_clkset_vpllsrc
,
441 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP1
, .shift
= 0, .size
= 1 },
444 static struct clk
*exynos4_clkset_sclk_vpll_list
[] = {
445 [0] = &exynos4_clk_vpllsrc
.clk
,
446 [1] = &clk_fout_vpll
,
449 static struct clksrc_sources exynos4_clkset_sclk_vpll
= {
450 .sources
= exynos4_clkset_sclk_vpll_list
,
451 .nr_sources
= ARRAY_SIZE(exynos4_clkset_sclk_vpll_list
),
454 static struct clksrc_clk exynos4_clk_sclk_vpll
= {
458 .sources
= &exynos4_clkset_sclk_vpll
,
459 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TOP0
, .shift
= 8, .size
= 1 },
462 static struct clk exynos4_init_clocks_off
[] = {
465 .parent
= &exynos4_clk_aclk_100
.clk
,
466 .enable
= exynos4_clk_ip_peril_ctrl
,
470 .devname
= "s5p-mipi-csis.0",
471 .enable
= exynos4_clk_ip_cam_ctrl
,
475 .devname
= "s5p-mipi-csis.1",
476 .enable
= exynos4_clk_ip_cam_ctrl
,
481 .enable
= exynos4_clk_ip_cam_ctrl
,
485 .devname
= "exynos4-fimc.0",
486 .enable
= exynos4_clk_ip_cam_ctrl
,
490 .devname
= "exynos4-fimc.1",
491 .enable
= exynos4_clk_ip_cam_ctrl
,
495 .devname
= "exynos4-fimc.2",
496 .enable
= exynos4_clk_ip_cam_ctrl
,
500 .devname
= "exynos4-fimc.3",
501 .enable
= exynos4_clk_ip_cam_ctrl
,
505 .enable
= exynos4_clk_ip_fsys_ctrl
,
509 .devname
= "exynos4-sdhci.0",
510 .parent
= &exynos4_clk_aclk_133
.clk
,
511 .enable
= exynos4_clk_ip_fsys_ctrl
,
515 .devname
= "exynos4-sdhci.1",
516 .parent
= &exynos4_clk_aclk_133
.clk
,
517 .enable
= exynos4_clk_ip_fsys_ctrl
,
521 .devname
= "exynos4-sdhci.2",
522 .parent
= &exynos4_clk_aclk_133
.clk
,
523 .enable
= exynos4_clk_ip_fsys_ctrl
,
527 .devname
= "exynos4-sdhci.3",
528 .parent
= &exynos4_clk_aclk_133
.clk
,
529 .enable
= exynos4_clk_ip_fsys_ctrl
,
533 .parent
= &exynos4_clk_aclk_133
.clk
,
534 .enable
= exynos4_clk_ip_fsys_ctrl
,
538 .enable
= exynos4_clk_ip_fsys_ctrl
,
539 .ctrlbit
= (1 << 15),
542 .enable
= exynos4_clk_ip_fsys_ctrl
,
543 .ctrlbit
= (1 << 16),
546 .devname
= "s5p-sdo",
547 .enable
= exynos4_clk_ip_tv_ctrl
,
551 .devname
= "s5p-mixer",
552 .enable
= exynos4_clk_ip_tv_ctrl
,
556 .devname
= "s5p-mixer",
557 .enable
= exynos4_clk_ip_tv_ctrl
,
561 .devname
= "exynos4-hdmi",
562 .enable
= exynos4_clk_ip_tv_ctrl
,
566 .devname
= "exynos4-hdmi",
567 .enable
= exynos4_clk_hdmiphy_ctrl
,
571 .devname
= "s5p-sdo",
572 .enable
= exynos4_clk_dac_ctrl
,
576 .enable
= exynos4_clk_ip_peril_ctrl
,
577 .ctrlbit
= (1 << 15),
580 .enable
= exynos4_clk_ip_perir_ctrl
,
581 .ctrlbit
= (1 << 17),
584 .enable
= exynos4_clk_ip_perir_ctrl
,
585 .ctrlbit
= (1 << 16),
588 .enable
= exynos4_clk_ip_perir_ctrl
,
589 .ctrlbit
= (1 << 15),
592 .parent
= &exynos4_clk_aclk_100
.clk
,
593 .enable
= exynos4_clk_ip_perir_ctrl
,
594 .ctrlbit
= (1 << 14),
597 .enable
= exynos4_clk_ip_fsys_ctrl
,
598 .ctrlbit
= (1 << 12),
601 .enable
= exynos4_clk_ip_fsys_ctrl
,
602 .ctrlbit
= (1 << 13),
605 .devname
= "exynos4210-spi.0",
606 .enable
= exynos4_clk_ip_peril_ctrl
,
607 .ctrlbit
= (1 << 16),
610 .devname
= "exynos4210-spi.1",
611 .enable
= exynos4_clk_ip_peril_ctrl
,
612 .ctrlbit
= (1 << 17),
615 .devname
= "exynos4210-spi.2",
616 .enable
= exynos4_clk_ip_peril_ctrl
,
617 .ctrlbit
= (1 << 18),
620 .devname
= "samsung-i2s.1",
621 .enable
= exynos4_clk_ip_peril_ctrl
,
622 .ctrlbit
= (1 << 20),
625 .devname
= "samsung-i2s.2",
626 .enable
= exynos4_clk_ip_peril_ctrl
,
627 .ctrlbit
= (1 << 21),
630 .devname
= "samsung-pcm.1",
631 .enable
= exynos4_clk_ip_peril_ctrl
,
632 .ctrlbit
= (1 << 22),
635 .devname
= "samsung-pcm.2",
636 .enable
= exynos4_clk_ip_peril_ctrl
,
637 .ctrlbit
= (1 << 23),
640 .enable
= exynos4_clk_ip_peril_ctrl
,
641 .ctrlbit
= (1 << 25),
644 .devname
= "samsung-spdif",
645 .enable
= exynos4_clk_ip_peril_ctrl
,
646 .ctrlbit
= (1 << 26),
649 .devname
= "samsung-ac97",
650 .enable
= exynos4_clk_ip_peril_ctrl
,
651 .ctrlbit
= (1 << 27),
654 .devname
= "s5p-mfc",
655 .enable
= exynos4_clk_ip_mfc_ctrl
,
659 .devname
= "s3c2440-i2c.0",
660 .parent
= &exynos4_clk_aclk_100
.clk
,
661 .enable
= exynos4_clk_ip_peril_ctrl
,
665 .devname
= "s3c2440-i2c.1",
666 .parent
= &exynos4_clk_aclk_100
.clk
,
667 .enable
= exynos4_clk_ip_peril_ctrl
,
671 .devname
= "s3c2440-i2c.2",
672 .parent
= &exynos4_clk_aclk_100
.clk
,
673 .enable
= exynos4_clk_ip_peril_ctrl
,
677 .devname
= "s3c2440-i2c.3",
678 .parent
= &exynos4_clk_aclk_100
.clk
,
679 .enable
= exynos4_clk_ip_peril_ctrl
,
683 .devname
= "s3c2440-i2c.4",
684 .parent
= &exynos4_clk_aclk_100
.clk
,
685 .enable
= exynos4_clk_ip_peril_ctrl
,
686 .ctrlbit
= (1 << 10),
689 .devname
= "s3c2440-i2c.5",
690 .parent
= &exynos4_clk_aclk_100
.clk
,
691 .enable
= exynos4_clk_ip_peril_ctrl
,
692 .ctrlbit
= (1 << 11),
695 .devname
= "s3c2440-i2c.6",
696 .parent
= &exynos4_clk_aclk_100
.clk
,
697 .enable
= exynos4_clk_ip_peril_ctrl
,
698 .ctrlbit
= (1 << 12),
701 .devname
= "s3c2440-i2c.7",
702 .parent
= &exynos4_clk_aclk_100
.clk
,
703 .enable
= exynos4_clk_ip_peril_ctrl
,
704 .ctrlbit
= (1 << 13),
707 .devname
= "s3c2440-hdmiphy-i2c",
708 .parent
= &exynos4_clk_aclk_100
.clk
,
709 .enable
= exynos4_clk_ip_peril_ctrl
,
710 .ctrlbit
= (1 << 14),
712 .name
= SYSMMU_CLOCK_NAME
,
713 .devname
= SYSMMU_CLOCK_DEVNAME(mfc_l
, 0),
714 .enable
= exynos4_clk_ip_mfc_ctrl
,
717 .name
= SYSMMU_CLOCK_NAME
,
718 .devname
= SYSMMU_CLOCK_DEVNAME(mfc_r
, 1),
719 .enable
= exynos4_clk_ip_mfc_ctrl
,
722 .name
= SYSMMU_CLOCK_NAME
,
723 .devname
= SYSMMU_CLOCK_DEVNAME(tv
, 2),
724 .enable
= exynos4_clk_ip_tv_ctrl
,
727 .name
= SYSMMU_CLOCK_NAME
,
728 .devname
= SYSMMU_CLOCK_DEVNAME(jpeg
, 3),
729 .enable
= exynos4_clk_ip_cam_ctrl
,
730 .ctrlbit
= (1 << 11),
732 .name
= SYSMMU_CLOCK_NAME
,
733 .devname
= SYSMMU_CLOCK_DEVNAME(rot
, 4),
734 .enable
= exynos4_clk_ip_image_ctrl
,
737 .name
= SYSMMU_CLOCK_NAME
,
738 .devname
= SYSMMU_CLOCK_DEVNAME(fimc0
, 5),
739 .enable
= exynos4_clk_ip_cam_ctrl
,
742 .name
= SYSMMU_CLOCK_NAME
,
743 .devname
= SYSMMU_CLOCK_DEVNAME(fimc1
, 6),
744 .enable
= exynos4_clk_ip_cam_ctrl
,
747 .name
= SYSMMU_CLOCK_NAME
,
748 .devname
= SYSMMU_CLOCK_DEVNAME(fimc2
, 7),
749 .enable
= exynos4_clk_ip_cam_ctrl
,
752 .name
= SYSMMU_CLOCK_NAME
,
753 .devname
= SYSMMU_CLOCK_DEVNAME(fimc3
, 8),
754 .enable
= exynos4_clk_ip_cam_ctrl
,
755 .ctrlbit
= (1 << 10),
757 .name
= SYSMMU_CLOCK_NAME
,
758 .devname
= SYSMMU_CLOCK_DEVNAME(fimd0
, 10),
759 .enable
= exynos4_clk_ip_lcd0_ctrl
,
764 static struct clk exynos4_init_clocks_on
[] = {
767 .devname
= "s5pv210-uart.0",
768 .enable
= exynos4_clk_ip_peril_ctrl
,
772 .devname
= "s5pv210-uart.1",
773 .enable
= exynos4_clk_ip_peril_ctrl
,
777 .devname
= "s5pv210-uart.2",
778 .enable
= exynos4_clk_ip_peril_ctrl
,
782 .devname
= "s5pv210-uart.3",
783 .enable
= exynos4_clk_ip_peril_ctrl
,
787 .devname
= "s5pv210-uart.4",
788 .enable
= exynos4_clk_ip_peril_ctrl
,
792 .devname
= "s5pv210-uart.5",
793 .enable
= exynos4_clk_ip_peril_ctrl
,
798 static struct clk exynos4_clk_pdma0
= {
800 .devname
= "dma-pl330.0",
801 .enable
= exynos4_clk_ip_fsys_ctrl
,
805 static struct clk exynos4_clk_pdma1
= {
807 .devname
= "dma-pl330.1",
808 .enable
= exynos4_clk_ip_fsys_ctrl
,
812 static struct clk exynos4_clk_mdma1
= {
814 .devname
= "dma-pl330.2",
815 .enable
= exynos4_clk_ip_image_ctrl
,
816 .ctrlbit
= ((1 << 8) | (1 << 5) | (1 << 2)),
819 static struct clk exynos4_clk_fimd0
= {
821 .devname
= "exynos4-fb.0",
822 .enable
= exynos4_clk_ip_lcd0_ctrl
,
826 struct clk
*exynos4_clkset_group_list
[] = {
827 [0] = &clk_ext_xtal_mux
,
829 [2] = &exynos4_clk_sclk_hdmi27m
,
830 [3] = &exynos4_clk_sclk_usbphy0
,
831 [4] = &exynos4_clk_sclk_usbphy1
,
832 [5] = &exynos4_clk_sclk_hdmiphy
,
833 [6] = &exynos4_clk_mout_mpll
.clk
,
834 [7] = &exynos4_clk_mout_epll
.clk
,
835 [8] = &exynos4_clk_sclk_vpll
.clk
,
838 struct clksrc_sources exynos4_clkset_group
= {
839 .sources
= exynos4_clkset_group_list
,
840 .nr_sources
= ARRAY_SIZE(exynos4_clkset_group_list
),
843 static struct clk
*exynos4_clkset_mout_g2d0_list
[] = {
844 [0] = &exynos4_clk_mout_mpll
.clk
,
845 [1] = &exynos4_clk_sclk_apll
.clk
,
848 struct clksrc_sources exynos4_clkset_mout_g2d0
= {
849 .sources
= exynos4_clkset_mout_g2d0_list
,
850 .nr_sources
= ARRAY_SIZE(exynos4_clkset_mout_g2d0_list
),
853 static struct clk
*exynos4_clkset_mout_g2d1_list
[] = {
854 [0] = &exynos4_clk_mout_epll
.clk
,
855 [1] = &exynos4_clk_sclk_vpll
.clk
,
858 struct clksrc_sources exynos4_clkset_mout_g2d1
= {
859 .sources
= exynos4_clkset_mout_g2d1_list
,
860 .nr_sources
= ARRAY_SIZE(exynos4_clkset_mout_g2d1_list
),
863 static struct clk
*exynos4_clkset_mout_mfc0_list
[] = {
864 [0] = &exynos4_clk_mout_mpll
.clk
,
865 [1] = &exynos4_clk_sclk_apll
.clk
,
868 static struct clksrc_sources exynos4_clkset_mout_mfc0
= {
869 .sources
= exynos4_clkset_mout_mfc0_list
,
870 .nr_sources
= ARRAY_SIZE(exynos4_clkset_mout_mfc0_list
),
873 static struct clksrc_clk exynos4_clk_mout_mfc0
= {
877 .sources
= &exynos4_clkset_mout_mfc0
,
878 .reg_src
= { .reg
= EXYNOS4_CLKSRC_MFC
, .shift
= 0, .size
= 1 },
881 static struct clk
*exynos4_clkset_mout_mfc1_list
[] = {
882 [0] = &exynos4_clk_mout_epll
.clk
,
883 [1] = &exynos4_clk_sclk_vpll
.clk
,
886 static struct clksrc_sources exynos4_clkset_mout_mfc1
= {
887 .sources
= exynos4_clkset_mout_mfc1_list
,
888 .nr_sources
= ARRAY_SIZE(exynos4_clkset_mout_mfc1_list
),
891 static struct clksrc_clk exynos4_clk_mout_mfc1
= {
895 .sources
= &exynos4_clkset_mout_mfc1
,
896 .reg_src
= { .reg
= EXYNOS4_CLKSRC_MFC
, .shift
= 4, .size
= 1 },
899 static struct clk
*exynos4_clkset_mout_mfc_list
[] = {
900 [0] = &exynos4_clk_mout_mfc0
.clk
,
901 [1] = &exynos4_clk_mout_mfc1
.clk
,
904 static struct clksrc_sources exynos4_clkset_mout_mfc
= {
905 .sources
= exynos4_clkset_mout_mfc_list
,
906 .nr_sources
= ARRAY_SIZE(exynos4_clkset_mout_mfc_list
),
909 static struct clk
*exynos4_clkset_sclk_dac_list
[] = {
910 [0] = &exynos4_clk_sclk_vpll
.clk
,
911 [1] = &exynos4_clk_sclk_hdmiphy
,
914 static struct clksrc_sources exynos4_clkset_sclk_dac
= {
915 .sources
= exynos4_clkset_sclk_dac_list
,
916 .nr_sources
= ARRAY_SIZE(exynos4_clkset_sclk_dac_list
),
919 static struct clksrc_clk exynos4_clk_sclk_dac
= {
922 .enable
= exynos4_clksrc_mask_tv_ctrl
,
925 .sources
= &exynos4_clkset_sclk_dac
,
926 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TV
, .shift
= 8, .size
= 1 },
929 static struct clksrc_clk exynos4_clk_sclk_pixel
= {
931 .name
= "sclk_pixel",
932 .parent
= &exynos4_clk_sclk_vpll
.clk
,
934 .reg_div
= { .reg
= EXYNOS4_CLKDIV_TV
, .shift
= 0, .size
= 4 },
937 static struct clk
*exynos4_clkset_sclk_hdmi_list
[] = {
938 [0] = &exynos4_clk_sclk_pixel
.clk
,
939 [1] = &exynos4_clk_sclk_hdmiphy
,
942 static struct clksrc_sources exynos4_clkset_sclk_hdmi
= {
943 .sources
= exynos4_clkset_sclk_hdmi_list
,
944 .nr_sources
= ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list
),
947 static struct clksrc_clk exynos4_clk_sclk_hdmi
= {
950 .enable
= exynos4_clksrc_mask_tv_ctrl
,
953 .sources
= &exynos4_clkset_sclk_hdmi
,
954 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TV
, .shift
= 0, .size
= 1 },
957 static struct clk
*exynos4_clkset_sclk_mixer_list
[] = {
958 [0] = &exynos4_clk_sclk_dac
.clk
,
959 [1] = &exynos4_clk_sclk_hdmi
.clk
,
962 static struct clksrc_sources exynos4_clkset_sclk_mixer
= {
963 .sources
= exynos4_clkset_sclk_mixer_list
,
964 .nr_sources
= ARRAY_SIZE(exynos4_clkset_sclk_mixer_list
),
967 static struct clksrc_clk exynos4_clk_sclk_mixer
= {
969 .name
= "sclk_mixer",
970 .enable
= exynos4_clksrc_mask_tv_ctrl
,
973 .sources
= &exynos4_clkset_sclk_mixer
,
974 .reg_src
= { .reg
= EXYNOS4_CLKSRC_TV
, .shift
= 4, .size
= 1 },
977 static struct clksrc_clk
*exynos4_sclk_tv
[] = {
978 &exynos4_clk_sclk_dac
,
979 &exynos4_clk_sclk_pixel
,
980 &exynos4_clk_sclk_hdmi
,
981 &exynos4_clk_sclk_mixer
,
984 static struct clksrc_clk exynos4_clk_dout_mmc0
= {
988 .sources
= &exynos4_clkset_group
,
989 .reg_src
= { .reg
= EXYNOS4_CLKSRC_FSYS
, .shift
= 0, .size
= 4 },
990 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS1
, .shift
= 0, .size
= 4 },
993 static struct clksrc_clk exynos4_clk_dout_mmc1
= {
997 .sources
= &exynos4_clkset_group
,
998 .reg_src
= { .reg
= EXYNOS4_CLKSRC_FSYS
, .shift
= 4, .size
= 4 },
999 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS1
, .shift
= 16, .size
= 4 },
1002 static struct clksrc_clk exynos4_clk_dout_mmc2
= {
1004 .name
= "dout_mmc2",
1006 .sources
= &exynos4_clkset_group
,
1007 .reg_src
= { .reg
= EXYNOS4_CLKSRC_FSYS
, .shift
= 8, .size
= 4 },
1008 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS2
, .shift
= 0, .size
= 4 },
1011 static struct clksrc_clk exynos4_clk_dout_mmc3
= {
1013 .name
= "dout_mmc3",
1015 .sources
= &exynos4_clkset_group
,
1016 .reg_src
= { .reg
= EXYNOS4_CLKSRC_FSYS
, .shift
= 12, .size
= 4 },
1017 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS2
, .shift
= 16, .size
= 4 },
1020 static struct clksrc_clk exynos4_clk_dout_mmc4
= {
1022 .name
= "dout_mmc4",
1024 .sources
= &exynos4_clkset_group
,
1025 .reg_src
= { .reg
= EXYNOS4_CLKSRC_FSYS
, .shift
= 16, .size
= 4 },
1026 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS3
, .shift
= 0, .size
= 4 },
1029 static struct clksrc_clk exynos4_clksrcs
[] = {
1033 .enable
= exynos4_clksrc_mask_peril0_ctrl
,
1034 .ctrlbit
= (1 << 24),
1036 .sources
= &exynos4_clkset_group
,
1037 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL0
, .shift
= 24, .size
= 4 },
1038 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL3
, .shift
= 0, .size
= 4 },
1041 .name
= "sclk_csis",
1042 .devname
= "s5p-mipi-csis.0",
1043 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1044 .ctrlbit
= (1 << 24),
1046 .sources
= &exynos4_clkset_group
,
1047 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 24, .size
= 4 },
1048 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 24, .size
= 4 },
1051 .name
= "sclk_csis",
1052 .devname
= "s5p-mipi-csis.1",
1053 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1054 .ctrlbit
= (1 << 28),
1056 .sources
= &exynos4_clkset_group
,
1057 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 28, .size
= 4 },
1058 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 28, .size
= 4 },
1061 .name
= "sclk_cam0",
1062 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1063 .ctrlbit
= (1 << 16),
1065 .sources
= &exynos4_clkset_group
,
1066 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 16, .size
= 4 },
1067 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 16, .size
= 4 },
1070 .name
= "sclk_cam1",
1071 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1072 .ctrlbit
= (1 << 20),
1074 .sources
= &exynos4_clkset_group
,
1075 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 20, .size
= 4 },
1076 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 20, .size
= 4 },
1079 .name
= "sclk_fimc",
1080 .devname
= "exynos4-fimc.0",
1081 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1082 .ctrlbit
= (1 << 0),
1084 .sources
= &exynos4_clkset_group
,
1085 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 0, .size
= 4 },
1086 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 0, .size
= 4 },
1089 .name
= "sclk_fimc",
1090 .devname
= "exynos4-fimc.1",
1091 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1092 .ctrlbit
= (1 << 4),
1094 .sources
= &exynos4_clkset_group
,
1095 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 4, .size
= 4 },
1096 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 4, .size
= 4 },
1099 .name
= "sclk_fimc",
1100 .devname
= "exynos4-fimc.2",
1101 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1102 .ctrlbit
= (1 << 8),
1104 .sources
= &exynos4_clkset_group
,
1105 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 8, .size
= 4 },
1106 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 8, .size
= 4 },
1109 .name
= "sclk_fimc",
1110 .devname
= "exynos4-fimc.3",
1111 .enable
= exynos4_clksrc_mask_cam_ctrl
,
1112 .ctrlbit
= (1 << 12),
1114 .sources
= &exynos4_clkset_group
,
1115 .reg_src
= { .reg
= EXYNOS4_CLKSRC_CAM
, .shift
= 12, .size
= 4 },
1116 .reg_div
= { .reg
= EXYNOS4_CLKDIV_CAM
, .shift
= 12, .size
= 4 },
1119 .name
= "sclk_fimd",
1120 .devname
= "exynos4-fb.0",
1121 .enable
= exynos4_clksrc_mask_lcd0_ctrl
,
1122 .ctrlbit
= (1 << 0),
1124 .sources
= &exynos4_clkset_group
,
1125 .reg_src
= { .reg
= EXYNOS4_CLKSRC_LCD0
, .shift
= 0, .size
= 4 },
1126 .reg_div
= { .reg
= EXYNOS4_CLKDIV_LCD0
, .shift
= 0, .size
= 4 },
1130 .devname
= "s5p-mfc",
1132 .sources
= &exynos4_clkset_mout_mfc
,
1133 .reg_src
= { .reg
= EXYNOS4_CLKSRC_MFC
, .shift
= 8, .size
= 1 },
1134 .reg_div
= { .reg
= EXYNOS4_CLKDIV_MFC
, .shift
= 0, .size
= 4 },
1137 .name
= "sclk_dwmmc",
1138 .parent
= &exynos4_clk_dout_mmc4
.clk
,
1139 .enable
= exynos4_clksrc_mask_fsys_ctrl
,
1140 .ctrlbit
= (1 << 16),
1142 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS3
, .shift
= 8, .size
= 8 },
1146 static struct clksrc_clk exynos4_clk_sclk_uart0
= {
1149 .devname
= "exynos4210-uart.0",
1150 .enable
= exynos4_clksrc_mask_peril0_ctrl
,
1151 .ctrlbit
= (1 << 0),
1153 .sources
= &exynos4_clkset_group
,
1154 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL0
, .shift
= 0, .size
= 4 },
1155 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL0
, .shift
= 0, .size
= 4 },
1158 static struct clksrc_clk exynos4_clk_sclk_uart1
= {
1161 .devname
= "exynos4210-uart.1",
1162 .enable
= exynos4_clksrc_mask_peril0_ctrl
,
1163 .ctrlbit
= (1 << 4),
1165 .sources
= &exynos4_clkset_group
,
1166 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL0
, .shift
= 4, .size
= 4 },
1167 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL0
, .shift
= 4, .size
= 4 },
1170 static struct clksrc_clk exynos4_clk_sclk_uart2
= {
1173 .devname
= "exynos4210-uart.2",
1174 .enable
= exynos4_clksrc_mask_peril0_ctrl
,
1175 .ctrlbit
= (1 << 8),
1177 .sources
= &exynos4_clkset_group
,
1178 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL0
, .shift
= 8, .size
= 4 },
1179 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL0
, .shift
= 8, .size
= 4 },
1182 static struct clksrc_clk exynos4_clk_sclk_uart3
= {
1185 .devname
= "exynos4210-uart.3",
1186 .enable
= exynos4_clksrc_mask_peril0_ctrl
,
1187 .ctrlbit
= (1 << 12),
1189 .sources
= &exynos4_clkset_group
,
1190 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL0
, .shift
= 12, .size
= 4 },
1191 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL0
, .shift
= 12, .size
= 4 },
1194 static struct clksrc_clk exynos4_clk_sclk_mmc0
= {
1197 .devname
= "exynos4-sdhci.0",
1198 .parent
= &exynos4_clk_dout_mmc0
.clk
,
1199 .enable
= exynos4_clksrc_mask_fsys_ctrl
,
1200 .ctrlbit
= (1 << 0),
1202 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS1
, .shift
= 8, .size
= 8 },
1205 static struct clksrc_clk exynos4_clk_sclk_mmc1
= {
1208 .devname
= "exynos4-sdhci.1",
1209 .parent
= &exynos4_clk_dout_mmc1
.clk
,
1210 .enable
= exynos4_clksrc_mask_fsys_ctrl
,
1211 .ctrlbit
= (1 << 4),
1213 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS1
, .shift
= 24, .size
= 8 },
1216 static struct clksrc_clk exynos4_clk_sclk_mmc2
= {
1219 .devname
= "exynos4-sdhci.2",
1220 .parent
= &exynos4_clk_dout_mmc2
.clk
,
1221 .enable
= exynos4_clksrc_mask_fsys_ctrl
,
1222 .ctrlbit
= (1 << 8),
1224 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS2
, .shift
= 8, .size
= 8 },
1227 static struct clksrc_clk exynos4_clk_sclk_mmc3
= {
1230 .devname
= "exynos4-sdhci.3",
1231 .parent
= &exynos4_clk_dout_mmc3
.clk
,
1232 .enable
= exynos4_clksrc_mask_fsys_ctrl
,
1233 .ctrlbit
= (1 << 12),
1235 .reg_div
= { .reg
= EXYNOS4_CLKDIV_FSYS2
, .shift
= 24, .size
= 8 },
1238 static struct clksrc_clk exynos4_clk_mdout_spi0
= {
1240 .name
= "mdout_spi",
1241 .devname
= "exynos4210-spi.0",
1243 .sources
= &exynos4_clkset_group
,
1244 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL1
, .shift
= 16, .size
= 4 },
1245 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL1
, .shift
= 0, .size
= 4 },
1248 static struct clksrc_clk exynos4_clk_mdout_spi1
= {
1250 .name
= "mdout_spi",
1251 .devname
= "exynos4210-spi.1",
1253 .sources
= &exynos4_clkset_group
,
1254 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL1
, .shift
= 20, .size
= 4 },
1255 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL1
, .shift
= 16, .size
= 4 },
1258 static struct clksrc_clk exynos4_clk_mdout_spi2
= {
1260 .name
= "mdout_spi",
1261 .devname
= "exynos4210-spi.2",
1263 .sources
= &exynos4_clkset_group
,
1264 .reg_src
= { .reg
= EXYNOS4_CLKSRC_PERIL1
, .shift
= 24, .size
= 4 },
1265 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL2
, .shift
= 0, .size
= 4 },
1268 static struct clksrc_clk exynos4_clk_sclk_spi0
= {
1271 .devname
= "exynos4210-spi.0",
1272 .parent
= &exynos4_clk_mdout_spi0
.clk
,
1273 .enable
= exynos4_clksrc_mask_peril1_ctrl
,
1274 .ctrlbit
= (1 << 16),
1276 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL1
, .shift
= 8, .size
= 8 },
1279 static struct clksrc_clk exynos4_clk_sclk_spi1
= {
1282 .devname
= "exynos4210-spi.1",
1283 .parent
= &exynos4_clk_mdout_spi1
.clk
,
1284 .enable
= exynos4_clksrc_mask_peril1_ctrl
,
1285 .ctrlbit
= (1 << 20),
1287 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL1
, .shift
= 24, .size
= 8 },
1290 static struct clksrc_clk exynos4_clk_sclk_spi2
= {
1293 .devname
= "exynos4210-spi.2",
1294 .parent
= &exynos4_clk_mdout_spi2
.clk
,
1295 .enable
= exynos4_clksrc_mask_peril1_ctrl
,
1296 .ctrlbit
= (1 << 24),
1298 .reg_div
= { .reg
= EXYNOS4_CLKDIV_PERIL2
, .shift
= 8, .size
= 8 },
1301 /* Clock initialization code */
1302 static struct clksrc_clk
*exynos4_sysclks
[] = {
1303 &exynos4_clk_mout_apll
,
1304 &exynos4_clk_sclk_apll
,
1305 &exynos4_clk_mout_epll
,
1306 &exynos4_clk_mout_mpll
,
1307 &exynos4_clk_moutcore
,
1308 &exynos4_clk_coreclk
,
1309 &exynos4_clk_armclk
,
1310 &exynos4_clk_aclk_corem0
,
1311 &exynos4_clk_aclk_cores
,
1312 &exynos4_clk_aclk_corem1
,
1313 &exynos4_clk_periphclk
,
1314 &exynos4_clk_mout_corebus
,
1315 &exynos4_clk_sclk_dmc
,
1316 &exynos4_clk_aclk_cored
,
1317 &exynos4_clk_aclk_corep
,
1318 &exynos4_clk_aclk_acp
,
1319 &exynos4_clk_pclk_acp
,
1320 &exynos4_clk_vpllsrc
,
1321 &exynos4_clk_sclk_vpll
,
1322 &exynos4_clk_aclk_200
,
1323 &exynos4_clk_aclk_100
,
1324 &exynos4_clk_aclk_160
,
1325 &exynos4_clk_aclk_133
,
1326 &exynos4_clk_dout_mmc0
,
1327 &exynos4_clk_dout_mmc1
,
1328 &exynos4_clk_dout_mmc2
,
1329 &exynos4_clk_dout_mmc3
,
1330 &exynos4_clk_dout_mmc4
,
1331 &exynos4_clk_mout_mfc0
,
1332 &exynos4_clk_mout_mfc1
,
1335 static struct clk
*exynos4_clk_cdev
[] = {
1342 static struct clksrc_clk
*exynos4_clksrc_cdev
[] = {
1343 &exynos4_clk_sclk_uart0
,
1344 &exynos4_clk_sclk_uart1
,
1345 &exynos4_clk_sclk_uart2
,
1346 &exynos4_clk_sclk_uart3
,
1347 &exynos4_clk_sclk_mmc0
,
1348 &exynos4_clk_sclk_mmc1
,
1349 &exynos4_clk_sclk_mmc2
,
1350 &exynos4_clk_sclk_mmc3
,
1351 &exynos4_clk_sclk_spi0
,
1352 &exynos4_clk_sclk_spi1
,
1353 &exynos4_clk_sclk_spi2
,
1354 &exynos4_clk_mdout_spi0
,
1355 &exynos4_clk_mdout_spi1
,
1356 &exynos4_clk_mdout_spi2
,
1359 static struct clk_lookup exynos4_clk_lookup
[] = {
1360 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0
.clk
),
1361 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1
.clk
),
1362 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2
.clk
),
1363 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3
.clk
),
1364 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0
.clk
),
1365 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1
.clk
),
1366 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2
.clk
),
1367 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3
.clk
),
1368 CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0
),
1369 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0
),
1370 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1
),
1371 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1
),
1372 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0
.clk
),
1373 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1
.clk
),
1374 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2
.clk
),
1377 static int xtal_rate
;
1379 static unsigned long exynos4_fout_apll_get_rate(struct clk
*clk
)
1381 if (soc_is_exynos4210())
1382 return s5p_get_pll45xx(xtal_rate
, __raw_readl(EXYNOS4_APLL_CON0
),
1384 else if (soc_is_exynos4212() || soc_is_exynos4412())
1385 return s5p_get_pll35xx(xtal_rate
, __raw_readl(EXYNOS4_APLL_CON0
));
1390 static struct clk_ops exynos4_fout_apll_ops
= {
1391 .get_rate
= exynos4_fout_apll_get_rate
,
1394 static u32 exynos4_vpll_div
[][8] = {
1395 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1396 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1399 static unsigned long exynos4_vpll_get_rate(struct clk
*clk
)
1404 static int exynos4_vpll_set_rate(struct clk
*clk
, unsigned long rate
)
1406 unsigned int vpll_con0
, vpll_con1
= 0;
1409 /* Return if nothing changed */
1410 if (clk
->rate
== rate
)
1413 vpll_con0
= __raw_readl(EXYNOS4_VPLL_CON0
);
1414 vpll_con0
&= ~(0x1 << 27 | \
1415 PLL90XX_MDIV_MASK
<< PLL46XX_MDIV_SHIFT
| \
1416 PLL90XX_PDIV_MASK
<< PLL46XX_PDIV_SHIFT
| \
1417 PLL90XX_SDIV_MASK
<< PLL46XX_SDIV_SHIFT
);
1419 vpll_con1
= __raw_readl(EXYNOS4_VPLL_CON1
);
1420 vpll_con1
&= ~(PLL46XX_MRR_MASK
<< PLL46XX_MRR_SHIFT
| \
1421 PLL46XX_MFR_MASK
<< PLL46XX_MFR_SHIFT
| \
1422 PLL4650C_KDIV_MASK
<< PLL46XX_KDIV_SHIFT
);
1424 for (i
= 0; i
< ARRAY_SIZE(exynos4_vpll_div
); i
++) {
1425 if (exynos4_vpll_div
[i
][0] == rate
) {
1426 vpll_con0
|= exynos4_vpll_div
[i
][1] << PLL46XX_PDIV_SHIFT
;
1427 vpll_con0
|= exynos4_vpll_div
[i
][2] << PLL46XX_MDIV_SHIFT
;
1428 vpll_con0
|= exynos4_vpll_div
[i
][3] << PLL46XX_SDIV_SHIFT
;
1429 vpll_con1
|= exynos4_vpll_div
[i
][4] << PLL46XX_KDIV_SHIFT
;
1430 vpll_con1
|= exynos4_vpll_div
[i
][5] << PLL46XX_MFR_SHIFT
;
1431 vpll_con1
|= exynos4_vpll_div
[i
][6] << PLL46XX_MRR_SHIFT
;
1432 vpll_con0
|= exynos4_vpll_div
[i
][7] << 27;
1437 if (i
== ARRAY_SIZE(exynos4_vpll_div
)) {
1438 printk(KERN_ERR
"%s: Invalid Clock VPLL Frequency\n",
1443 __raw_writel(vpll_con0
, EXYNOS4_VPLL_CON0
);
1444 __raw_writel(vpll_con1
, EXYNOS4_VPLL_CON1
);
1446 /* Wait for VPLL lock */
1447 while (!(__raw_readl(EXYNOS4_VPLL_CON0
) & (1 << PLL46XX_LOCKED_SHIFT
)))
1454 static struct clk_ops exynos4_vpll_ops
= {
1455 .get_rate
= exynos4_vpll_get_rate
,
1456 .set_rate
= exynos4_vpll_set_rate
,
1459 void __init_or_cpufreq
exynos4_setup_clocks(void)
1461 struct clk
*xtal_clk
;
1462 unsigned long apll
= 0;
1463 unsigned long mpll
= 0;
1464 unsigned long epll
= 0;
1465 unsigned long vpll
= 0;
1466 unsigned long vpllsrc
;
1468 unsigned long armclk
;
1469 unsigned long sclk_dmc
;
1470 unsigned long aclk_200
;
1471 unsigned long aclk_100
;
1472 unsigned long aclk_160
;
1473 unsigned long aclk_133
;
1476 printk(KERN_DEBUG
"%s: registering clocks\n", __func__
);
1478 xtal_clk
= clk_get(NULL
, "xtal");
1479 BUG_ON(IS_ERR(xtal_clk
));
1481 xtal
= clk_get_rate(xtal_clk
);
1487 printk(KERN_DEBUG
"%s: xtal is %ld\n", __func__
, xtal
);
1489 if (soc_is_exynos4210()) {
1490 apll
= s5p_get_pll45xx(xtal
, __raw_readl(EXYNOS4_APLL_CON0
),
1492 mpll
= s5p_get_pll45xx(xtal
, __raw_readl(EXYNOS4_MPLL_CON0
),
1494 epll
= s5p_get_pll46xx(xtal
, __raw_readl(EXYNOS4_EPLL_CON0
),
1495 __raw_readl(EXYNOS4_EPLL_CON1
), pll_4600
);
1497 vpllsrc
= clk_get_rate(&exynos4_clk_vpllsrc
.clk
);
1498 vpll
= s5p_get_pll46xx(vpllsrc
, __raw_readl(EXYNOS4_VPLL_CON0
),
1499 __raw_readl(EXYNOS4_VPLL_CON1
), pll_4650c
);
1500 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1501 apll
= s5p_get_pll35xx(xtal
, __raw_readl(EXYNOS4_APLL_CON0
));
1502 mpll
= s5p_get_pll35xx(xtal
, __raw_readl(EXYNOS4_MPLL_CON0
));
1503 epll
= s5p_get_pll36xx(xtal
, __raw_readl(EXYNOS4_EPLL_CON0
),
1504 __raw_readl(EXYNOS4_EPLL_CON1
));
1506 vpllsrc
= clk_get_rate(&exynos4_clk_vpllsrc
.clk
);
1507 vpll
= s5p_get_pll36xx(vpllsrc
, __raw_readl(EXYNOS4_VPLL_CON0
),
1508 __raw_readl(EXYNOS4_VPLL_CON1
));
1513 clk_fout_apll
.ops
= &exynos4_fout_apll_ops
;
1514 clk_fout_mpll
.rate
= mpll
;
1515 clk_fout_epll
.rate
= epll
;
1516 clk_fout_vpll
.ops
= &exynos4_vpll_ops
;
1517 clk_fout_vpll
.rate
= vpll
;
1519 printk(KERN_INFO
"EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1520 apll
, mpll
, epll
, vpll
);
1522 armclk
= clk_get_rate(&exynos4_clk_armclk
.clk
);
1523 sclk_dmc
= clk_get_rate(&exynos4_clk_sclk_dmc
.clk
);
1525 aclk_200
= clk_get_rate(&exynos4_clk_aclk_200
.clk
);
1526 aclk_100
= clk_get_rate(&exynos4_clk_aclk_100
.clk
);
1527 aclk_160
= clk_get_rate(&exynos4_clk_aclk_160
.clk
);
1528 aclk_133
= clk_get_rate(&exynos4_clk_aclk_133
.clk
);
1530 printk(KERN_INFO
"EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1531 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1532 armclk
, sclk_dmc
, aclk_200
,
1533 aclk_100
, aclk_160
, aclk_133
);
1535 clk_f
.rate
= armclk
;
1536 clk_h
.rate
= sclk_dmc
;
1537 clk_p
.rate
= aclk_100
;
1539 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos4_clksrcs
); ptr
++)
1540 s3c_set_clksrc(&exynos4_clksrcs
[ptr
], true);
1543 static struct clk
*exynos4_clks
[] __initdata
= {
1544 &exynos4_clk_sclk_hdmi27m
,
1545 &exynos4_clk_sclk_hdmiphy
,
1546 &exynos4_clk_sclk_usbphy0
,
1547 &exynos4_clk_sclk_usbphy1
,
1550 #ifdef CONFIG_PM_SLEEP
1551 static int exynos4_clock_suspend(void)
1553 s3c_pm_do_save(exynos4_clock_save
, ARRAY_SIZE(exynos4_clock_save
));
1557 static void exynos4_clock_resume(void)
1559 s3c_pm_do_restore_core(exynos4_clock_save
, ARRAY_SIZE(exynos4_clock_save
));
1563 #define exynos4_clock_suspend NULL
1564 #define exynos4_clock_resume NULL
1567 static struct syscore_ops exynos4_clock_syscore_ops
= {
1568 .suspend
= exynos4_clock_suspend
,
1569 .resume
= exynos4_clock_resume
,
1572 void __init
exynos4_register_clocks(void)
1576 s3c24xx_register_clocks(exynos4_clks
, ARRAY_SIZE(exynos4_clks
));
1578 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos4_sysclks
); ptr
++)
1579 s3c_register_clksrc(exynos4_sysclks
[ptr
], 1);
1581 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos4_sclk_tv
); ptr
++)
1582 s3c_register_clksrc(exynos4_sclk_tv
[ptr
], 1);
1584 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos4_clksrc_cdev
); ptr
++)
1585 s3c_register_clksrc(exynos4_clksrc_cdev
[ptr
], 1);
1587 s3c_register_clksrc(exynos4_clksrcs
, ARRAY_SIZE(exynos4_clksrcs
));
1588 s3c_register_clocks(exynos4_init_clocks_on
, ARRAY_SIZE(exynos4_init_clocks_on
));
1590 s3c24xx_register_clocks(exynos4_clk_cdev
, ARRAY_SIZE(exynos4_clk_cdev
));
1591 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos4_clk_cdev
); ptr
++)
1592 s3c_disable_clocks(exynos4_clk_cdev
[ptr
], 1);
1594 s3c_register_clocks(exynos4_init_clocks_off
, ARRAY_SIZE(exynos4_init_clocks_off
));
1595 s3c_disable_clocks(exynos4_init_clocks_off
, ARRAY_SIZE(exynos4_init_clocks_off
));
1596 clkdev_add_table(exynos4_clk_lookup
, ARRAY_SIZE(exynos4_clk_lookup
));
1598 register_syscore_ops(&exynos4_clock_syscore_ops
);
1599 s3c24xx_register_clock(&dummy_apb_pclk
);