arch/arm/mach-exynos/clock-exynos4210.c

   1 /*
   2  * linux/arch/arm/mach-exynos4/clock-exynos4210.c
   3  *
   4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * EXYNOS4210 - Clock support
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12 */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/syscore_ops.h>
  19
  20 #include <plat/cpu-freq.h>
  21 #include <plat/clock.h>
  22 #include <plat/cpu.h>
  23 #include <plat/pll.h>
  24 #include <plat/s5p-clock.h>
  25 #include <plat/clock-clksrc.h>
  26 #include <plat/exynos4.h>
  27 #include <plat/pm.h>
  28
  29 #include <mach/hardware.h>
  30 #include <mach/map.h>
  31 #include <mach/regs-clock.h>
  32 #include <mach/exynos4-clock.h>
  33
  34 static struct sleep_save exynos4210_clock_save[] = {
  35         SAVE_ITEM(S5P_CLKSRC_IMAGE),
  36         SAVE_ITEM(S5P_CLKSRC_LCD1),
  37         SAVE_ITEM(S5P_CLKDIV_IMAGE),
  38         SAVE_ITEM(S5P_CLKDIV_LCD1),
  39         SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
  40         SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
  41         SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
  42         SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
  43 };
  44
  45 static struct clksrc_clk *sysclks[] = {
  46         /* nothing here yet */
  47 };
  48
  49 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
  50 {
  51         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
  52 }
  53
  54 static struct clksrc_clk clksrcs[] = {
  55         {
  56                 .clk            = {
  57                         .name           = "sclk_sata",
  58                         .id             = -1,
  59                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
  60                         .ctrlbit        = (1 << 24),
  61                 },
  62                 .sources = &clkset_mout_corebus,
  63                 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
  64                 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
  65         }, {
  66                 .clk            = {
  67                         .name           = "sclk_fimd",
  68                         .devname        = "exynos4-fb.1",
  69                         .enable         = exynos4_clksrc_mask_lcd1_ctrl,
  70                         .ctrlbit        = (1 << 0),
  71                 },
  72                 .sources = &clkset_group,
  73                 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
  74                 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
  75         },
  76 };
  77
  78 static struct clk init_clocks_off[] = {
  79         {
  80                 .name           = "sataphy",
  81                 .id             = -1,
  82                 .parent         = &clk_aclk_133.clk,
  83                 .enable         = exynos4_clk_ip_fsys_ctrl,
  84                 .ctrlbit        = (1 << 3),
  85         }, {
  86                 .name           = "sata",
  87                 .id             = -1,
  88                 .parent         = &clk_aclk_133.clk,
  89                 .enable         = exynos4_clk_ip_fsys_ctrl,
  90                 .ctrlbit        = (1 << 10),
  91         }, {
  92                 .name           = "fimd",
  93                 .devname        = "exynos4-fb.1",
  94                 .enable         = exynos4_clk_ip_lcd1_ctrl,
  95                 .ctrlbit        = (1 << 0),
  96         },
  97 };
  98
  99 #ifdef CONFIG_PM_SLEEP
 100 static int exynos4210_clock_suspend(void)
 101 {
 102         s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
 103
 104         return 0;
 105 }
 106
 107 static void exynos4210_clock_resume(void)
 108 {
 109         s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
 110 }
 111
 112 #else
 113 #define exynos4210_clock_suspend NULL
 114 #define exynos4210_clock_resume NULL
 115 #endif
 116
 117 struct syscore_ops exynos4210_clock_syscore_ops = {
 118         .suspend        = exynos4210_clock_suspend,
 119         .resume         = exynos4210_clock_resume,
 120 };
 121
 122 void __init exynos4210_register_clocks(void)
 123 {
 124         int ptr;
 125
 126         clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
 127         clk_mout_mpll.reg_src.shift = 8;
 128         clk_mout_mpll.reg_src.size = 1;
 129
 130         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 131                 s3c_register_clksrc(sysclks[ptr], 1);
 132
 133         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 134
 135         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 136         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 137
 138         register_syscore_ops(&exynos4210_clock_syscore_ops);
 139 }