arch/arm/mach-exynos/clock-exynos4212.c

   1 /*
   2  * linux/arch/arm/mach-exynos4/clock-exynos4212.c
   3  *
   4  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * EXYNOS4212 - Clock support
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12 */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/syscore_ops.h>
  19
  20 #include <plat/cpu-freq.h>
  21 #include <plat/clock.h>
  22 #include <plat/cpu.h>
  23 #include <plat/pll.h>
  24 #include <plat/s5p-clock.h>
  25 #include <plat/clock-clksrc.h>
  26 #include <plat/pm.h>
  27
  28 #include <mach/hardware.h>
  29 #include <mach/map.h>
  30 #include <mach/regs-clock.h>
  31 #include <mach/exynos4-clock.h>
  32
  33 #include "common.h"
  34
  35 static struct sleep_save exynos4212_clock_save[] = {
  36         SAVE_ITEM(S5P_CLKSRC_IMAGE),
  37         SAVE_ITEM(S5P_CLKDIV_IMAGE),
  38         SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
  39         SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
  40 };
  41
  42 static struct clk *clk_src_mpll_user_list[] = {
  43         [0] = &clk_fin_mpll,
  44         [1] = &clk_mout_mpll.clk,
  45 };
  46
  47 static struct clksrc_sources clk_src_mpll_user = {
  48         .sources        = clk_src_mpll_user_list,
  49         .nr_sources     = ARRAY_SIZE(clk_src_mpll_user_list),
  50 };
  51
  52 static struct clksrc_clk clk_mout_mpll_user = {
  53         .clk = {
  54                 .name           = "mout_mpll_user",
  55         },
  56         .sources        = &clk_src_mpll_user,
  57         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
  58 };
  59
  60 static struct clksrc_clk *sysclks[] = {
  61         &clk_mout_mpll_user,
  62 };
  63
  64 static struct clksrc_clk clksrcs[] = {
  65         /* nothing here yet */
  66 };
  67
  68 static struct clk init_clocks_off[] = {
  69         /* nothing here yet */
  70 };
  71
  72 #ifdef CONFIG_PM_SLEEP
  73 static int exynos4212_clock_suspend(void)
  74 {
  75         s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
  76
  77         return 0;
  78 }
  79
  80 static void exynos4212_clock_resume(void)
  81 {
  82         s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
  83 }
  84
  85 #else
  86 #define exynos4212_clock_suspend NULL
  87 #define exynos4212_clock_resume NULL
  88 #endif
  89
  90 struct syscore_ops exynos4212_clock_syscore_ops = {
  91         .suspend        = exynos4212_clock_suspend,
  92         .resume         = exynos4212_clock_resume,
  93 };
  94
  95 void __init exynos4212_register_clocks(void)
  96 {
  97         int ptr;
  98
  99         /* usbphy1 is removed */
 100         clkset_group_list[4] = NULL;
 101
 102         /* mout_mpll_user is used */
 103         clkset_group_list[6] = &clk_mout_mpll_user.clk;
 104         clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
 105
 106         clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
 107         clk_mout_mpll.reg_src.shift = 12;
 108         clk_mout_mpll.reg_src.size = 1;
 109
 110         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 111                 s3c_register_clksrc(sysclks[ptr], 1);
 112
 113         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 114
 115         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 116         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 117
 118         register_syscore_ops(&exynos4212_clock_syscore_ops);
 119 }