2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Clock support for EXYNOS5 SoCs
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/err.h>
15 #include <linux/syscore_ops.h>
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
26 #include <mach/regs-clock.h>
27 #include <mach/sysmmu.h>
31 #ifdef CONFIG_PM_SLEEP
32 static struct sleep_save exynos5_clock_save
[] = {
33 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP
),
34 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL
),
35 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0
),
36 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS
),
37 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO
),
38 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0
),
39 SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1
),
40 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL
),
41 SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1
),
42 SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC
),
43 SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D
),
44 SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN
),
45 SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS
),
46 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC
),
47 SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS
),
48 SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK
),
49 SAVE_ITEM(EXYNOS5_CLKDIV_TOP0
),
50 SAVE_ITEM(EXYNOS5_CLKDIV_TOP1
),
51 SAVE_ITEM(EXYNOS5_CLKDIV_GSCL
),
52 SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0
),
53 SAVE_ITEM(EXYNOS5_CLKDIV_GEN
),
54 SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO
),
55 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0
),
56 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1
),
57 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2
),
58 SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3
),
59 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0
),
60 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1
),
61 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2
),
62 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3
),
63 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4
),
64 SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5
),
65 SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP
),
66 SAVE_ITEM(EXYNOS5_CLKSRC_TOP0
),
67 SAVE_ITEM(EXYNOS5_CLKSRC_TOP1
),
68 SAVE_ITEM(EXYNOS5_CLKSRC_TOP2
),
69 SAVE_ITEM(EXYNOS5_CLKSRC_TOP3
),
70 SAVE_ITEM(EXYNOS5_CLKSRC_GSCL
),
71 SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0
),
72 SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO
),
73 SAVE_ITEM(EXYNOS5_CLKSRC_FSYS
),
74 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0
),
75 SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1
),
76 SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP
),
77 SAVE_ITEM(EXYNOS5_EPLL_CON0
),
78 SAVE_ITEM(EXYNOS5_EPLL_CON1
),
79 SAVE_ITEM(EXYNOS5_EPLL_CON2
),
80 SAVE_ITEM(EXYNOS5_VPLL_CON0
),
81 SAVE_ITEM(EXYNOS5_VPLL_CON1
),
82 SAVE_ITEM(EXYNOS5_VPLL_CON2
),
86 static struct clk exynos5_clk_sclk_dptxphy
= {
90 static struct clk exynos5_clk_sclk_hdmi24m
= {
91 .name
= "sclk_hdmi24m",
95 static struct clk exynos5_clk_sclk_hdmi27m
= {
96 .name
= "sclk_hdmi27m",
100 static struct clk exynos5_clk_sclk_hdmiphy
= {
101 .name
= "sclk_hdmiphy",
104 static struct clk exynos5_clk_sclk_usbphy
= {
105 .name
= "sclk_usbphy",
109 static int exynos5_clksrc_mask_top_ctrl(struct clk
*clk
, int enable
)
111 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP
, clk
, enable
);
114 static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk
*clk
, int enable
)
116 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0
, clk
, enable
);
119 static int exynos5_clksrc_mask_fsys_ctrl(struct clk
*clk
, int enable
)
121 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS
, clk
, enable
);
124 static int exynos5_clksrc_mask_gscl_ctrl(struct clk
*clk
, int enable
)
126 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL
, clk
, enable
);
129 static int exynos5_clksrc_mask_peric0_ctrl(struct clk
*clk
, int enable
)
131 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0
, clk
, enable
);
134 static int exynos5_clksrc_mask_peric1_ctrl(struct clk
*clk
, int enable
)
136 return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1
, clk
, enable
);
139 static int exynos5_clk_ip_acp_ctrl(struct clk
*clk
, int enable
)
141 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP
, clk
, enable
);
144 static int exynos5_clk_ip_core_ctrl(struct clk
*clk
, int enable
)
146 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE
, clk
, enable
);
149 static int exynos5_clk_ip_disp1_ctrl(struct clk
*clk
, int enable
)
151 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1
, clk
, enable
);
154 static int exynos5_clk_ip_fsys_ctrl(struct clk
*clk
, int enable
)
156 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS
, clk
, enable
);
159 static int exynos5_clk_block_ctrl(struct clk
*clk
, int enable
)
161 return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK
, clk
, enable
);
164 static int exynos5_clk_ip_gen_ctrl(struct clk
*clk
, int enable
)
166 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN
, clk
, enable
);
169 static int exynos5_clk_ip_mfc_ctrl(struct clk
*clk
, int enable
)
171 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC
, clk
, enable
);
174 static int exynos5_clk_ip_peric_ctrl(struct clk
*clk
, int enable
)
176 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC
, clk
, enable
);
179 static int exynos5_clk_ip_peris_ctrl(struct clk
*clk
, int enable
)
181 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS
, clk
, enable
);
184 static int exynos5_clk_ip_gscl_ctrl(struct clk
*clk
, int enable
)
186 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL
, clk
, enable
);
189 static int exynos5_clk_ip_isp0_ctrl(struct clk
*clk
, int enable
)
191 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0
, clk
, enable
);
194 static int exynos5_clk_ip_isp1_ctrl(struct clk
*clk
, int enable
)
196 return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1
, clk
, enable
);
199 /* Core list of CMU_CPU side */
201 static struct clksrc_clk exynos5_clk_mout_apll
= {
205 .sources
= &clk_src_apll
,
206 .reg_src
= { .reg
= EXYNOS5_CLKSRC_CPU
, .shift
= 0, .size
= 1 },
209 static struct clksrc_clk exynos5_clk_sclk_apll
= {
212 .parent
= &exynos5_clk_mout_apll
.clk
,
214 .reg_div
= { .reg
= EXYNOS5_CLKDIV_CPU0
, .shift
= 24, .size
= 3 },
217 static struct clksrc_clk exynos5_clk_mout_bpll_fout
= {
219 .name
= "mout_bpll_fout",
221 .sources
= &clk_src_bpll_fout
,
222 .reg_src
= { .reg
= EXYNOS5_PLL_DIV2_SEL
, .shift
= 0, .size
= 1 },
225 static struct clk
*exynos5_clk_src_bpll_list
[] = {
227 [1] = &exynos5_clk_mout_bpll_fout
.clk
,
230 static struct clksrc_sources exynos5_clk_src_bpll
= {
231 .sources
= exynos5_clk_src_bpll_list
,
232 .nr_sources
= ARRAY_SIZE(exynos5_clk_src_bpll_list
),
235 static struct clksrc_clk exynos5_clk_mout_bpll
= {
239 .sources
= &exynos5_clk_src_bpll
,
240 .reg_src
= { .reg
= EXYNOS5_CLKSRC_CDREX
, .shift
= 0, .size
= 1 },
243 static struct clk
*exynos5_clk_src_bpll_user_list
[] = {
245 [1] = &exynos5_clk_mout_bpll
.clk
,
248 static struct clksrc_sources exynos5_clk_src_bpll_user
= {
249 .sources
= exynos5_clk_src_bpll_user_list
,
250 .nr_sources
= ARRAY_SIZE(exynos5_clk_src_bpll_user_list
),
253 static struct clksrc_clk exynos5_clk_mout_bpll_user
= {
255 .name
= "mout_bpll_user",
257 .sources
= &exynos5_clk_src_bpll_user
,
258 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP2
, .shift
= 24, .size
= 1 },
261 static struct clksrc_clk exynos5_clk_mout_cpll
= {
265 .sources
= &clk_src_cpll
,
266 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP2
, .shift
= 8, .size
= 1 },
269 static struct clksrc_clk exynos5_clk_mout_epll
= {
273 .sources
= &clk_src_epll
,
274 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP2
, .shift
= 12, .size
= 1 },
277 static struct clksrc_clk exynos5_clk_mout_mpll_fout
= {
279 .name
= "mout_mpll_fout",
281 .sources
= &clk_src_mpll_fout
,
282 .reg_src
= { .reg
= EXYNOS5_PLL_DIV2_SEL
, .shift
= 4, .size
= 1 },
285 static struct clk
*exynos5_clk_src_mpll_list
[] = {
287 [1] = &exynos5_clk_mout_mpll_fout
.clk
,
290 static struct clksrc_sources exynos5_clk_src_mpll
= {
291 .sources
= exynos5_clk_src_mpll_list
,
292 .nr_sources
= ARRAY_SIZE(exynos5_clk_src_mpll_list
),
295 struct clksrc_clk exynos5_clk_mout_mpll
= {
299 .sources
= &exynos5_clk_src_mpll
,
300 .reg_src
= { .reg
= EXYNOS5_CLKSRC_CORE1
, .shift
= 8, .size
= 1 },
303 static struct clk
*exynos_clkset_vpllsrc_list
[] = {
305 [1] = &exynos5_clk_sclk_hdmi27m
,
308 static struct clksrc_sources exynos5_clkset_vpllsrc
= {
309 .sources
= exynos_clkset_vpllsrc_list
,
310 .nr_sources
= ARRAY_SIZE(exynos_clkset_vpllsrc_list
),
313 static struct clksrc_clk exynos5_clk_vpllsrc
= {
316 .enable
= exynos5_clksrc_mask_top_ctrl
,
319 .sources
= &exynos5_clkset_vpllsrc
,
320 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP2
, .shift
= 0, .size
= 1 },
323 static struct clk
*exynos5_clkset_sclk_vpll_list
[] = {
324 [0] = &exynos5_clk_vpllsrc
.clk
,
325 [1] = &clk_fout_vpll
,
328 static struct clksrc_sources exynos5_clkset_sclk_vpll
= {
329 .sources
= exynos5_clkset_sclk_vpll_list
,
330 .nr_sources
= ARRAY_SIZE(exynos5_clkset_sclk_vpll_list
),
333 static struct clksrc_clk exynos5_clk_sclk_vpll
= {
337 .sources
= &exynos5_clkset_sclk_vpll
,
338 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP2
, .shift
= 16, .size
= 1 },
341 static struct clksrc_clk exynos5_clk_sclk_pixel
= {
343 .name
= "sclk_pixel",
344 .parent
= &exynos5_clk_sclk_vpll
.clk
,
346 .reg_div
= { .reg
= EXYNOS5_CLKDIV_DISP1_0
, .shift
= 28, .size
= 4 },
349 static struct clk
*exynos5_clkset_sclk_hdmi_list
[] = {
350 [0] = &exynos5_clk_sclk_pixel
.clk
,
351 [1] = &exynos5_clk_sclk_hdmiphy
,
354 static struct clksrc_sources exynos5_clkset_sclk_hdmi
= {
355 .sources
= exynos5_clkset_sclk_hdmi_list
,
356 .nr_sources
= ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list
),
359 static struct clksrc_clk exynos5_clk_sclk_hdmi
= {
362 .enable
= exynos5_clksrc_mask_disp1_0_ctrl
,
363 .ctrlbit
= (1 << 20),
365 .sources
= &exynos5_clkset_sclk_hdmi
,
366 .reg_src
= { .reg
= EXYNOS5_CLKSRC_DISP1_0
, .shift
= 20, .size
= 1 },
369 static struct clksrc_clk
*exynos5_sclk_tv
[] = {
370 &exynos5_clk_sclk_pixel
,
371 &exynos5_clk_sclk_hdmi
,
374 static struct clk
*exynos5_clk_src_mpll_user_list
[] = {
376 [1] = &exynos5_clk_mout_mpll
.clk
,
379 static struct clksrc_sources exynos5_clk_src_mpll_user
= {
380 .sources
= exynos5_clk_src_mpll_user_list
,
381 .nr_sources
= ARRAY_SIZE(exynos5_clk_src_mpll_user_list
),
384 static struct clksrc_clk exynos5_clk_mout_mpll_user
= {
386 .name
= "mout_mpll_user",
388 .sources
= &exynos5_clk_src_mpll_user
,
389 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP2
, .shift
= 20, .size
= 1 },
392 static struct clk
*exynos5_clkset_mout_cpu_list
[] = {
393 [0] = &exynos5_clk_mout_apll
.clk
,
394 [1] = &exynos5_clk_mout_mpll
.clk
,
397 static struct clksrc_sources exynos5_clkset_mout_cpu
= {
398 .sources
= exynos5_clkset_mout_cpu_list
,
399 .nr_sources
= ARRAY_SIZE(exynos5_clkset_mout_cpu_list
),
402 static struct clksrc_clk exynos5_clk_mout_cpu
= {
406 .sources
= &exynos5_clkset_mout_cpu
,
407 .reg_src
= { .reg
= EXYNOS5_CLKSRC_CPU
, .shift
= 16, .size
= 1 },
410 static struct clksrc_clk exynos5_clk_dout_armclk
= {
412 .name
= "dout_armclk",
413 .parent
= &exynos5_clk_mout_cpu
.clk
,
415 .reg_div
= { .reg
= EXYNOS5_CLKDIV_CPU0
, .shift
= 0, .size
= 3 },
418 static struct clksrc_clk exynos5_clk_dout_arm2clk
= {
420 .name
= "dout_arm2clk",
421 .parent
= &exynos5_clk_dout_armclk
.clk
,
423 .reg_div
= { .reg
= EXYNOS5_CLKDIV_CPU0
, .shift
= 28, .size
= 3 },
426 static struct clk exynos5_clk_armclk
= {
428 .parent
= &exynos5_clk_dout_arm2clk
.clk
,
431 /* Core list of CMU_CDREX side */
433 static struct clk
*exynos5_clkset_cdrex_list
[] = {
434 [0] = &exynos5_clk_mout_mpll
.clk
,
435 [1] = &exynos5_clk_mout_bpll
.clk
,
438 static struct clksrc_sources exynos5_clkset_cdrex
= {
439 .sources
= exynos5_clkset_cdrex_list
,
440 .nr_sources
= ARRAY_SIZE(exynos5_clkset_cdrex_list
),
443 static struct clksrc_clk exynos5_clk_cdrex
= {
447 .sources
= &exynos5_clkset_cdrex
,
448 .reg_src
= { .reg
= EXYNOS5_CLKSRC_CDREX
, .shift
= 4, .size
= 1 },
449 .reg_div
= { .reg
= EXYNOS5_CLKDIV_CDREX
, .shift
= 16, .size
= 3 },
452 static struct clksrc_clk exynos5_clk_aclk_acp
= {
455 .parent
= &exynos5_clk_mout_mpll
.clk
,
457 .reg_div
= { .reg
= EXYNOS5_CLKDIV_ACP
, .shift
= 0, .size
= 3 },
460 static struct clksrc_clk exynos5_clk_pclk_acp
= {
463 .parent
= &exynos5_clk_aclk_acp
.clk
,
465 .reg_div
= { .reg
= EXYNOS5_CLKDIV_ACP
, .shift
= 4, .size
= 3 },
468 /* Core list of CMU_TOP side */
470 struct clk
*exynos5_clkset_aclk_top_list
[] = {
471 [0] = &exynos5_clk_mout_mpll_user
.clk
,
472 [1] = &exynos5_clk_mout_bpll_user
.clk
,
475 struct clksrc_sources exynos5_clkset_aclk
= {
476 .sources
= exynos5_clkset_aclk_top_list
,
477 .nr_sources
= ARRAY_SIZE(exynos5_clkset_aclk_top_list
),
480 static struct clksrc_clk exynos5_clk_aclk_400
= {
484 .sources
= &exynos5_clkset_aclk
,
485 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP0
, .shift
= 20, .size
= 1 },
486 .reg_div
= { .reg
= EXYNOS5_CLKDIV_TOP0
, .shift
= 24, .size
= 3 },
489 struct clk
*exynos5_clkset_aclk_333_166_list
[] = {
490 [0] = &exynos5_clk_mout_cpll
.clk
,
491 [1] = &exynos5_clk_mout_mpll_user
.clk
,
494 struct clksrc_sources exynos5_clkset_aclk_333_166
= {
495 .sources
= exynos5_clkset_aclk_333_166_list
,
496 .nr_sources
= ARRAY_SIZE(exynos5_clkset_aclk_333_166_list
),
499 static struct clksrc_clk exynos5_clk_aclk_333
= {
503 .sources
= &exynos5_clkset_aclk_333_166
,
504 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP0
, .shift
= 16, .size
= 1 },
505 .reg_div
= { .reg
= EXYNOS5_CLKDIV_TOP0
, .shift
= 20, .size
= 3 },
508 static struct clksrc_clk exynos5_clk_aclk_166
= {
512 .sources
= &exynos5_clkset_aclk_333_166
,
513 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP0
, .shift
= 8, .size
= 1 },
514 .reg_div
= { .reg
= EXYNOS5_CLKDIV_TOP0
, .shift
= 8, .size
= 3 },
517 static struct clksrc_clk exynos5_clk_aclk_266
= {
520 .parent
= &exynos5_clk_mout_mpll_user
.clk
,
522 .reg_div
= { .reg
= EXYNOS5_CLKDIV_TOP0
, .shift
= 16, .size
= 3 },
525 static struct clksrc_clk exynos5_clk_aclk_200
= {
529 .sources
= &exynos5_clkset_aclk
,
530 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP0
, .shift
= 12, .size
= 1 },
531 .reg_div
= { .reg
= EXYNOS5_CLKDIV_TOP0
, .shift
= 12, .size
= 3 },
534 static struct clksrc_clk exynos5_clk_aclk_66_pre
= {
536 .name
= "aclk_66_pre",
537 .parent
= &exynos5_clk_mout_mpll_user
.clk
,
539 .reg_div
= { .reg
= EXYNOS5_CLKDIV_TOP1
, .shift
= 24, .size
= 3 },
542 static struct clksrc_clk exynos5_clk_aclk_66
= {
545 .parent
= &exynos5_clk_aclk_66_pre
.clk
,
547 .reg_div
= { .reg
= EXYNOS5_CLKDIV_TOP0
, .shift
= 0, .size
= 3 },
550 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid
= {
552 .name
= "mout_aclk_300_gscl_mid",
554 .sources
= &exynos5_clkset_aclk
,
555 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP0
, .shift
= 24, .size
= 1 },
558 static struct clk
*exynos5_clkset_aclk_300_mid1_list
[] = {
559 [0] = &exynos5_clk_sclk_vpll
.clk
,
560 [1] = &exynos5_clk_mout_cpll
.clk
,
563 static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1
= {
564 .sources
= exynos5_clkset_aclk_300_mid1_list
,
565 .nr_sources
= ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list
),
568 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1
= {
570 .name
= "mout_aclk_300_gscl_mid1",
572 .sources
= &exynos5_clkset_aclk_300_gscl_mid1
,
573 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP1
, .shift
= 12, .size
= 1 },
576 static struct clk
*exynos5_clkset_aclk_300_gscl_list
[] = {
577 [0] = &exynos5_clk_mout_aclk_300_gscl_mid
.clk
,
578 [1] = &exynos5_clk_mout_aclk_300_gscl_mid1
.clk
,
581 static struct clksrc_sources exynos5_clkset_aclk_300_gscl
= {
582 .sources
= exynos5_clkset_aclk_300_gscl_list
,
583 .nr_sources
= ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list
),
586 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl
= {
588 .name
= "mout_aclk_300_gscl",
590 .sources
= &exynos5_clkset_aclk_300_gscl
,
591 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP0
, .shift
= 25, .size
= 1 },
594 static struct clk
*exynos5_clk_src_gscl_300_list
[] = {
595 [0] = &clk_ext_xtal_mux
,
596 [1] = &exynos5_clk_mout_aclk_300_gscl
.clk
,
599 static struct clksrc_sources exynos5_clk_src_gscl_300
= {
600 .sources
= exynos5_clk_src_gscl_300_list
,
601 .nr_sources
= ARRAY_SIZE(exynos5_clk_src_gscl_300_list
),
604 static struct clksrc_clk exynos5_clk_aclk_300_gscl
= {
606 .name
= "aclk_300_gscl",
608 .sources
= &exynos5_clk_src_gscl_300
,
609 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP3
, .shift
= 10, .size
= 1 },
612 static struct clk exynos5_init_clocks_off
[] = {
615 .parent
= &exynos5_clk_aclk_66
.clk
,
616 .enable
= exynos5_clk_ip_peric_ctrl
,
617 .ctrlbit
= (1 << 24),
620 .parent
= &exynos5_clk_aclk_66
.clk
,
621 .enable
= exynos5_clk_ip_peris_ctrl
,
622 .ctrlbit
= (1 << 20),
625 .parent
= &exynos5_clk_aclk_66
.clk
,
626 .enable
= exynos5_clk_ip_peris_ctrl
,
627 .ctrlbit
= (1 << 19),
629 .name
= "biu", /* bus interface unit clock */
630 .devname
= "dw_mmc.0",
631 .parent
= &exynos5_clk_aclk_200
.clk
,
632 .enable
= exynos5_clk_ip_fsys_ctrl
,
633 .ctrlbit
= (1 << 12),
636 .devname
= "dw_mmc.1",
637 .parent
= &exynos5_clk_aclk_200
.clk
,
638 .enable
= exynos5_clk_ip_fsys_ctrl
,
639 .ctrlbit
= (1 << 13),
642 .devname
= "dw_mmc.2",
643 .parent
= &exynos5_clk_aclk_200
.clk
,
644 .enable
= exynos5_clk_ip_fsys_ctrl
,
645 .ctrlbit
= (1 << 14),
648 .devname
= "dw_mmc.3",
649 .parent
= &exynos5_clk_aclk_200
.clk
,
650 .enable
= exynos5_clk_ip_fsys_ctrl
,
651 .ctrlbit
= (1 << 15),
655 .enable
= exynos5_clk_ip_fsys_ctrl
,
659 .enable
= exynos5_clk_ip_fsys_ctrl
,
660 .ctrlbit
= (1 << 24),
662 .name
= "sata_phy_i2c",
663 .enable
= exynos5_clk_ip_fsys_ctrl
,
664 .ctrlbit
= (1 << 25),
667 .devname
= "s5p-mfc",
668 .enable
= exynos5_clk_ip_mfc_ctrl
,
672 .devname
= "exynos4-hdmi",
673 .enable
= exynos5_clk_ip_disp1_ctrl
,
677 .devname
= "s5p-mixer",
678 .enable
= exynos5_clk_ip_disp1_ctrl
,
682 .enable
= exynos5_clk_ip_gen_ctrl
,
686 .enable
= exynos5_clk_ip_disp1_ctrl
,
690 .devname
= "samsung-i2s.1",
691 .enable
= exynos5_clk_ip_peric_ctrl
,
692 .ctrlbit
= (1 << 20),
695 .devname
= "samsung-i2s.2",
696 .enable
= exynos5_clk_ip_peric_ctrl
,
697 .ctrlbit
= (1 << 21),
700 .devname
= "samsung-pcm.1",
701 .enable
= exynos5_clk_ip_peric_ctrl
,
702 .ctrlbit
= (1 << 22),
705 .devname
= "samsung-pcm.2",
706 .enable
= exynos5_clk_ip_peric_ctrl
,
707 .ctrlbit
= (1 << 23),
710 .devname
= "samsung-spdif",
711 .enable
= exynos5_clk_ip_peric_ctrl
,
712 .ctrlbit
= (1 << 26),
715 .devname
= "samsung-ac97",
716 .enable
= exynos5_clk_ip_peric_ctrl
,
717 .ctrlbit
= (1 << 27),
720 .enable
= exynos5_clk_ip_fsys_ctrl
,
721 .ctrlbit
= (1 << 18),
724 .enable
= exynos5_clk_ip_fsys_ctrl
,
728 .enable
= exynos5_clk_ip_fsys_ctrl
,
729 .ctrlbit
= (1 << 22),
732 .enable
= exynos5_clk_ip_fsys_ctrl
,
733 .ctrlbit
= ((1 << 30) | (1 << 26) | (1 << 23)),
736 .enable
= exynos5_clk_ip_core_ctrl
,
737 .ctrlbit
= ((1 << 21) | (1 << 3)),
740 .enable
= exynos5_clk_ip_fsys_ctrl
,
744 .devname
= "s3c2440-i2c.0",
745 .parent
= &exynos5_clk_aclk_66
.clk
,
746 .enable
= exynos5_clk_ip_peric_ctrl
,
750 .devname
= "s3c2440-i2c.1",
751 .parent
= &exynos5_clk_aclk_66
.clk
,
752 .enable
= exynos5_clk_ip_peric_ctrl
,
756 .devname
= "s3c2440-i2c.2",
757 .parent
= &exynos5_clk_aclk_66
.clk
,
758 .enable
= exynos5_clk_ip_peric_ctrl
,
762 .devname
= "s3c2440-i2c.3",
763 .parent
= &exynos5_clk_aclk_66
.clk
,
764 .enable
= exynos5_clk_ip_peric_ctrl
,
768 .devname
= "s3c2440-i2c.4",
769 .parent
= &exynos5_clk_aclk_66
.clk
,
770 .enable
= exynos5_clk_ip_peric_ctrl
,
771 .ctrlbit
= (1 << 10),
774 .devname
= "s3c2440-i2c.5",
775 .parent
= &exynos5_clk_aclk_66
.clk
,
776 .enable
= exynos5_clk_ip_peric_ctrl
,
777 .ctrlbit
= (1 << 11),
780 .devname
= "s3c2440-i2c.6",
781 .parent
= &exynos5_clk_aclk_66
.clk
,
782 .enable
= exynos5_clk_ip_peric_ctrl
,
783 .ctrlbit
= (1 << 12),
786 .devname
= "s3c2440-i2c.7",
787 .parent
= &exynos5_clk_aclk_66
.clk
,
788 .enable
= exynos5_clk_ip_peric_ctrl
,
789 .ctrlbit
= (1 << 13),
792 .devname
= "s3c2440-hdmiphy-i2c",
793 .parent
= &exynos5_clk_aclk_66
.clk
,
794 .enable
= exynos5_clk_ip_peric_ctrl
,
795 .ctrlbit
= (1 << 14),
798 .devname
= "exynos4210-spi.0",
799 .parent
= &exynos5_clk_aclk_66
.clk
,
800 .enable
= exynos5_clk_ip_peric_ctrl
,
801 .ctrlbit
= (1 << 16),
804 .devname
= "exynos4210-spi.1",
805 .parent
= &exynos5_clk_aclk_66
.clk
,
806 .enable
= exynos5_clk_ip_peric_ctrl
,
807 .ctrlbit
= (1 << 17),
810 .devname
= "exynos4210-spi.2",
811 .parent
= &exynos5_clk_aclk_66
.clk
,
812 .enable
= exynos5_clk_ip_peric_ctrl
,
813 .ctrlbit
= (1 << 18),
816 .devname
= "exynos-gsc.0",
817 .enable
= exynos5_clk_ip_gscl_ctrl
,
821 .devname
= "exynos-gsc.1",
822 .enable
= exynos5_clk_ip_gscl_ctrl
,
826 .devname
= "exynos-gsc.2",
827 .enable
= exynos5_clk_ip_gscl_ctrl
,
831 .devname
= "exynos-gsc.3",
832 .enable
= exynos5_clk_ip_gscl_ctrl
,
835 .name
= SYSMMU_CLOCK_NAME
,
836 .devname
= SYSMMU_CLOCK_DEVNAME(mfc_l
, 0),
837 .enable
= &exynos5_clk_ip_mfc_ctrl
,
840 .name
= SYSMMU_CLOCK_NAME
,
841 .devname
= SYSMMU_CLOCK_DEVNAME(mfc_r
, 1),
842 .enable
= &exynos5_clk_ip_mfc_ctrl
,
845 .name
= SYSMMU_CLOCK_NAME
,
846 .devname
= SYSMMU_CLOCK_DEVNAME(tv
, 2),
847 .enable
= &exynos5_clk_ip_disp1_ctrl
,
850 .name
= SYSMMU_CLOCK_NAME
,
851 .devname
= SYSMMU_CLOCK_DEVNAME(jpeg
, 3),
852 .enable
= &exynos5_clk_ip_gen_ctrl
,
855 .name
= SYSMMU_CLOCK_NAME
,
856 .devname
= SYSMMU_CLOCK_DEVNAME(rot
, 4),
857 .enable
= &exynos5_clk_ip_gen_ctrl
,
860 .name
= SYSMMU_CLOCK_NAME
,
861 .devname
= SYSMMU_CLOCK_DEVNAME(gsc0
, 5),
862 .enable
= &exynos5_clk_ip_gscl_ctrl
,
865 .name
= SYSMMU_CLOCK_NAME
,
866 .devname
= SYSMMU_CLOCK_DEVNAME(gsc1
, 6),
867 .enable
= &exynos5_clk_ip_gscl_ctrl
,
870 .name
= SYSMMU_CLOCK_NAME
,
871 .devname
= SYSMMU_CLOCK_DEVNAME(gsc2
, 7),
872 .enable
= &exynos5_clk_ip_gscl_ctrl
,
875 .name
= SYSMMU_CLOCK_NAME
,
876 .devname
= SYSMMU_CLOCK_DEVNAME(gsc3
, 8),
877 .enable
= &exynos5_clk_ip_gscl_ctrl
,
878 .ctrlbit
= (1 << 10),
880 .name
= SYSMMU_CLOCK_NAME
,
881 .devname
= SYSMMU_CLOCK_DEVNAME(isp
, 9),
882 .enable
= &exynos5_clk_ip_isp0_ctrl
,
883 .ctrlbit
= (0x3F << 8),
885 .name
= SYSMMU_CLOCK_NAME2
,
886 .devname
= SYSMMU_CLOCK_DEVNAME(isp
, 9),
887 .enable
= &exynos5_clk_ip_isp1_ctrl
,
888 .ctrlbit
= (0xF << 4),
890 .name
= SYSMMU_CLOCK_NAME
,
891 .devname
= SYSMMU_CLOCK_DEVNAME(camif0
, 12),
892 .enable
= &exynos5_clk_ip_gscl_ctrl
,
893 .ctrlbit
= (1 << 11),
895 .name
= SYSMMU_CLOCK_NAME
,
896 .devname
= SYSMMU_CLOCK_DEVNAME(camif1
, 13),
897 .enable
= &exynos5_clk_ip_gscl_ctrl
,
898 .ctrlbit
= (1 << 12),
900 .name
= SYSMMU_CLOCK_NAME
,
901 .devname
= SYSMMU_CLOCK_DEVNAME(2d
, 14),
902 .enable
= &exynos5_clk_ip_acp_ctrl
,
907 static struct clk exynos5_init_clocks_on
[] = {
910 .devname
= "s5pv210-uart.0",
911 .enable
= exynos5_clk_ip_peric_ctrl
,
915 .devname
= "s5pv210-uart.1",
916 .enable
= exynos5_clk_ip_peric_ctrl
,
920 .devname
= "s5pv210-uart.2",
921 .enable
= exynos5_clk_ip_peric_ctrl
,
925 .devname
= "s5pv210-uart.3",
926 .enable
= exynos5_clk_ip_peric_ctrl
,
930 .devname
= "s5pv210-uart.4",
931 .enable
= exynos5_clk_ip_peric_ctrl
,
935 .devname
= "s5pv210-uart.5",
936 .enable
= exynos5_clk_ip_peric_ctrl
,
941 static struct clk exynos5_clk_pdma0
= {
943 .devname
= "dma-pl330.0",
944 .enable
= exynos5_clk_ip_fsys_ctrl
,
948 static struct clk exynos5_clk_pdma1
= {
950 .devname
= "dma-pl330.1",
951 .enable
= exynos5_clk_ip_fsys_ctrl
,
955 static struct clk exynos5_clk_mdma1
= {
957 .devname
= "dma-pl330.2",
958 .enable
= exynos5_clk_ip_gen_ctrl
,
962 static struct clk exynos5_clk_fimd1
= {
964 .devname
= "exynos5-fb.1",
965 .enable
= exynos5_clk_ip_disp1_ctrl
,
969 struct clk
*exynos5_clkset_group_list
[] = {
970 [0] = &clk_ext_xtal_mux
,
972 [2] = &exynos5_clk_sclk_hdmi24m
,
973 [3] = &exynos5_clk_sclk_dptxphy
,
974 [4] = &exynos5_clk_sclk_usbphy
,
975 [5] = &exynos5_clk_sclk_hdmiphy
,
976 [6] = &exynos5_clk_mout_mpll_user
.clk
,
977 [7] = &exynos5_clk_mout_epll
.clk
,
978 [8] = &exynos5_clk_sclk_vpll
.clk
,
979 [9] = &exynos5_clk_mout_cpll
.clk
,
982 struct clksrc_sources exynos5_clkset_group
= {
983 .sources
= exynos5_clkset_group_list
,
984 .nr_sources
= ARRAY_SIZE(exynos5_clkset_group_list
),
987 /* Possible clock sources for aclk_266_gscl_sub Mux */
988 static struct clk
*clk_src_gscl_266_list
[] = {
989 [0] = &clk_ext_xtal_mux
,
990 [1] = &exynos5_clk_aclk_266
.clk
,
993 static struct clksrc_sources clk_src_gscl_266
= {
994 .sources
= clk_src_gscl_266_list
,
995 .nr_sources
= ARRAY_SIZE(clk_src_gscl_266_list
),
998 static struct clksrc_clk exynos5_clk_dout_mmc0
= {
1000 .name
= "dout_mmc0",
1002 .sources
= &exynos5_clkset_group
,
1003 .reg_src
= { .reg
= EXYNOS5_CLKSRC_FSYS
, .shift
= 0, .size
= 4 },
1004 .reg_div
= { .reg
= EXYNOS5_CLKDIV_FSYS1
, .shift
= 0, .size
= 4 },
1007 static struct clksrc_clk exynos5_clk_dout_mmc1
= {
1009 .name
= "dout_mmc1",
1011 .sources
= &exynos5_clkset_group
,
1012 .reg_src
= { .reg
= EXYNOS5_CLKSRC_FSYS
, .shift
= 4, .size
= 4 },
1013 .reg_div
= { .reg
= EXYNOS5_CLKDIV_FSYS1
, .shift
= 16, .size
= 4 },
1016 static struct clksrc_clk exynos5_clk_dout_mmc2
= {
1018 .name
= "dout_mmc2",
1020 .sources
= &exynos5_clkset_group
,
1021 .reg_src
= { .reg
= EXYNOS5_CLKSRC_FSYS
, .shift
= 8, .size
= 4 },
1022 .reg_div
= { .reg
= EXYNOS5_CLKDIV_FSYS2
, .shift
= 0, .size
= 4 },
1025 static struct clksrc_clk exynos5_clk_dout_mmc3
= {
1027 .name
= "dout_mmc3",
1029 .sources
= &exynos5_clkset_group
,
1030 .reg_src
= { .reg
= EXYNOS5_CLKSRC_FSYS
, .shift
= 12, .size
= 4 },
1031 .reg_div
= { .reg
= EXYNOS5_CLKDIV_FSYS2
, .shift
= 16, .size
= 4 },
1034 static struct clksrc_clk exynos5_clk_dout_mmc4
= {
1036 .name
= "dout_mmc4",
1038 .sources
= &exynos5_clkset_group
,
1039 .reg_src
= { .reg
= EXYNOS5_CLKSRC_FSYS
, .shift
= 16, .size
= 4 },
1040 .reg_div
= { .reg
= EXYNOS5_CLKDIV_FSYS3
, .shift
= 0, .size
= 4 },
1043 static struct clksrc_clk exynos5_clk_sclk_uart0
= {
1046 .devname
= "exynos4210-uart.0",
1047 .enable
= exynos5_clksrc_mask_peric0_ctrl
,
1048 .ctrlbit
= (1 << 0),
1050 .sources
= &exynos5_clkset_group
,
1051 .reg_src
= { .reg
= EXYNOS5_CLKSRC_PERIC0
, .shift
= 0, .size
= 4 },
1052 .reg_div
= { .reg
= EXYNOS5_CLKDIV_PERIC0
, .shift
= 0, .size
= 4 },
1055 static struct clksrc_clk exynos5_clk_sclk_uart1
= {
1058 .devname
= "exynos4210-uart.1",
1059 .enable
= exynos5_clksrc_mask_peric0_ctrl
,
1060 .ctrlbit
= (1 << 4),
1062 .sources
= &exynos5_clkset_group
,
1063 .reg_src
= { .reg
= EXYNOS5_CLKSRC_PERIC0
, .shift
= 4, .size
= 4 },
1064 .reg_div
= { .reg
= EXYNOS5_CLKDIV_PERIC0
, .shift
= 4, .size
= 4 },
1067 static struct clksrc_clk exynos5_clk_sclk_uart2
= {
1070 .devname
= "exynos4210-uart.2",
1071 .enable
= exynos5_clksrc_mask_peric0_ctrl
,
1072 .ctrlbit
= (1 << 8),
1074 .sources
= &exynos5_clkset_group
,
1075 .reg_src
= { .reg
= EXYNOS5_CLKSRC_PERIC0
, .shift
= 8, .size
= 4 },
1076 .reg_div
= { .reg
= EXYNOS5_CLKDIV_PERIC0
, .shift
= 8, .size
= 4 },
1079 static struct clksrc_clk exynos5_clk_sclk_uart3
= {
1082 .devname
= "exynos4210-uart.3",
1083 .enable
= exynos5_clksrc_mask_peric0_ctrl
,
1084 .ctrlbit
= (1 << 12),
1086 .sources
= &exynos5_clkset_group
,
1087 .reg_src
= { .reg
= EXYNOS5_CLKSRC_PERIC0
, .shift
= 12, .size
= 4 },
1088 .reg_div
= { .reg
= EXYNOS5_CLKDIV_PERIC0
, .shift
= 12, .size
= 4 },
1091 static struct clksrc_clk exynos5_clk_sclk_mmc0
= {
1093 .name
= "ciu", /* card interface unit clock */
1094 .devname
= "dw_mmc.0",
1095 .parent
= &exynos5_clk_dout_mmc0
.clk
,
1096 .enable
= exynos5_clksrc_mask_fsys_ctrl
,
1097 .ctrlbit
= (1 << 0),
1099 .reg_div
= { .reg
= EXYNOS5_CLKDIV_FSYS1
, .shift
= 8, .size
= 8 },
1102 static struct clksrc_clk exynos5_clk_sclk_mmc1
= {
1105 .devname
= "dw_mmc.1",
1106 .parent
= &exynos5_clk_dout_mmc1
.clk
,
1107 .enable
= exynos5_clksrc_mask_fsys_ctrl
,
1108 .ctrlbit
= (1 << 4),
1110 .reg_div
= { .reg
= EXYNOS5_CLKDIV_FSYS1
, .shift
= 24, .size
= 8 },
1113 static struct clksrc_clk exynos5_clk_sclk_mmc2
= {
1116 .devname
= "dw_mmc.2",
1117 .parent
= &exynos5_clk_dout_mmc2
.clk
,
1118 .enable
= exynos5_clksrc_mask_fsys_ctrl
,
1119 .ctrlbit
= (1 << 8),
1121 .reg_div
= { .reg
= EXYNOS5_CLKDIV_FSYS2
, .shift
= 8, .size
= 8 },
1124 static struct clksrc_clk exynos5_clk_sclk_mmc3
= {
1127 .devname
= "dw_mmc.3",
1128 .parent
= &exynos5_clk_dout_mmc3
.clk
,
1129 .enable
= exynos5_clksrc_mask_fsys_ctrl
,
1130 .ctrlbit
= (1 << 12),
1132 .reg_div
= { .reg
= EXYNOS5_CLKDIV_FSYS2
, .shift
= 24, .size
= 8 },
1135 static struct clksrc_clk exynos5_clk_mdout_spi0
= {
1137 .name
= "mdout_spi",
1138 .devname
= "exynos4210-spi.0",
1140 .sources
= &exynos5_clkset_group
,
1141 .reg_src
= { .reg
= EXYNOS5_CLKSRC_PERIC1
, .shift
= 16, .size
= 4 },
1142 .reg_div
= { .reg
= EXYNOS5_CLKDIV_PERIC1
, .shift
= 0, .size
= 4 },
1145 static struct clksrc_clk exynos5_clk_mdout_spi1
= {
1147 .name
= "mdout_spi",
1148 .devname
= "exynos4210-spi.1",
1150 .sources
= &exynos5_clkset_group
,
1151 .reg_src
= { .reg
= EXYNOS5_CLKSRC_PERIC1
, .shift
= 20, .size
= 4 },
1152 .reg_div
= { .reg
= EXYNOS5_CLKDIV_PERIC1
, .shift
= 16, .size
= 4 },
1155 static struct clksrc_clk exynos5_clk_mdout_spi2
= {
1157 .name
= "mdout_spi",
1158 .devname
= "exynos4210-spi.2",
1160 .sources
= &exynos5_clkset_group
,
1161 .reg_src
= { .reg
= EXYNOS5_CLKSRC_PERIC1
, .shift
= 24, .size
= 4 },
1162 .reg_div
= { .reg
= EXYNOS5_CLKDIV_PERIC2
, .shift
= 0, .size
= 4 },
1165 static struct clksrc_clk exynos5_clk_sclk_spi0
= {
1168 .devname
= "exynos4210-spi.0",
1169 .parent
= &exynos5_clk_mdout_spi0
.clk
,
1170 .enable
= exynos5_clksrc_mask_peric1_ctrl
,
1171 .ctrlbit
= (1 << 16),
1173 .reg_div
= { .reg
= EXYNOS5_CLKDIV_PERIC1
, .shift
= 8, .size
= 8 },
1176 static struct clksrc_clk exynos5_clk_sclk_spi1
= {
1179 .devname
= "exynos4210-spi.1",
1180 .parent
= &exynos5_clk_mdout_spi1
.clk
,
1181 .enable
= exynos5_clksrc_mask_peric1_ctrl
,
1182 .ctrlbit
= (1 << 20),
1184 .reg_div
= { .reg
= EXYNOS5_CLKDIV_PERIC1
, .shift
= 24, .size
= 8 },
1187 static struct clksrc_clk exynos5_clk_sclk_spi2
= {
1190 .devname
= "exynos4210-spi.2",
1191 .parent
= &exynos5_clk_mdout_spi2
.clk
,
1192 .enable
= exynos5_clksrc_mask_peric1_ctrl
,
1193 .ctrlbit
= (1 << 24),
1195 .reg_div
= { .reg
= EXYNOS5_CLKDIV_PERIC2
, .shift
= 8, .size
= 8 },
1198 struct clksrc_clk exynos5_clk_sclk_fimd1
= {
1200 .name
= "sclk_fimd",
1201 .devname
= "exynos5-fb.1",
1202 .enable
= exynos5_clksrc_mask_disp1_0_ctrl
,
1203 .ctrlbit
= (1 << 0),
1205 .sources
= &exynos5_clkset_group
,
1206 .reg_src
= { .reg
= EXYNOS5_CLKSRC_DISP1_0
, .shift
= 0, .size
= 4 },
1207 .reg_div
= { .reg
= EXYNOS5_CLKDIV_DISP1_0
, .shift
= 0, .size
= 4 },
1210 static struct clksrc_clk exynos5_clksrcs
[] = {
1213 .name
= "aclk_266_gscl",
1215 .sources
= &clk_src_gscl_266
,
1216 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP3
, .shift
= 8, .size
= 1 },
1220 .devname
= "mali-t604.0",
1221 .enable
= exynos5_clk_block_ctrl
,
1222 .ctrlbit
= (1 << 1),
1224 .sources
= &exynos5_clkset_aclk
,
1225 .reg_src
= { .reg
= EXYNOS5_CLKSRC_TOP0
, .shift
= 20, .size
= 1 },
1226 .reg_div
= { .reg
= EXYNOS5_CLKDIV_TOP0
, .shift
= 24, .size
= 3 },
1229 .name
= "sclk_gscl_wrap",
1230 .devname
= "s5p-mipi-csis.0",
1231 .enable
= exynos5_clksrc_mask_gscl_ctrl
,
1232 .ctrlbit
= (1 << 24),
1234 .sources
= &exynos5_clkset_group
,
1235 .reg_src
= { .reg
= EXYNOS5_CLKSRC_GSCL
, .shift
= 24, .size
= 4 },
1236 .reg_div
= { .reg
= EXYNOS5_CLKDIV_GSCL
, .shift
= 24, .size
= 4 },
1239 .name
= "sclk_gscl_wrap",
1240 .devname
= "s5p-mipi-csis.1",
1241 .enable
= exynos5_clksrc_mask_gscl_ctrl
,
1242 .ctrlbit
= (1 << 28),
1244 .sources
= &exynos5_clkset_group
,
1245 .reg_src
= { .reg
= EXYNOS5_CLKSRC_GSCL
, .shift
= 28, .size
= 4 },
1246 .reg_div
= { .reg
= EXYNOS5_CLKDIV_GSCL
, .shift
= 28, .size
= 4 },
1249 .name
= "sclk_cam0",
1250 .enable
= exynos5_clksrc_mask_gscl_ctrl
,
1251 .ctrlbit
= (1 << 16),
1253 .sources
= &exynos5_clkset_group
,
1254 .reg_src
= { .reg
= EXYNOS5_CLKSRC_GSCL
, .shift
= 16, .size
= 4 },
1255 .reg_div
= { .reg
= EXYNOS5_CLKDIV_GSCL
, .shift
= 16, .size
= 4 },
1258 .name
= "sclk_cam1",
1259 .enable
= exynos5_clksrc_mask_gscl_ctrl
,
1260 .ctrlbit
= (1 << 20),
1262 .sources
= &exynos5_clkset_group
,
1263 .reg_src
= { .reg
= EXYNOS5_CLKSRC_GSCL
, .shift
= 20, .size
= 4 },
1264 .reg_div
= { .reg
= EXYNOS5_CLKDIV_GSCL
, .shift
= 20, .size
= 4 },
1267 .name
= "sclk_jpeg",
1268 .parent
= &exynos5_clk_mout_cpll
.clk
,
1270 .reg_div
= { .reg
= EXYNOS5_CLKDIV_GEN
, .shift
= 4, .size
= 3 },
1274 /* Clock initialization code */
1275 static struct clksrc_clk
*exynos5_sysclks
[] = {
1276 &exynos5_clk_mout_apll
,
1277 &exynos5_clk_sclk_apll
,
1278 &exynos5_clk_mout_bpll
,
1279 &exynos5_clk_mout_bpll_fout
,
1280 &exynos5_clk_mout_bpll_user
,
1281 &exynos5_clk_mout_cpll
,
1282 &exynos5_clk_mout_epll
,
1283 &exynos5_clk_mout_mpll
,
1284 &exynos5_clk_mout_mpll_fout
,
1285 &exynos5_clk_mout_mpll_user
,
1286 &exynos5_clk_vpllsrc
,
1287 &exynos5_clk_sclk_vpll
,
1288 &exynos5_clk_mout_cpu
,
1289 &exynos5_clk_dout_armclk
,
1290 &exynos5_clk_dout_arm2clk
,
1292 &exynos5_clk_aclk_400
,
1293 &exynos5_clk_aclk_333
,
1294 &exynos5_clk_aclk_266
,
1295 &exynos5_clk_aclk_200
,
1296 &exynos5_clk_aclk_166
,
1297 &exynos5_clk_aclk_300_gscl
,
1298 &exynos5_clk_mout_aclk_300_gscl
,
1299 &exynos5_clk_mout_aclk_300_gscl_mid
,
1300 &exynos5_clk_mout_aclk_300_gscl_mid1
,
1301 &exynos5_clk_aclk_66_pre
,
1302 &exynos5_clk_aclk_66
,
1303 &exynos5_clk_dout_mmc0
,
1304 &exynos5_clk_dout_mmc1
,
1305 &exynos5_clk_dout_mmc2
,
1306 &exynos5_clk_dout_mmc3
,
1307 &exynos5_clk_dout_mmc4
,
1308 &exynos5_clk_aclk_acp
,
1309 &exynos5_clk_pclk_acp
,
1310 &exynos5_clk_sclk_spi0
,
1311 &exynos5_clk_sclk_spi1
,
1312 &exynos5_clk_sclk_spi2
,
1313 &exynos5_clk_mdout_spi0
,
1314 &exynos5_clk_mdout_spi1
,
1315 &exynos5_clk_mdout_spi2
,
1316 &exynos5_clk_sclk_fimd1
,
1319 static struct clk
*exynos5_clk_cdev
[] = {
1326 static struct clksrc_clk
*exynos5_clksrc_cdev
[] = {
1327 &exynos5_clk_sclk_uart0
,
1328 &exynos5_clk_sclk_uart1
,
1329 &exynos5_clk_sclk_uart2
,
1330 &exynos5_clk_sclk_uart3
,
1331 &exynos5_clk_sclk_mmc0
,
1332 &exynos5_clk_sclk_mmc1
,
1333 &exynos5_clk_sclk_mmc2
,
1334 &exynos5_clk_sclk_mmc3
,
1337 static struct clk_lookup exynos5_clk_lookup
[] = {
1338 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0
.clk
),
1339 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1
.clk
),
1340 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2
.clk
),
1341 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3
.clk
),
1342 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0
.clk
),
1343 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1
.clk
),
1344 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2
.clk
),
1345 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3
.clk
),
1346 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0
.clk
),
1347 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1
.clk
),
1348 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2
.clk
),
1349 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0
),
1350 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1
),
1351 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1
),
1352 CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1
),
1355 static unsigned long exynos5_epll_get_rate(struct clk
*clk
)
1360 static struct clk
*exynos5_clks
[] __initdata
= {
1361 &exynos5_clk_sclk_hdmi27m
,
1362 &exynos5_clk_sclk_hdmiphy
,
1364 &clk_fout_bpll_div2
,
1366 &clk_fout_mpll_div2
,
1367 &exynos5_clk_armclk
,
1370 static u32 epll_div
[][6] = {
1371 { 192000000, 0, 48, 3, 1, 0 },
1372 { 180000000, 0, 45, 3, 1, 0 },
1373 { 73728000, 1, 73, 3, 3, 47710 },
1374 { 67737600, 1, 90, 4, 3, 20762 },
1375 { 49152000, 0, 49, 3, 3, 9961 },
1376 { 45158400, 0, 45, 3, 3, 10381 },
1377 { 180633600, 0, 45, 3, 1, 10381 },
1380 static int exynos5_epll_set_rate(struct clk
*clk
, unsigned long rate
)
1382 unsigned int epll_con
, epll_con_k
;
1385 unsigned int epll_rate
;
1386 unsigned int locktime
;
1387 unsigned int lockcnt
;
1389 /* Return if nothing changed */
1390 if (clk
->rate
== rate
)
1394 epll_rate
= clk_get_rate(clk
->parent
);
1396 epll_rate
= clk_ext_xtal_mux
.rate
;
1398 if (epll_rate
!= 24000000) {
1399 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1403 epll_con
= __raw_readl(EXYNOS5_EPLL_CON0
);
1404 epll_con
&= ~(0x1 << 27 | \
1405 PLL46XX_MDIV_MASK
<< PLL46XX_MDIV_SHIFT
| \
1406 PLL46XX_PDIV_MASK
<< PLL46XX_PDIV_SHIFT
| \
1407 PLL46XX_SDIV_MASK
<< PLL46XX_SDIV_SHIFT
);
1409 for (i
= 0; i
< ARRAY_SIZE(epll_div
); i
++) {
1410 if (epll_div
[i
][0] == rate
) {
1411 epll_con_k
= epll_div
[i
][5] << 0;
1412 epll_con
|= epll_div
[i
][1] << 27;
1413 epll_con
|= epll_div
[i
][2] << PLL46XX_MDIV_SHIFT
;
1414 epll_con
|= epll_div
[i
][3] << PLL46XX_PDIV_SHIFT
;
1415 epll_con
|= epll_div
[i
][4] << PLL46XX_SDIV_SHIFT
;
1420 if (i
== ARRAY_SIZE(epll_div
)) {
1421 printk(KERN_ERR
"%s: Invalid Clock EPLL Frequency\n",
1426 epll_rate
/= 1000000;
1428 /* 3000 max_cycls : specification data */
1429 locktime
= 3000 / epll_rate
* epll_div
[i
][3];
1430 lockcnt
= locktime
* 10000 / (10000 / epll_rate
);
1432 __raw_writel(lockcnt
, EXYNOS5_EPLL_LOCK
);
1434 __raw_writel(epll_con
, EXYNOS5_EPLL_CON0
);
1435 __raw_writel(epll_con_k
, EXYNOS5_EPLL_CON1
);
1438 tmp
= __raw_readl(EXYNOS5_EPLL_CON0
);
1439 } while (!(tmp
& 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT
));
1446 static struct clk_ops exynos5_epll_ops
= {
1447 .get_rate
= exynos5_epll_get_rate
,
1448 .set_rate
= exynos5_epll_set_rate
,
1451 static int xtal_rate
;
1453 static unsigned long exynos5_fout_apll_get_rate(struct clk
*clk
)
1455 return s5p_get_pll35xx(xtal_rate
, __raw_readl(EXYNOS5_APLL_CON0
));
1458 static struct clk_ops exynos5_fout_apll_ops
= {
1459 .get_rate
= exynos5_fout_apll_get_rate
,
1463 static int exynos5_clock_suspend(void)
1465 s3c_pm_do_save(exynos5_clock_save
, ARRAY_SIZE(exynos5_clock_save
));
1470 static void exynos5_clock_resume(void)
1472 s3c_pm_do_restore_core(exynos5_clock_save
, ARRAY_SIZE(exynos5_clock_save
));
1475 #define exynos5_clock_suspend NULL
1476 #define exynos5_clock_resume NULL
1479 struct syscore_ops exynos5_clock_syscore_ops
= {
1480 .suspend
= exynos5_clock_suspend
,
1481 .resume
= exynos5_clock_resume
,
1484 void __init_or_cpufreq
exynos5_setup_clocks(void)
1486 struct clk
*xtal_clk
;
1493 unsigned long vpllsrc
;
1495 unsigned long armclk
;
1496 unsigned long mout_cdrex
;
1497 unsigned long aclk_400
;
1498 unsigned long aclk_333
;
1499 unsigned long aclk_266
;
1500 unsigned long aclk_200
;
1501 unsigned long aclk_166
;
1502 unsigned long aclk_66
;
1505 printk(KERN_DEBUG
"%s: registering clocks\n", __func__
);
1507 xtal_clk
= clk_get(NULL
, "xtal");
1508 BUG_ON(IS_ERR(xtal_clk
));
1510 xtal
= clk_get_rate(xtal_clk
);
1516 printk(KERN_DEBUG
"%s: xtal is %ld\n", __func__
, xtal
);
1518 apll
= s5p_get_pll35xx(xtal
, __raw_readl(EXYNOS5_APLL_CON0
));
1519 bpll
= s5p_get_pll35xx(xtal
, __raw_readl(EXYNOS5_BPLL_CON0
));
1520 cpll
= s5p_get_pll35xx(xtal
, __raw_readl(EXYNOS5_CPLL_CON0
));
1521 mpll
= s5p_get_pll35xx(xtal
, __raw_readl(EXYNOS5_MPLL_CON0
));
1522 epll
= s5p_get_pll36xx(xtal
, __raw_readl(EXYNOS5_EPLL_CON0
),
1523 __raw_readl(EXYNOS5_EPLL_CON1
));
1525 vpllsrc
= clk_get_rate(&exynos5_clk_vpllsrc
.clk
);
1526 vpll
= s5p_get_pll36xx(vpllsrc
, __raw_readl(EXYNOS5_VPLL_CON0
),
1527 __raw_readl(EXYNOS5_VPLL_CON1
));
1529 clk_fout_apll
.ops
= &exynos5_fout_apll_ops
;
1530 clk_fout_bpll
.rate
= bpll
;
1531 clk_fout_bpll_div2
.rate
= bpll
>> 1;
1532 clk_fout_cpll
.rate
= cpll
;
1533 clk_fout_mpll
.rate
= mpll
;
1534 clk_fout_mpll_div2
.rate
= mpll
>> 1;
1535 clk_fout_epll
.rate
= epll
;
1536 clk_fout_vpll
.rate
= vpll
;
1538 printk(KERN_INFO
"EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1539 "M=%ld, E=%ld V=%ld",
1540 apll
, bpll
, cpll
, mpll
, epll
, vpll
);
1542 armclk
= clk_get_rate(&exynos5_clk_armclk
);
1543 mout_cdrex
= clk_get_rate(&exynos5_clk_cdrex
.clk
);
1545 aclk_400
= clk_get_rate(&exynos5_clk_aclk_400
.clk
);
1546 aclk_333
= clk_get_rate(&exynos5_clk_aclk_333
.clk
);
1547 aclk_266
= clk_get_rate(&exynos5_clk_aclk_266
.clk
);
1548 aclk_200
= clk_get_rate(&exynos5_clk_aclk_200
.clk
);
1549 aclk_166
= clk_get_rate(&exynos5_clk_aclk_166
.clk
);
1550 aclk_66
= clk_get_rate(&exynos5_clk_aclk_66
.clk
);
1552 printk(KERN_INFO
"EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1553 "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1554 "ACLK166=%ld, ACLK66=%ld\n",
1555 armclk
, mout_cdrex
, aclk_400
,
1556 aclk_333
, aclk_266
, aclk_200
,
1560 clk_fout_epll
.ops
= &exynos5_epll_ops
;
1562 if (clk_set_parent(&exynos5_clk_mout_epll
.clk
, &clk_fout_epll
))
1563 printk(KERN_ERR
"Unable to set parent %s of clock %s.\n",
1564 clk_fout_epll
.name
, exynos5_clk_mout_epll
.clk
.name
);
1566 clk_set_rate(&exynos5_clk_sclk_apll
.clk
, 100000000);
1567 clk_set_rate(&exynos5_clk_aclk_266
.clk
, 300000000);
1569 clk_set_rate(&exynos5_clk_aclk_acp
.clk
, 267000000);
1570 clk_set_rate(&exynos5_clk_pclk_acp
.clk
, 134000000);
1572 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos5_clksrcs
); ptr
++)
1573 s3c_set_clksrc(&exynos5_clksrcs
[ptr
], true);
1576 void __init
exynos5_register_clocks(void)
1580 s3c24xx_register_clocks(exynos5_clks
, ARRAY_SIZE(exynos5_clks
));
1582 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos5_sysclks
); ptr
++)
1583 s3c_register_clksrc(exynos5_sysclks
[ptr
], 1);
1585 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos5_sclk_tv
); ptr
++)
1586 s3c_register_clksrc(exynos5_sclk_tv
[ptr
], 1);
1588 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos5_clksrc_cdev
); ptr
++)
1589 s3c_register_clksrc(exynos5_clksrc_cdev
[ptr
], 1);
1591 s3c_register_clksrc(exynos5_clksrcs
, ARRAY_SIZE(exynos5_clksrcs
));
1592 s3c_register_clocks(exynos5_init_clocks_on
, ARRAY_SIZE(exynos5_init_clocks_on
));
1594 s3c24xx_register_clocks(exynos5_clk_cdev
, ARRAY_SIZE(exynos5_clk_cdev
));
1595 for (ptr
= 0; ptr
< ARRAY_SIZE(exynos5_clk_cdev
); ptr
++)
1596 s3c_disable_clocks(exynos5_clk_cdev
[ptr
], 1);
1598 s3c_register_clocks(exynos5_init_clocks_off
, ARRAY_SIZE(exynos5_init_clocks_off
));
1599 s3c_disable_clocks(exynos5_init_clocks_off
, ARRAY_SIZE(exynos5_init_clocks_off
));
1600 clkdev_add_table(exynos5_clk_lookup
, ARRAY_SIZE(exynos5_clk_lookup
));
1602 register_syscore_ops(&exynos5_clock_syscore_ops
);