2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Common Codes for EXYNOS
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/bitops.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/irqchip.h>
18 #include <linux/device.h>
19 #include <linux/gpio.h>
20 #include <clocksource/samsung_pwm.h>
21 #include <linux/sched.h>
22 #include <linux/serial_core.h>
24 #include <linux/of_fdt.h>
25 #include <linux/of_irq.h>
26 #include <linux/export.h>
27 #include <linux/irqdomain.h>
28 #include <linux/of_address.h>
29 #include <linux/clocksource.h>
30 #include <linux/clk-provider.h>
31 #include <linux/irqchip/arm-gic.h>
32 #include <linux/irqchip/chained_irq.h>
34 #include <asm/proc-fns.h>
35 #include <asm/exception.h>
36 #include <asm/hardware/cache-l2x0.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/irq.h>
39 #include <asm/cacheflush.h>
41 #include <mach/regs-irq.h>
42 #include <mach/regs-pmu.h>
46 #include <plat/regs-serial.h>
49 #define L2_AUX_VAL 0x7C470001
50 #define L2_AUX_MASK 0xC200ffff
52 static const char name_exynos4210
[] = "EXYNOS4210";
53 static const char name_exynos4212
[] = "EXYNOS4212";
54 static const char name_exynos4412
[] = "EXYNOS4412";
55 static const char name_exynos5250
[] = "EXYNOS5250";
56 static const char name_exynos5420
[] = "EXYNOS5420";
57 static const char name_exynos5440
[] = "EXYNOS5440";
59 static void exynos4_map_io(void);
60 static void exynos5_map_io(void);
61 static void exynos5440_map_io(void);
62 static int exynos_init(void);
64 static struct cpu_table cpu_ids
[] __initdata
= {
66 .idcode
= EXYNOS4210_CPU_ID
,
67 .idmask
= EXYNOS4_CPU_MASK
,
68 .map_io
= exynos4_map_io
,
70 .name
= name_exynos4210
,
72 .idcode
= EXYNOS4212_CPU_ID
,
73 .idmask
= EXYNOS4_CPU_MASK
,
74 .map_io
= exynos4_map_io
,
76 .name
= name_exynos4212
,
78 .idcode
= EXYNOS4412_CPU_ID
,
79 .idmask
= EXYNOS4_CPU_MASK
,
80 .map_io
= exynos4_map_io
,
82 .name
= name_exynos4412
,
84 .idcode
= EXYNOS5250_SOC_ID
,
85 .idmask
= EXYNOS5_SOC_MASK
,
86 .map_io
= exynos5_map_io
,
88 .name
= name_exynos5250
,
90 .idcode
= EXYNOS5420_SOC_ID
,
91 .idmask
= EXYNOS5_SOC_MASK
,
92 .map_io
= exynos5_map_io
,
94 .name
= name_exynos5420
,
96 .idcode
= EXYNOS5440_SOC_ID
,
97 .idmask
= EXYNOS5_SOC_MASK
,
98 .map_io
= exynos5440_map_io
,
100 .name
= name_exynos5440
,
104 /* Initial IO mappings */
106 static struct map_desc exynos4_iodesc
[] __initdata
= {
108 .virtual = (unsigned long)S3C_VA_SYS
,
109 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSCON
),
113 .virtual = (unsigned long)S3C_VA_TIMER
,
114 .pfn
= __phys_to_pfn(EXYNOS4_PA_TIMER
),
118 .virtual = (unsigned long)S3C_VA_WATCHDOG
,
119 .pfn
= __phys_to_pfn(EXYNOS4_PA_WATCHDOG
),
123 .virtual = (unsigned long)S5P_VA_SROMC
,
124 .pfn
= __phys_to_pfn(EXYNOS4_PA_SROMC
),
128 .virtual = (unsigned long)S5P_VA_SYSTIMER
,
129 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSTIMER
),
133 .virtual = (unsigned long)S5P_VA_PMU
,
134 .pfn
= __phys_to_pfn(EXYNOS4_PA_PMU
),
138 .virtual = (unsigned long)S5P_VA_COMBINER_BASE
,
139 .pfn
= __phys_to_pfn(EXYNOS4_PA_COMBINER
),
143 .virtual = (unsigned long)S5P_VA_GIC_CPU
,
144 .pfn
= __phys_to_pfn(EXYNOS4_PA_GIC_CPU
),
148 .virtual = (unsigned long)S5P_VA_GIC_DIST
,
149 .pfn
= __phys_to_pfn(EXYNOS4_PA_GIC_DIST
),
153 .virtual = (unsigned long)S3C_VA_UART
,
154 .pfn
= __phys_to_pfn(EXYNOS4_PA_UART
),
158 .virtual = (unsigned long)S5P_VA_CMU
,
159 .pfn
= __phys_to_pfn(EXYNOS4_PA_CMU
),
163 .virtual = (unsigned long)S5P_VA_COREPERI_BASE
,
164 .pfn
= __phys_to_pfn(EXYNOS4_PA_COREPERI
),
168 .virtual = (unsigned long)S5P_VA_L2CC
,
169 .pfn
= __phys_to_pfn(EXYNOS4_PA_L2CC
),
173 .virtual = (unsigned long)S5P_VA_DMC0
,
174 .pfn
= __phys_to_pfn(EXYNOS4_PA_DMC0
),
178 .virtual = (unsigned long)S5P_VA_DMC1
,
179 .pfn
= __phys_to_pfn(EXYNOS4_PA_DMC1
),
183 .virtual = (unsigned long)S3C_VA_USB_HSPHY
,
184 .pfn
= __phys_to_pfn(EXYNOS4_PA_HSPHY
),
190 static struct map_desc exynos4_iodesc0
[] __initdata
= {
192 .virtual = (unsigned long)S5P_VA_SYSRAM
,
193 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSRAM0
),
199 static struct map_desc exynos4_iodesc1
[] __initdata
= {
201 .virtual = (unsigned long)S5P_VA_SYSRAM
,
202 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSRAM1
),
208 static struct map_desc exynos4210_iodesc
[] __initdata
= {
210 .virtual = (unsigned long)S5P_VA_SYSRAM_NS
,
211 .pfn
= __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS
),
217 static struct map_desc exynos4x12_iodesc
[] __initdata
= {
219 .virtual = (unsigned long)S5P_VA_SYSRAM_NS
,
220 .pfn
= __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS
),
226 static struct map_desc exynos5250_iodesc
[] __initdata
= {
228 .virtual = (unsigned long)S5P_VA_SYSRAM_NS
,
229 .pfn
= __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS
),
235 static struct map_desc exynos5_iodesc
[] __initdata
= {
237 .virtual = (unsigned long)S3C_VA_SYS
,
238 .pfn
= __phys_to_pfn(EXYNOS5_PA_SYSCON
),
242 .virtual = (unsigned long)S3C_VA_TIMER
,
243 .pfn
= __phys_to_pfn(EXYNOS5_PA_TIMER
),
247 .virtual = (unsigned long)S3C_VA_WATCHDOG
,
248 .pfn
= __phys_to_pfn(EXYNOS5_PA_WATCHDOG
),
252 .virtual = (unsigned long)S5P_VA_SROMC
,
253 .pfn
= __phys_to_pfn(EXYNOS5_PA_SROMC
),
257 .virtual = (unsigned long)S5P_VA_SYSRAM
,
258 .pfn
= __phys_to_pfn(EXYNOS5_PA_SYSRAM
),
262 .virtual = (unsigned long)S5P_VA_CMU
,
263 .pfn
= __phys_to_pfn(EXYNOS5_PA_CMU
),
264 .length
= 144 * SZ_1K
,
267 .virtual = (unsigned long)S5P_VA_PMU
,
268 .pfn
= __phys_to_pfn(EXYNOS5_PA_PMU
),
272 .virtual = (unsigned long)S3C_VA_UART
,
273 .pfn
= __phys_to_pfn(EXYNOS5_PA_UART
),
279 static struct map_desc exynos5440_iodesc0
[] __initdata
= {
281 .virtual = (unsigned long)S3C_VA_UART
,
282 .pfn
= __phys_to_pfn(EXYNOS5440_PA_UART0
),
288 void exynos4_restart(enum reboot_mode mode
, const char *cmd
)
290 __raw_writel(0x1, S5P_SWRESET
);
293 void exynos5_restart(enum reboot_mode mode
, const char *cmd
)
295 struct device_node
*np
;
300 addr
= EXYNOS_SWRESET
;
302 if (of_machine_is_compatible("samsung,exynos5440")) {
304 np
= of_find_compatible_node(NULL
, NULL
, "samsung,exynos5440-clock");
306 addr
= of_iomap(np
, 0) + 0xbc;
307 status
= __raw_readl(addr
);
309 addr
= of_iomap(np
, 0) + 0xcc;
310 val
= __raw_readl(addr
);
312 val
= (val
& 0xffff0000) | (status
& 0xffff);
315 __raw_writel(val
, addr
);
318 void __init
exynos_init_late(void)
320 if (of_machine_is_compatible("samsung,exynos5440"))
321 /* to be supported later */
324 exynos_pm_late_initcall();
327 static int __init
exynos_fdt_map_chipid(unsigned long node
, const char *uname
,
328 int depth
, void *data
)
330 struct map_desc iodesc
;
334 if (!of_flat_dt_is_compatible(node
, "samsung,exynos4210-chipid") &&
335 !of_flat_dt_is_compatible(node
, "samsung,exynos5440-clock"))
338 reg
= of_get_flat_dt_prop(node
, "reg", &len
);
339 if (reg
== NULL
|| len
!= (sizeof(unsigned long) * 2))
342 iodesc
.pfn
= __phys_to_pfn(be32_to_cpu(reg
[0]));
343 iodesc
.length
= be32_to_cpu(reg
[1]) - 1;
344 iodesc
.virtual = (unsigned long)S5P_VA_CHIPID
;
345 iodesc
.type
= MT_DEVICE
;
346 iotable_init(&iodesc
, 1);
353 * register the standard cpu IO areas
356 void __init
exynos_init_io(void)
360 of_scan_flat_dt(exynos_fdt_map_chipid
, NULL
);
362 /* detect cpu id and rev. */
363 s5p_init_cpu(S5P_VA_CHIPID
);
365 s3c_init_cpu(samsung_cpu_id
, cpu_ids
, ARRAY_SIZE(cpu_ids
));
368 static void __init
exynos4_map_io(void)
370 iotable_init(exynos4_iodesc
, ARRAY_SIZE(exynos4_iodesc
));
372 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0
)
373 iotable_init(exynos4_iodesc0
, ARRAY_SIZE(exynos4_iodesc0
));
375 iotable_init(exynos4_iodesc1
, ARRAY_SIZE(exynos4_iodesc1
));
377 if (soc_is_exynos4210())
378 iotable_init(exynos4210_iodesc
, ARRAY_SIZE(exynos4210_iodesc
));
379 if (soc_is_exynos4212() || soc_is_exynos4412())
380 iotable_init(exynos4x12_iodesc
, ARRAY_SIZE(exynos4x12_iodesc
));
383 static void __init
exynos5_map_io(void)
385 iotable_init(exynos5_iodesc
, ARRAY_SIZE(exynos5_iodesc
));
387 if (soc_is_exynos5250())
388 iotable_init(exynos5250_iodesc
, ARRAY_SIZE(exynos5250_iodesc
));
391 static void __init
exynos5440_map_io(void)
393 iotable_init(exynos5440_iodesc0
, ARRAY_SIZE(exynos5440_iodesc0
));
396 void __init
exynos_init_time(void)
399 clocksource_of_init();
402 struct bus_type exynos_subsys
= {
403 .name
= "exynos-core",
404 .dev_name
= "exynos-core",
407 static struct device exynos4_dev
= {
408 .bus
= &exynos_subsys
,
411 static int __init
exynos_core_init(void)
413 return subsys_system_register(&exynos_subsys
, NULL
);
415 core_initcall(exynos_core_init
);
417 static int __init
exynos4_l2x0_cache_init(void)
421 ret
= l2x0_of_init(L2_AUX_VAL
, L2_AUX_MASK
);
425 l2x0_regs_phys
= virt_to_phys(&l2x0_saved_regs
);
426 clean_dcache_area(&l2x0_regs_phys
, sizeof(unsigned long));
429 early_initcall(exynos4_l2x0_cache_init
);
431 static int __init
exynos_init(void)
433 printk(KERN_INFO
"EXYNOS: Initializing architecture\n");
435 return device_register(&exynos4_dev
);