2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Common Codes for EXYNOS
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/irqchip.h>
17 #include <linux/device.h>
18 #include <linux/gpio.h>
19 #include <linux/sched.h>
20 #include <linux/serial_core.h>
22 #include <linux/of_fdt.h>
23 #include <linux/of_irq.h>
24 #include <linux/export.h>
25 #include <linux/irqdomain.h>
26 #include <linux/of_address.h>
27 #include <linux/clocksource.h>
28 #include <linux/clk-provider.h>
29 #include <linux/irqchip/arm-gic.h>
30 #include <linux/irqchip/chained_irq.h>
32 #include <asm/proc-fns.h>
33 #include <asm/exception.h>
34 #include <asm/hardware/cache-l2x0.h>
35 #include <asm/mach/map.h>
36 #include <asm/mach/irq.h>
37 #include <asm/cacheflush.h>
39 #include <mach/regs-irq.h>
40 #include <mach/regs-pmu.h>
41 #include <mach/regs-gpio.h>
42 #include <mach/irqs.h>
45 #include <plat/devs.h>
47 #include <plat/sdhci.h>
48 #include <plat/gpio-cfg.h>
49 #include <plat/adc-core.h>
50 #include <plat/fb-core.h>
51 #include <plat/fimc-core.h>
52 #include <plat/iic-core.h>
53 #include <plat/tv-core.h>
54 #include <plat/spi-core.h>
55 #include <plat/regs-serial.h>
58 #define L2_AUX_VAL 0x7C470001
59 #define L2_AUX_MASK 0xC200ffff
61 static const char name_exynos4210
[] = "EXYNOS4210";
62 static const char name_exynos4212
[] = "EXYNOS4212";
63 static const char name_exynos4412
[] = "EXYNOS4412";
64 static const char name_exynos5250
[] = "EXYNOS5250";
65 static const char name_exynos5440
[] = "EXYNOS5440";
67 static void exynos4_map_io(void);
68 static void exynos5_map_io(void);
69 static void exynos5440_map_io(void);
70 static void exynos4_init_uarts(struct s3c2410_uartcfg
*cfg
, int no
);
71 static int exynos_init(void);
73 unsigned long xxti_f
= 0, xusbxti_f
= 0;
75 static struct cpu_table cpu_ids
[] __initdata
= {
77 .idcode
= EXYNOS4210_CPU_ID
,
78 .idmask
= EXYNOS4_CPU_MASK
,
79 .map_io
= exynos4_map_io
,
80 .init_uarts
= exynos4_init_uarts
,
82 .name
= name_exynos4210
,
84 .idcode
= EXYNOS4212_CPU_ID
,
85 .idmask
= EXYNOS4_CPU_MASK
,
86 .map_io
= exynos4_map_io
,
87 .init_uarts
= exynos4_init_uarts
,
89 .name
= name_exynos4212
,
91 .idcode
= EXYNOS4412_CPU_ID
,
92 .idmask
= EXYNOS4_CPU_MASK
,
93 .map_io
= exynos4_map_io
,
94 .init_uarts
= exynos4_init_uarts
,
96 .name
= name_exynos4412
,
98 .idcode
= EXYNOS5250_SOC_ID
,
99 .idmask
= EXYNOS5_SOC_MASK
,
100 .map_io
= exynos5_map_io
,
102 .name
= name_exynos5250
,
104 .idcode
= EXYNOS5440_SOC_ID
,
105 .idmask
= EXYNOS5_SOC_MASK
,
106 .map_io
= exynos5440_map_io
,
108 .name
= name_exynos5440
,
112 /* Initial IO mappings */
114 static struct map_desc exynos_iodesc
[] __initdata
= {
116 .virtual = (unsigned long)S5P_VA_CHIPID
,
117 .pfn
= __phys_to_pfn(EXYNOS_PA_CHIPID
),
123 static struct map_desc exynos4_iodesc
[] __initdata
= {
125 .virtual = (unsigned long)S3C_VA_SYS
,
126 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSCON
),
130 .virtual = (unsigned long)S3C_VA_TIMER
,
131 .pfn
= __phys_to_pfn(EXYNOS4_PA_TIMER
),
135 .virtual = (unsigned long)S3C_VA_WATCHDOG
,
136 .pfn
= __phys_to_pfn(EXYNOS4_PA_WATCHDOG
),
140 .virtual = (unsigned long)S5P_VA_SROMC
,
141 .pfn
= __phys_to_pfn(EXYNOS4_PA_SROMC
),
145 .virtual = (unsigned long)S5P_VA_SYSTIMER
,
146 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSTIMER
),
150 .virtual = (unsigned long)S5P_VA_PMU
,
151 .pfn
= __phys_to_pfn(EXYNOS4_PA_PMU
),
155 .virtual = (unsigned long)S5P_VA_COMBINER_BASE
,
156 .pfn
= __phys_to_pfn(EXYNOS4_PA_COMBINER
),
160 .virtual = (unsigned long)S5P_VA_GIC_CPU
,
161 .pfn
= __phys_to_pfn(EXYNOS4_PA_GIC_CPU
),
165 .virtual = (unsigned long)S5P_VA_GIC_DIST
,
166 .pfn
= __phys_to_pfn(EXYNOS4_PA_GIC_DIST
),
170 .virtual = (unsigned long)S3C_VA_UART
,
171 .pfn
= __phys_to_pfn(EXYNOS4_PA_UART
),
175 .virtual = (unsigned long)S5P_VA_CMU
,
176 .pfn
= __phys_to_pfn(EXYNOS4_PA_CMU
),
180 .virtual = (unsigned long)S5P_VA_COREPERI_BASE
,
181 .pfn
= __phys_to_pfn(EXYNOS4_PA_COREPERI
),
185 .virtual = (unsigned long)S5P_VA_L2CC
,
186 .pfn
= __phys_to_pfn(EXYNOS4_PA_L2CC
),
190 .virtual = (unsigned long)S5P_VA_DMC0
,
191 .pfn
= __phys_to_pfn(EXYNOS4_PA_DMC0
),
195 .virtual = (unsigned long)S5P_VA_DMC1
,
196 .pfn
= __phys_to_pfn(EXYNOS4_PA_DMC1
),
200 .virtual = (unsigned long)S3C_VA_USB_HSPHY
,
201 .pfn
= __phys_to_pfn(EXYNOS4_PA_HSPHY
),
207 static struct map_desc exynos4_iodesc0
[] __initdata
= {
209 .virtual = (unsigned long)S5P_VA_SYSRAM
,
210 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSRAM0
),
216 static struct map_desc exynos4_iodesc1
[] __initdata
= {
218 .virtual = (unsigned long)S5P_VA_SYSRAM
,
219 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSRAM1
),
225 static struct map_desc exynos4210_iodesc
[] __initdata
= {
227 .virtual = (unsigned long)S5P_VA_SYSRAM_NS
,
228 .pfn
= __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS
),
234 static struct map_desc exynos4x12_iodesc
[] __initdata
= {
236 .virtual = (unsigned long)S5P_VA_SYSRAM_NS
,
237 .pfn
= __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS
),
243 static struct map_desc exynos5250_iodesc
[] __initdata
= {
245 .virtual = (unsigned long)S5P_VA_SYSRAM_NS
,
246 .pfn
= __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS
),
252 static struct map_desc exynos5_iodesc
[] __initdata
= {
254 .virtual = (unsigned long)S3C_VA_SYS
,
255 .pfn
= __phys_to_pfn(EXYNOS5_PA_SYSCON
),
259 .virtual = (unsigned long)S3C_VA_TIMER
,
260 .pfn
= __phys_to_pfn(EXYNOS5_PA_TIMER
),
264 .virtual = (unsigned long)S3C_VA_WATCHDOG
,
265 .pfn
= __phys_to_pfn(EXYNOS5_PA_WATCHDOG
),
269 .virtual = (unsigned long)S5P_VA_SROMC
,
270 .pfn
= __phys_to_pfn(EXYNOS5_PA_SROMC
),
274 .virtual = (unsigned long)S5P_VA_SYSRAM
,
275 .pfn
= __phys_to_pfn(EXYNOS5_PA_SYSRAM
),
279 .virtual = (unsigned long)S5P_VA_CMU
,
280 .pfn
= __phys_to_pfn(EXYNOS5_PA_CMU
),
281 .length
= 144 * SZ_1K
,
284 .virtual = (unsigned long)S5P_VA_PMU
,
285 .pfn
= __phys_to_pfn(EXYNOS5_PA_PMU
),
289 .virtual = (unsigned long)S3C_VA_UART
,
290 .pfn
= __phys_to_pfn(EXYNOS5_PA_UART
),
296 static struct map_desc exynos5440_iodesc0
[] __initdata
= {
298 .virtual = (unsigned long)S3C_VA_UART
,
299 .pfn
= __phys_to_pfn(EXYNOS5440_PA_UART0
),
305 void exynos4_restart(char mode
, const char *cmd
)
307 __raw_writel(0x1, S5P_SWRESET
);
310 void exynos5_restart(char mode
, const char *cmd
)
312 struct device_node
*np
;
316 if (of_machine_is_compatible("samsung,exynos5250")) {
318 addr
= EXYNOS_SWRESET
;
319 } else if (of_machine_is_compatible("samsung,exynos5440")) {
320 np
= of_find_compatible_node(NULL
, NULL
, "samsung,exynos5440-clock");
321 addr
= of_iomap(np
, 0) + 0xcc;
322 val
= (0xfff << 20) | (0x1 << 16);
324 pr_err("%s: cannot support non-DT\n", __func__
);
328 __raw_writel(val
, addr
);
331 void __init
exynos_init_late(void)
333 if (of_machine_is_compatible("samsung,exynos5440"))
334 /* to be supported later */
337 exynos_pm_late_initcall();
341 int __init
exynos_fdt_map_chipid(unsigned long node
, const char *uname
,
342 int depth
, void *data
)
344 struct map_desc iodesc
;
348 if (!of_flat_dt_is_compatible(node
, "samsung,exynos4210-chipid") &&
349 !of_flat_dt_is_compatible(node
, "samsung,exynos5440-clock"))
352 reg
= of_get_flat_dt_prop(node
, "reg", &len
);
353 if (reg
== NULL
|| len
!= (sizeof(unsigned long) * 2))
356 iodesc
.pfn
= __phys_to_pfn(be32_to_cpu(reg
[0]));
357 iodesc
.length
= be32_to_cpu(reg
[1]) - 1;
358 iodesc
.virtual = (unsigned long)S5P_VA_CHIPID
;
359 iodesc
.type
= MT_DEVICE
;
360 iotable_init(&iodesc
, 1);
368 * register the standard cpu IO areas
371 void __init
exynos_init_io(struct map_desc
*mach_desc
, int size
)
374 if (initial_boot_params
)
375 of_scan_flat_dt(exynos_fdt_map_chipid
, NULL
);
378 iotable_init(exynos_iodesc
, ARRAY_SIZE(exynos_iodesc
));
381 iotable_init(mach_desc
, size
);
383 /* detect cpu id and rev. */
384 s5p_init_cpu(S5P_VA_CHIPID
);
386 s3c_init_cpu(samsung_cpu_id
, cpu_ids
, ARRAY_SIZE(cpu_ids
));
389 static void __init
exynos4_map_io(void)
391 iotable_init(exynos4_iodesc
, ARRAY_SIZE(exynos4_iodesc
));
393 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0
)
394 iotable_init(exynos4_iodesc0
, ARRAY_SIZE(exynos4_iodesc0
));
396 iotable_init(exynos4_iodesc1
, ARRAY_SIZE(exynos4_iodesc1
));
398 if (soc_is_exynos4210())
399 iotable_init(exynos4210_iodesc
, ARRAY_SIZE(exynos4210_iodesc
));
400 if (soc_is_exynos4212() || soc_is_exynos4412())
401 iotable_init(exynos4x12_iodesc
, ARRAY_SIZE(exynos4x12_iodesc
));
403 /* initialize device information early */
404 exynos4_default_sdhci0();
405 exynos4_default_sdhci1();
406 exynos4_default_sdhci2();
407 exynos4_default_sdhci3();
409 s3c_adc_setname("samsung-adc-v3");
411 s3c_fimc_setname(0, "exynos4-fimc");
412 s3c_fimc_setname(1, "exynos4-fimc");
413 s3c_fimc_setname(2, "exynos4-fimc");
414 s3c_fimc_setname(3, "exynos4-fimc");
416 s3c_sdhci_setname(0, "exynos4-sdhci");
417 s3c_sdhci_setname(1, "exynos4-sdhci");
418 s3c_sdhci_setname(2, "exynos4-sdhci");
419 s3c_sdhci_setname(3, "exynos4-sdhci");
421 /* The I2C bus controllers are directly compatible with s3c2440 */
422 s3c_i2c0_setname("s3c2440-i2c");
423 s3c_i2c1_setname("s3c2440-i2c");
424 s3c_i2c2_setname("s3c2440-i2c");
426 s5p_fb_setname(0, "exynos4-fb");
427 s5p_hdmi_setname("exynos4-hdmi");
429 s3c64xx_spi_setname("exynos4210-spi");
432 static void __init
exynos5_map_io(void)
434 iotable_init(exynos5_iodesc
, ARRAY_SIZE(exynos5_iodesc
));
436 if (soc_is_exynos5250())
437 iotable_init(exynos5250_iodesc
, ARRAY_SIZE(exynos5250_iodesc
));
440 static void __init
exynos5440_map_io(void)
442 iotable_init(exynos5440_iodesc0
, ARRAY_SIZE(exynos5440_iodesc0
));
445 void __init
exynos_init_time(void)
447 if (of_have_populated_dt()) {
450 clocksource_of_init();
453 /* todo: remove after migrating legacy E4 platforms to dt */
454 #ifdef CONFIG_ARCH_EXYNOS4
455 exynos4_clk_init(NULL
, !soc_is_exynos4210(), S5P_VA_CMU
, readl(S5P_VA_CHIPID
+ 8) & 1);
456 exynos4_clk_register_fixed_ext(xxti_f
, xusbxti_f
);
458 mct_init(S5P_VA_SYSTIMER
, EXYNOS4_IRQ_MCT_G0
, EXYNOS4_IRQ_MCT_L0
, EXYNOS4_IRQ_MCT_L1
);
462 static unsigned int max_combiner_nr(void)
464 if (soc_is_exynos5250())
465 return EXYNOS5_MAX_COMBINER_NR
;
466 else if (soc_is_exynos4412())
467 return EXYNOS4412_MAX_COMBINER_NR
;
468 else if (soc_is_exynos4212())
469 return EXYNOS4212_MAX_COMBINER_NR
;
471 return EXYNOS4210_MAX_COMBINER_NR
;
475 void __init
exynos4_init_irq(void)
477 unsigned int gic_bank_offset
;
479 gic_bank_offset
= soc_is_exynos4412() ? 0x4000 : 0x8000;
481 if (!of_have_populated_dt())
482 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST
, S5P_VA_GIC_CPU
, gic_bank_offset
, NULL
);
488 if (!of_have_populated_dt())
489 combiner_init(S5P_VA_COMBINER_BASE
, NULL
,
490 max_combiner_nr(), COMBINER_IRQ(0, 0));
492 gic_arch_extn
.irq_set_wake
= s3c_irq_wake
;
495 void __init
exynos5_init_irq(void)
500 gic_arch_extn
.irq_set_wake
= s3c_irq_wake
;
503 struct bus_type exynos_subsys
= {
504 .name
= "exynos-core",
505 .dev_name
= "exynos-core",
508 static struct device exynos4_dev
= {
509 .bus
= &exynos_subsys
,
512 static int __init
exynos_core_init(void)
514 return subsys_system_register(&exynos_subsys
, NULL
);
516 core_initcall(exynos_core_init
);
518 #ifdef CONFIG_CACHE_L2X0
519 static int __init
exynos4_l2x0_cache_init(void)
523 if (soc_is_exynos5250() || soc_is_exynos5440())
526 ret
= l2x0_of_init(L2_AUX_VAL
, L2_AUX_MASK
);
528 l2x0_regs_phys
= virt_to_phys(&l2x0_saved_regs
);
529 clean_dcache_area(&l2x0_regs_phys
, sizeof(unsigned long));
533 if (!(__raw_readl(S5P_VA_L2CC
+ L2X0_CTRL
) & 0x1)) {
534 l2x0_saved_regs
.phy_base
= EXYNOS4_PA_L2CC
;
535 /* TAG, Data Latency Control: 2 cycles */
536 l2x0_saved_regs
.tag_latency
= 0x110;
538 if (soc_is_exynos4212() || soc_is_exynos4412())
539 l2x0_saved_regs
.data_latency
= 0x120;
541 l2x0_saved_regs
.data_latency
= 0x110;
543 l2x0_saved_regs
.prefetch_ctrl
= 0x30000007;
544 l2x0_saved_regs
.pwr_ctrl
=
545 (L2X0_DYNAMIC_CLK_GATING_EN
| L2X0_STNDBY_MODE_EN
);
547 l2x0_regs_phys
= virt_to_phys(&l2x0_saved_regs
);
549 __raw_writel(l2x0_saved_regs
.tag_latency
,
550 S5P_VA_L2CC
+ L2X0_TAG_LATENCY_CTRL
);
551 __raw_writel(l2x0_saved_regs
.data_latency
,
552 S5P_VA_L2CC
+ L2X0_DATA_LATENCY_CTRL
);
554 /* L2X0 Prefetch Control */
555 __raw_writel(l2x0_saved_regs
.prefetch_ctrl
,
556 S5P_VA_L2CC
+ L2X0_PREFETCH_CTRL
);
558 /* L2X0 Power Control */
559 __raw_writel(l2x0_saved_regs
.pwr_ctrl
,
560 S5P_VA_L2CC
+ L2X0_POWER_CTRL
);
562 clean_dcache_area(&l2x0_regs_phys
, sizeof(unsigned long));
563 clean_dcache_area(&l2x0_saved_regs
, sizeof(struct l2x0_regs
));
566 l2x0_init(S5P_VA_L2CC
, L2_AUX_VAL
, L2_AUX_MASK
);
569 early_initcall(exynos4_l2x0_cache_init
);
572 static int __init
exynos_init(void)
574 printk(KERN_INFO
"EXYNOS: Initializing architecture\n");
576 return device_register(&exynos4_dev
);
579 /* uart registration process */
581 static void __init
exynos4_init_uarts(struct s3c2410_uartcfg
*cfg
, int no
)
583 struct s3c2410_uartcfg
*tcfg
= cfg
;
586 for (ucnt
= 0; ucnt
< no
; ucnt
++, tcfg
++)
587 tcfg
->has_fracval
= 1;
589 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources
, cfg
, no
);
592 static void __iomem
*exynos_eint_base
;
594 static DEFINE_SPINLOCK(eint_lock
);
596 static unsigned int eint0_15_data
[16];
598 static inline int exynos4_irq_to_gpio(unsigned int irq
)
600 if (irq
< IRQ_EINT(0))
605 return EXYNOS4_GPX0(irq
);
609 return EXYNOS4_GPX1(irq
);
613 return EXYNOS4_GPX2(irq
);
617 return EXYNOS4_GPX3(irq
);
622 static inline int exynos5_irq_to_gpio(unsigned int irq
)
624 if (irq
< IRQ_EINT(0))
629 return EXYNOS5_GPX0(irq
);
633 return EXYNOS5_GPX1(irq
);
637 return EXYNOS5_GPX2(irq
);
641 return EXYNOS5_GPX3(irq
);
646 static unsigned int exynos4_eint0_15_src_int
[16] = {
665 static unsigned int exynos5_eint0_15_src_int
[16] = {
683 static inline void exynos_irq_eint_mask(struct irq_data
*data
)
687 spin_lock(&eint_lock
);
688 mask
= __raw_readl(EINT_MASK(exynos_eint_base
, data
->irq
));
689 mask
|= EINT_OFFSET_BIT(data
->irq
);
690 __raw_writel(mask
, EINT_MASK(exynos_eint_base
, data
->irq
));
691 spin_unlock(&eint_lock
);
694 static void exynos_irq_eint_unmask(struct irq_data
*data
)
698 spin_lock(&eint_lock
);
699 mask
= __raw_readl(EINT_MASK(exynos_eint_base
, data
->irq
));
700 mask
&= ~(EINT_OFFSET_BIT(data
->irq
));
701 __raw_writel(mask
, EINT_MASK(exynos_eint_base
, data
->irq
));
702 spin_unlock(&eint_lock
);
705 static inline void exynos_irq_eint_ack(struct irq_data
*data
)
707 __raw_writel(EINT_OFFSET_BIT(data
->irq
),
708 EINT_PEND(exynos_eint_base
, data
->irq
));
711 static void exynos_irq_eint_maskack(struct irq_data
*data
)
713 exynos_irq_eint_mask(data
);
714 exynos_irq_eint_ack(data
);
717 static int exynos_irq_eint_set_type(struct irq_data
*data
, unsigned int type
)
719 int offs
= EINT_OFFSET(data
->irq
);
725 case IRQ_TYPE_EDGE_RISING
:
726 newvalue
= S5P_IRQ_TYPE_EDGE_RISING
;
729 case IRQ_TYPE_EDGE_FALLING
:
730 newvalue
= S5P_IRQ_TYPE_EDGE_FALLING
;
733 case IRQ_TYPE_EDGE_BOTH
:
734 newvalue
= S5P_IRQ_TYPE_EDGE_BOTH
;
737 case IRQ_TYPE_LEVEL_LOW
:
738 newvalue
= S5P_IRQ_TYPE_LEVEL_LOW
;
741 case IRQ_TYPE_LEVEL_HIGH
:
742 newvalue
= S5P_IRQ_TYPE_LEVEL_HIGH
;
746 printk(KERN_ERR
"No such irq type %d", type
);
750 shift
= (offs
& 0x7) * 4;
753 spin_lock(&eint_lock
);
754 ctrl
= __raw_readl(EINT_CON(exynos_eint_base
, data
->irq
));
756 ctrl
|= newvalue
<< shift
;
757 __raw_writel(ctrl
, EINT_CON(exynos_eint_base
, data
->irq
));
758 spin_unlock(&eint_lock
);
760 if (soc_is_exynos5250())
761 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data
->irq
), S3C_GPIO_SFN(0xf));
763 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data
->irq
), S3C_GPIO_SFN(0xf));
768 static struct irq_chip exynos_irq_eint
= {
769 .name
= "exynos-eint",
770 .irq_mask
= exynos_irq_eint_mask
,
771 .irq_unmask
= exynos_irq_eint_unmask
,
772 .irq_mask_ack
= exynos_irq_eint_maskack
,
773 .irq_ack
= exynos_irq_eint_ack
,
774 .irq_set_type
= exynos_irq_eint_set_type
,
776 .irq_set_wake
= s3c_irqext_wake
,
781 * exynos4_irq_demux_eint
783 * This function demuxes the IRQ from from EINTs 16 to 31.
784 * It is designed to be inlined into the specific handler
785 * s5p_irq_demux_eintX_Y.
787 * Each EINT pend/mask registers handle eight of them.
789 static inline void exynos_irq_demux_eint(unsigned int start
)
793 u32 status
= __raw_readl(EINT_PEND(exynos_eint_base
, start
));
794 u32 mask
= __raw_readl(EINT_MASK(exynos_eint_base
, start
));
800 irq
= fls(status
) - 1;
801 generic_handle_irq(irq
+ start
);
802 status
&= ~(1 << irq
);
806 static void exynos_irq_demux_eint16_31(unsigned int irq
, struct irq_desc
*desc
)
808 struct irq_chip
*chip
= irq_get_chip(irq
);
809 chained_irq_enter(chip
, desc
);
810 exynos_irq_demux_eint(IRQ_EINT(16));
811 exynos_irq_demux_eint(IRQ_EINT(24));
812 chained_irq_exit(chip
, desc
);
815 static void exynos_irq_eint0_15(unsigned int irq
, struct irq_desc
*desc
)
817 u32
*irq_data
= irq_get_handler_data(irq
);
818 struct irq_chip
*chip
= irq_get_chip(irq
);
820 chained_irq_enter(chip
, desc
);
821 generic_handle_irq(*irq_data
);
822 chained_irq_exit(chip
, desc
);
825 static int __init
exynos_init_irq_eint(void)
829 #ifdef CONFIG_PINCTRL_SAMSUNG
831 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
832 * functionality along with support for external gpio and wakeup
833 * interrupts. If the samsung pinctrl driver is enabled and includes
834 * the wakeup interrupt support, then the setting up external wakeup
835 * interrupts here can be skipped. This check here is temporary to
836 * allow exynos4 platforms that do not use Samsung pinctrl driver to
837 * co-exist with platforms that do. When all of the Samsung Exynos4
838 * platforms switch over to using the pinctrl driver, the wakeup
839 * interrupt support code here can be completely removed.
841 static const struct of_device_id exynos_pinctrl_ids
[] = {
842 { .compatible
= "samsung,exynos4210-pinctrl", },
843 { .compatible
= "samsung,exynos4x12-pinctrl", },
844 { .compatible
= "samsung,exynos5250-pinctrl", },
846 struct device_node
*pctrl_np
, *wkup_np
;
847 const char *wkup_compat
= "samsung,exynos4210-wakeup-eint";
849 for_each_matching_node(pctrl_np
, exynos_pinctrl_ids
) {
850 if (of_device_is_available(pctrl_np
)) {
851 wkup_np
= of_find_compatible_node(pctrl_np
, NULL
,
858 if (soc_is_exynos5440())
861 if (soc_is_exynos5250())
862 exynos_eint_base
= ioremap(EXYNOS5_PA_GPIO1
, SZ_4K
);
864 exynos_eint_base
= ioremap(EXYNOS4_PA_GPIO2
, SZ_4K
);
866 if (exynos_eint_base
== NULL
) {
867 pr_err("unable to ioremap for EINT base address\n");
871 for (irq
= 0 ; irq
<= 31 ; irq
++) {
872 irq_set_chip_and_handler(IRQ_EINT(irq
), &exynos_irq_eint
,
874 set_irq_flags(IRQ_EINT(irq
), IRQF_VALID
);
877 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31
, exynos_irq_demux_eint16_31
);
879 for (irq
= 0 ; irq
<= 15 ; irq
++) {
880 eint0_15_data
[irq
] = IRQ_EINT(irq
);
882 if (soc_is_exynos5250()) {
883 irq_set_handler_data(exynos5_eint0_15_src_int
[irq
],
884 &eint0_15_data
[irq
]);
885 irq_set_chained_handler(exynos5_eint0_15_src_int
[irq
],
886 exynos_irq_eint0_15
);
888 irq_set_handler_data(exynos4_eint0_15_src_int
[irq
],
889 &eint0_15_data
[irq
]);
890 irq_set_chained_handler(exynos4_eint0_15_src_int
[irq
],
891 exynos_irq_eint0_15
);
897 arch_initcall(exynos_init_irq_eint
);
899 static struct resource exynos4_pmu_resource
[] = {
900 DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU
),
901 DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1
),
902 #if defined(CONFIG_SOC_EXYNOS4412)
903 DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2
),
904 DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3
),
908 static struct platform_device exynos4_device_pmu
= {
910 .num_resources
= ARRAY_SIZE(exynos4_pmu_resource
),
911 .resource
= exynos4_pmu_resource
,
914 static int __init
exynos_armpmu_init(void)
916 if (!of_have_populated_dt()) {
917 if (soc_is_exynos4210() || soc_is_exynos4212())
918 exynos4_device_pmu
.num_resources
= 2;
919 platform_device_register(&exynos4_device_pmu
);
924 arch_initcall(exynos_armpmu_init
);