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Merge branch 'next/soc-exynos5250-gpio' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / mach-exynos / common.c
1 /*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/io.h>
16 #include <linux/device.h>
17 #include <linux/gpio.h>
18 #include <linux/sched.h>
19 #include <linux/serial_core.h>
20 #include <linux/of.h>
21 #include <linux/of_irq.h>
22
23 #include <asm/proc-fns.h>
24 #include <asm/exception.h>
25 #include <asm/hardware/cache-l2x0.h>
26 #include <asm/hardware/gic.h>
27 #include <asm/mach/map.h>
28 #include <asm/mach/irq.h>
29
30 #include <mach/regs-irq.h>
31 #include <mach/regs-pmu.h>
32 #include <mach/regs-gpio.h>
33
34 #include <plat/cpu.h>
35 #include <plat/clock.h>
36 #include <plat/devs.h>
37 #include <plat/pm.h>
38 #include <plat/sdhci.h>
39 #include <plat/gpio-cfg.h>
40 #include <plat/adc-core.h>
41 #include <plat/fb-core.h>
42 #include <plat/fimc-core.h>
43 #include <plat/iic-core.h>
44 #include <plat/tv-core.h>
45 #include <plat/regs-serial.h>
46
47 #include "common.h"
48
49 static const char name_exynos4210[] = "EXYNOS4210";
50 static const char name_exynos4212[] = "EXYNOS4212";
51 static const char name_exynos4412[] = "EXYNOS4412";
52
53 static struct cpu_table cpu_ids[] __initdata = {
54 {
55 .idcode = EXYNOS4210_CPU_ID,
56 .idmask = EXYNOS4_CPU_MASK,
57 .map_io = exynos4_map_io,
58 .init_clocks = exynos4_init_clocks,
59 .init_uarts = exynos4_init_uarts,
60 .init = exynos_init,
61 .name = name_exynos4210,
62 }, {
63 .idcode = EXYNOS4212_CPU_ID,
64 .idmask = EXYNOS4_CPU_MASK,
65 .map_io = exynos4_map_io,
66 .init_clocks = exynos4_init_clocks,
67 .init_uarts = exynos4_init_uarts,
68 .init = exynos_init,
69 .name = name_exynos4212,
70 }, {
71 .idcode = EXYNOS4412_CPU_ID,
72 .idmask = EXYNOS4_CPU_MASK,
73 .map_io = exynos4_map_io,
74 .init_clocks = exynos4_init_clocks,
75 .init_uarts = exynos4_init_uarts,
76 .init = exynos_init,
77 .name = name_exynos4412,
78 },
79 };
80
81 /* Initial IO mappings */
82
83 static struct map_desc exynos_iodesc[] __initdata = {
84 {
85 .virtual = (unsigned long)S5P_VA_CHIPID,
86 .pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID),
87 .length = SZ_4K,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = (unsigned long)S3C_VA_SYS,
91 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
92 .length = SZ_64K,
93 .type = MT_DEVICE,
94 }, {
95 .virtual = (unsigned long)S3C_VA_TIMER,
96 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
97 .length = SZ_16K,
98 .type = MT_DEVICE,
99 }, {
100 .virtual = (unsigned long)S3C_VA_WATCHDOG,
101 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
102 .length = SZ_4K,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = (unsigned long)S5P_VA_SROMC,
106 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
107 .length = SZ_4K,
108 .type = MT_DEVICE,
109 }, {
110 .virtual = (unsigned long)S5P_VA_SYSTIMER,
111 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
112 .length = SZ_4K,
113 .type = MT_DEVICE,
114 }, {
115 .virtual = (unsigned long)S5P_VA_PMU,
116 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
117 .length = SZ_64K,
118 .type = MT_DEVICE,
119 }, {
120 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
121 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
122 .length = SZ_4K,
123 .type = MT_DEVICE,
124 }, {
125 .virtual = (unsigned long)S5P_VA_GIC_CPU,
126 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
127 .length = SZ_64K,
128 .type = MT_DEVICE,
129 }, {
130 .virtual = (unsigned long)S5P_VA_GIC_DIST,
131 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
132 .length = SZ_64K,
133 .type = MT_DEVICE,
134 }, {
135 .virtual = (unsigned long)S3C_VA_UART,
136 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
137 .length = SZ_512K,
138 .type = MT_DEVICE,
139 },
140 };
141
142 static struct map_desc exynos4_iodesc[] __initdata = {
143 {
144 .virtual = (unsigned long)S5P_VA_CMU,
145 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
146 .length = SZ_128K,
147 .type = MT_DEVICE,
148 }, {
149 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
150 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
151 .length = SZ_8K,
152 .type = MT_DEVICE,
153 }, {
154 .virtual = (unsigned long)S5P_VA_L2CC,
155 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
156 .length = SZ_4K,
157 .type = MT_DEVICE,
158 }, {
159 .virtual = (unsigned long)S5P_VA_DMC0,
160 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
161 .length = SZ_4K,
162 .type = MT_DEVICE,
163 }, {
164 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
165 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
166 .length = SZ_4K,
167 .type = MT_DEVICE,
168 },
169 };
170
171 static struct map_desc exynos4_iodesc0[] __initdata = {
172 {
173 .virtual = (unsigned long)S5P_VA_SYSRAM,
174 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
175 .length = SZ_4K,
176 .type = MT_DEVICE,
177 },
178 };
179
180 static struct map_desc exynos4_iodesc1[] __initdata = {
181 {
182 .virtual = (unsigned long)S5P_VA_SYSRAM,
183 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
184 .length = SZ_4K,
185 .type = MT_DEVICE,
186 },
187 };
188
189 void exynos4_restart(char mode, const char *cmd)
190 {
191 __raw_writel(0x1, S5P_SWRESET);
192 }
193
194 /*
195 * exynos_map_io
196 *
197 * register the standard cpu IO areas
198 */
199
200 void __init exynos_init_io(struct map_desc *mach_desc, int size)
201 {
202 /* initialize the io descriptors we need for initialization */
203 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
204 if (mach_desc)
205 iotable_init(mach_desc, size);
206
207 /* detect cpu id and rev. */
208 s5p_init_cpu(S5P_VA_CHIPID);
209
210 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
211 }
212
213 void __init exynos4_map_io(void)
214 {
215 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
216
217 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
218 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
219 else
220 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
221
222 /* initialize device information early */
223 exynos4_default_sdhci0();
224 exynos4_default_sdhci1();
225 exynos4_default_sdhci2();
226 exynos4_default_sdhci3();
227
228 s3c_adc_setname("samsung-adc-v3");
229
230 s3c_fimc_setname(0, "exynos4-fimc");
231 s3c_fimc_setname(1, "exynos4-fimc");
232 s3c_fimc_setname(2, "exynos4-fimc");
233 s3c_fimc_setname(3, "exynos4-fimc");
234
235 /* The I2C bus controllers are directly compatible with s3c2440 */
236 s3c_i2c0_setname("s3c2440-i2c");
237 s3c_i2c1_setname("s3c2440-i2c");
238 s3c_i2c2_setname("s3c2440-i2c");
239
240 s5p_fb_setname(0, "exynos4-fb");
241 s5p_hdmi_setname("exynos4-hdmi");
242 }
243
244 void __init exynos4_init_clocks(int xtal)
245 {
246 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
247
248 s3c24xx_register_baseclocks(xtal);
249 s5p_register_clocks(xtal);
250
251 if (soc_is_exynos4210())
252 exynos4210_register_clocks();
253 else if (soc_is_exynos4212() || soc_is_exynos4412())
254 exynos4212_register_clocks();
255
256 exynos4_register_clocks();
257 exynos4_setup_clocks();
258 }
259
260 #define COMBINER_ENABLE_SET 0x0
261 #define COMBINER_ENABLE_CLEAR 0x4
262 #define COMBINER_INT_STATUS 0xC
263
264 static DEFINE_SPINLOCK(irq_controller_lock);
265
266 struct combiner_chip_data {
267 unsigned int irq_offset;
268 unsigned int irq_mask;
269 void __iomem *base;
270 };
271
272 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
273
274 static inline void __iomem *combiner_base(struct irq_data *data)
275 {
276 struct combiner_chip_data *combiner_data =
277 irq_data_get_irq_chip_data(data);
278
279 return combiner_data->base;
280 }
281
282 static void combiner_mask_irq(struct irq_data *data)
283 {
284 u32 mask = 1 << (data->irq % 32);
285
286 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
287 }
288
289 static void combiner_unmask_irq(struct irq_data *data)
290 {
291 u32 mask = 1 << (data->irq % 32);
292
293 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
294 }
295
296 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
297 {
298 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
299 struct irq_chip *chip = irq_get_chip(irq);
300 unsigned int cascade_irq, combiner_irq;
301 unsigned long status;
302
303 chained_irq_enter(chip, desc);
304
305 spin_lock(&irq_controller_lock);
306 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
307 spin_unlock(&irq_controller_lock);
308 status &= chip_data->irq_mask;
309
310 if (status == 0)
311 goto out;
312
313 combiner_irq = __ffs(status);
314
315 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
316 if (unlikely(cascade_irq >= NR_IRQS))
317 do_bad_IRQ(cascade_irq, desc);
318 else
319 generic_handle_irq(cascade_irq);
320
321 out:
322 chained_irq_exit(chip, desc);
323 }
324
325 static struct irq_chip combiner_chip = {
326 .name = "COMBINER",
327 .irq_mask = combiner_mask_irq,
328 .irq_unmask = combiner_unmask_irq,
329 };
330
331 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
332 {
333 if (combiner_nr >= MAX_COMBINER_NR)
334 BUG();
335 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
336 BUG();
337 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
338 }
339
340 static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
341 unsigned int irq_start)
342 {
343 unsigned int i;
344
345 if (combiner_nr >= MAX_COMBINER_NR)
346 BUG();
347
348 combiner_data[combiner_nr].base = base;
349 combiner_data[combiner_nr].irq_offset = irq_start;
350 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
351
352 /* Disable all interrupts */
353
354 __raw_writel(combiner_data[combiner_nr].irq_mask,
355 base + COMBINER_ENABLE_CLEAR);
356
357 /* Setup the Linux IRQ subsystem */
358
359 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
360 + MAX_IRQ_IN_COMBINER; i++) {
361 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
362 irq_set_chip_data(i, &combiner_data[combiner_nr]);
363 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
364 }
365 }
366
367 #ifdef CONFIG_OF
368 static const struct of_device_id exynos4_dt_irq_match[] = {
369 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
370 {},
371 };
372 #endif
373
374 void __init exynos4_init_irq(void)
375 {
376 int irq;
377 unsigned int gic_bank_offset;
378
379 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
380
381 if (!of_have_populated_dt())
382 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
383 #ifdef CONFIG_OF
384 else
385 of_irq_init(exynos4_dt_irq_match);
386 #endif
387
388 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
389
390 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
391 COMBINER_IRQ(irq, 0));
392 combiner_cascade_irq(irq, IRQ_SPI(irq));
393 }
394
395 /*
396 * The parameters of s5p_init_irq() are for VIC init.
397 * Theses parameters should be NULL and 0 because EXYNOS4
398 * uses GIC instead of VIC.
399 */
400 s5p_init_irq(NULL, 0);
401 }
402
403 struct bus_type exynos4_subsys = {
404 .name = "exynos4-core",
405 .dev_name = "exynos4-core",
406 };
407
408 static struct device exynos4_dev = {
409 .bus = &exynos4_subsys,
410 };
411
412 static int __init exynos4_core_init(void)
413 {
414 return subsys_system_register(&exynos4_subsys, NULL);
415 }
416 core_initcall(exynos4_core_init);
417
418 #ifdef CONFIG_CACHE_L2X0
419 static int __init exynos4_l2x0_cache_init(void)
420 {
421 /* TAG, Data Latency Control: 2cycle */
422 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
423
424 if (soc_is_exynos4210())
425 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
426 else if (soc_is_exynos4212() || soc_is_exynos4412())
427 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
428
429 /* L2X0 Prefetch Control */
430 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
431
432 /* L2X0 Power Control */
433 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
434 S5P_VA_L2CC + L2X0_POWER_CTRL);
435
436 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
437
438 return 0;
439 }
440
441 early_initcall(exynos4_l2x0_cache_init);
442 #endif
443
444 int __init exynos_init(void)
445 {
446 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
447 return device_register(&exynos4_dev);
448 }
449
450 /* uart registration process */
451
452 void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
453 {
454 struct s3c2410_uartcfg *tcfg = cfg;
455 u32 ucnt;
456
457 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
458 tcfg->has_fracval = 1;
459
460 s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
461 }
462
463 static DEFINE_SPINLOCK(eint_lock);
464
465 static unsigned int eint0_15_data[16];
466
467 static unsigned int exynos4_get_irq_nr(unsigned int number)
468 {
469 u32 ret = 0;
470
471 switch (number) {
472 case 0 ... 3:
473 ret = (number + IRQ_EINT0);
474 break;
475 case 4 ... 7:
476 ret = (number + (IRQ_EINT4 - 4));
477 break;
478 case 8 ... 15:
479 ret = (number + (IRQ_EINT8 - 8));
480 break;
481 default:
482 printk(KERN_ERR "number available : %d\n", number);
483 }
484
485 return ret;
486 }
487
488 static inline void exynos4_irq_eint_mask(struct irq_data *data)
489 {
490 u32 mask;
491
492 spin_lock(&eint_lock);
493 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
494 mask |= eint_irq_to_bit(data->irq);
495 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
496 spin_unlock(&eint_lock);
497 }
498
499 static void exynos4_irq_eint_unmask(struct irq_data *data)
500 {
501 u32 mask;
502
503 spin_lock(&eint_lock);
504 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
505 mask &= ~(eint_irq_to_bit(data->irq));
506 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
507 spin_unlock(&eint_lock);
508 }
509
510 static inline void exynos4_irq_eint_ack(struct irq_data *data)
511 {
512 __raw_writel(eint_irq_to_bit(data->irq),
513 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
514 }
515
516 static void exynos4_irq_eint_maskack(struct irq_data *data)
517 {
518 exynos4_irq_eint_mask(data);
519 exynos4_irq_eint_ack(data);
520 }
521
522 static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
523 {
524 int offs = EINT_OFFSET(data->irq);
525 int shift;
526 u32 ctrl, mask;
527 u32 newvalue = 0;
528
529 switch (type) {
530 case IRQ_TYPE_EDGE_RISING:
531 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
532 break;
533
534 case IRQ_TYPE_EDGE_FALLING:
535 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
536 break;
537
538 case IRQ_TYPE_EDGE_BOTH:
539 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
540 break;
541
542 case IRQ_TYPE_LEVEL_LOW:
543 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
544 break;
545
546 case IRQ_TYPE_LEVEL_HIGH:
547 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
548 break;
549
550 default:
551 printk(KERN_ERR "No such irq type %d", type);
552 return -EINVAL;
553 }
554
555 shift = (offs & 0x7) * 4;
556 mask = 0x7 << shift;
557
558 spin_lock(&eint_lock);
559 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
560 ctrl &= ~mask;
561 ctrl |= newvalue << shift;
562 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
563 spin_unlock(&eint_lock);
564
565 switch (offs) {
566 case 0 ... 7:
567 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
568 break;
569 case 8 ... 15:
570 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
571 break;
572 case 16 ... 23:
573 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
574 break;
575 case 24 ... 31:
576 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
577 break;
578 default:
579 printk(KERN_ERR "No such irq number %d", offs);
580 }
581
582 return 0;
583 }
584
585 static struct irq_chip exynos4_irq_eint = {
586 .name = "exynos4-eint",
587 .irq_mask = exynos4_irq_eint_mask,
588 .irq_unmask = exynos4_irq_eint_unmask,
589 .irq_mask_ack = exynos4_irq_eint_maskack,
590 .irq_ack = exynos4_irq_eint_ack,
591 .irq_set_type = exynos4_irq_eint_set_type,
592 #ifdef CONFIG_PM
593 .irq_set_wake = s3c_irqext_wake,
594 #endif
595 };
596
597 /*
598 * exynos4_irq_demux_eint
599 *
600 * This function demuxes the IRQ from from EINTs 16 to 31.
601 * It is designed to be inlined into the specific handler
602 * s5p_irq_demux_eintX_Y.
603 *
604 * Each EINT pend/mask registers handle eight of them.
605 */
606 static inline void exynos4_irq_demux_eint(unsigned int start)
607 {
608 unsigned int irq;
609
610 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
611 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
612
613 status &= ~mask;
614 status &= 0xff;
615
616 while (status) {
617 irq = fls(status) - 1;
618 generic_handle_irq(irq + start);
619 status &= ~(1 << irq);
620 }
621 }
622
623 static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
624 {
625 struct irq_chip *chip = irq_get_chip(irq);
626 chained_irq_enter(chip, desc);
627 exynos4_irq_demux_eint(IRQ_EINT(16));
628 exynos4_irq_demux_eint(IRQ_EINT(24));
629 chained_irq_exit(chip, desc);
630 }
631
632 static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
633 {
634 u32 *irq_data = irq_get_handler_data(irq);
635 struct irq_chip *chip = irq_get_chip(irq);
636
637 chained_irq_enter(chip, desc);
638 chip->irq_mask(&desc->irq_data);
639
640 if (chip->irq_ack)
641 chip->irq_ack(&desc->irq_data);
642
643 generic_handle_irq(*irq_data);
644
645 chip->irq_unmask(&desc->irq_data);
646 chained_irq_exit(chip, desc);
647 }
648
649 static int __init exynos4_init_irq_eint(void)
650 {
651 int irq;
652
653 for (irq = 0 ; irq <= 31 ; irq++) {
654 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
655 handle_level_irq);
656 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
657 }
658
659 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
660
661 for (irq = 0 ; irq <= 15 ; irq++) {
662 eint0_15_data[irq] = IRQ_EINT(irq);
663
664 irq_set_handler_data(exynos4_get_irq_nr(irq),
665 &eint0_15_data[irq]);
666 irq_set_chained_handler(exynos4_get_irq_nr(irq),
667 exynos4_irq_eint0_15);
668 }
669
670 return 0;
671 }
672 arch_initcall(exynos4_init_irq_eint);
Linux kernel - Deliverables
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