2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Common Codes for EXYNOS
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
16 #include <linux/device.h>
17 #include <linux/gpio.h>
18 #include <linux/sched.h>
19 #include <linux/serial_core.h>
21 #include <linux/of_fdt.h>
22 #include <linux/of_irq.h>
23 #include <linux/export.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_address.h>
27 #include <asm/proc-fns.h>
28 #include <asm/exception.h>
29 #include <asm/hardware/cache-l2x0.h>
30 #include <asm/hardware/gic.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/irq.h>
33 #include <asm/cacheflush.h>
35 #include <mach/regs-irq.h>
36 #include <mach/regs-pmu.h>
37 #include <mach/regs-gpio.h>
41 #include <plat/clock.h>
42 #include <plat/devs.h>
44 #include <plat/sdhci.h>
45 #include <plat/gpio-cfg.h>
46 #include <plat/adc-core.h>
47 #include <plat/fb-core.h>
48 #include <plat/fimc-core.h>
49 #include <plat/iic-core.h>
50 #include <plat/tv-core.h>
51 #include <plat/spi-core.h>
52 #include <plat/regs-serial.h>
55 #define L2_AUX_VAL 0x7C470001
56 #define L2_AUX_MASK 0xC200ffff
58 static const char name_exynos4210
[] = "EXYNOS4210";
59 static const char name_exynos4212
[] = "EXYNOS4212";
60 static const char name_exynos4412
[] = "EXYNOS4412";
61 static const char name_exynos5250
[] = "EXYNOS5250";
62 static const char name_exynos5440
[] = "EXYNOS5440";
64 static void exynos4_map_io(void);
65 static void exynos5_map_io(void);
66 static void exynos5440_map_io(void);
67 static void exynos4_init_clocks(int xtal
);
68 static void exynos5_init_clocks(int xtal
);
69 static void exynos4_init_uarts(struct s3c2410_uartcfg
*cfg
, int no
);
70 static int exynos_init(void);
72 static struct cpu_table cpu_ids
[] __initdata
= {
74 .idcode
= EXYNOS4210_CPU_ID
,
75 .idmask
= EXYNOS4_CPU_MASK
,
76 .map_io
= exynos4_map_io
,
77 .init_clocks
= exynos4_init_clocks
,
78 .init_uarts
= exynos4_init_uarts
,
80 .name
= name_exynos4210
,
82 .idcode
= EXYNOS4212_CPU_ID
,
83 .idmask
= EXYNOS4_CPU_MASK
,
84 .map_io
= exynos4_map_io
,
85 .init_clocks
= exynos4_init_clocks
,
86 .init_uarts
= exynos4_init_uarts
,
88 .name
= name_exynos4212
,
90 .idcode
= EXYNOS4412_CPU_ID
,
91 .idmask
= EXYNOS4_CPU_MASK
,
92 .map_io
= exynos4_map_io
,
93 .init_clocks
= exynos4_init_clocks
,
94 .init_uarts
= exynos4_init_uarts
,
96 .name
= name_exynos4412
,
98 .idcode
= EXYNOS5250_SOC_ID
,
99 .idmask
= EXYNOS5_SOC_MASK
,
100 .map_io
= exynos5_map_io
,
101 .init_clocks
= exynos5_init_clocks
,
103 .name
= name_exynos5250
,
105 .idcode
= EXYNOS5440_SOC_ID
,
106 .idmask
= EXYNOS5_SOC_MASK
,
107 .map_io
= exynos5440_map_io
,
109 .name
= name_exynos5440
,
113 /* Initial IO mappings */
115 static struct map_desc exynos_iodesc
[] __initdata
= {
117 .virtual = (unsigned long)S5P_VA_CHIPID
,
118 .pfn
= __phys_to_pfn(EXYNOS_PA_CHIPID
),
124 #ifdef CONFIG_ARCH_EXYNOS5
125 static struct map_desc exynos5440_iodesc
[] __initdata
= {
127 .virtual = (unsigned long)S5P_VA_CHIPID
,
128 .pfn
= __phys_to_pfn(EXYNOS5440_PA_CHIPID
),
135 static struct map_desc exynos4_iodesc
[] __initdata
= {
137 .virtual = (unsigned long)S3C_VA_SYS
,
138 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSCON
),
142 .virtual = (unsigned long)S3C_VA_TIMER
,
143 .pfn
= __phys_to_pfn(EXYNOS4_PA_TIMER
),
147 .virtual = (unsigned long)S3C_VA_WATCHDOG
,
148 .pfn
= __phys_to_pfn(EXYNOS4_PA_WATCHDOG
),
152 .virtual = (unsigned long)S5P_VA_SROMC
,
153 .pfn
= __phys_to_pfn(EXYNOS4_PA_SROMC
),
157 .virtual = (unsigned long)S5P_VA_SYSTIMER
,
158 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSTIMER
),
162 .virtual = (unsigned long)S5P_VA_PMU
,
163 .pfn
= __phys_to_pfn(EXYNOS4_PA_PMU
),
167 .virtual = (unsigned long)S5P_VA_COMBINER_BASE
,
168 .pfn
= __phys_to_pfn(EXYNOS4_PA_COMBINER
),
172 .virtual = (unsigned long)S5P_VA_GIC_CPU
,
173 .pfn
= __phys_to_pfn(EXYNOS4_PA_GIC_CPU
),
177 .virtual = (unsigned long)S5P_VA_GIC_DIST
,
178 .pfn
= __phys_to_pfn(EXYNOS4_PA_GIC_DIST
),
182 .virtual = (unsigned long)S3C_VA_UART
,
183 .pfn
= __phys_to_pfn(EXYNOS4_PA_UART
),
187 .virtual = (unsigned long)S5P_VA_CMU
,
188 .pfn
= __phys_to_pfn(EXYNOS4_PA_CMU
),
192 .virtual = (unsigned long)S5P_VA_COREPERI_BASE
,
193 .pfn
= __phys_to_pfn(EXYNOS4_PA_COREPERI
),
197 .virtual = (unsigned long)S5P_VA_L2CC
,
198 .pfn
= __phys_to_pfn(EXYNOS4_PA_L2CC
),
202 .virtual = (unsigned long)S5P_VA_DMC0
,
203 .pfn
= __phys_to_pfn(EXYNOS4_PA_DMC0
),
207 .virtual = (unsigned long)S5P_VA_DMC1
,
208 .pfn
= __phys_to_pfn(EXYNOS4_PA_DMC1
),
212 .virtual = (unsigned long)S3C_VA_USB_HSPHY
,
213 .pfn
= __phys_to_pfn(EXYNOS4_PA_HSPHY
),
219 static struct map_desc exynos4_iodesc0
[] __initdata
= {
221 .virtual = (unsigned long)S5P_VA_SYSRAM
,
222 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSRAM0
),
228 static struct map_desc exynos4_iodesc1
[] __initdata
= {
230 .virtual = (unsigned long)S5P_VA_SYSRAM
,
231 .pfn
= __phys_to_pfn(EXYNOS4_PA_SYSRAM1
),
237 static struct map_desc exynos5_iodesc
[] __initdata
= {
239 .virtual = (unsigned long)S3C_VA_SYS
,
240 .pfn
= __phys_to_pfn(EXYNOS5_PA_SYSCON
),
244 .virtual = (unsigned long)S3C_VA_TIMER
,
245 .pfn
= __phys_to_pfn(EXYNOS5_PA_TIMER
),
249 .virtual = (unsigned long)S3C_VA_WATCHDOG
,
250 .pfn
= __phys_to_pfn(EXYNOS5_PA_WATCHDOG
),
254 .virtual = (unsigned long)S5P_VA_SROMC
,
255 .pfn
= __phys_to_pfn(EXYNOS5_PA_SROMC
),
259 .virtual = (unsigned long)S5P_VA_SYSTIMER
,
260 .pfn
= __phys_to_pfn(EXYNOS5_PA_SYSTIMER
),
264 .virtual = (unsigned long)S5P_VA_SYSRAM
,
265 .pfn
= __phys_to_pfn(EXYNOS5_PA_SYSRAM
),
269 .virtual = (unsigned long)S5P_VA_CMU
,
270 .pfn
= __phys_to_pfn(EXYNOS5_PA_CMU
),
271 .length
= 144 * SZ_1K
,
274 .virtual = (unsigned long)S5P_VA_PMU
,
275 .pfn
= __phys_to_pfn(EXYNOS5_PA_PMU
),
279 .virtual = (unsigned long)S3C_VA_UART
,
280 .pfn
= __phys_to_pfn(EXYNOS5_PA_UART
),
286 static struct map_desc exynos5440_iodesc0
[] __initdata
= {
288 .virtual = (unsigned long)S3C_VA_UART
,
289 .pfn
= __phys_to_pfn(EXYNOS5440_PA_UART0
),
295 void exynos4_restart(char mode
, const char *cmd
)
297 __raw_writel(0x1, S5P_SWRESET
);
300 void exynos5_restart(char mode
, const char *cmd
)
305 if (of_machine_is_compatible("samsung,exynos5250")) {
307 addr
= EXYNOS_SWRESET
;
308 } else if (of_machine_is_compatible("samsung,exynos5440")) {
309 val
= (0x10 << 20) | (0x1 << 16);
310 addr
= EXYNOS5440_SWRESET
;
312 pr_err("%s: cannot support non-DT\n", __func__
);
316 __raw_writel(val
, addr
);
319 void __init
exynos_init_late(void)
321 if (of_machine_is_compatible("samsung,exynos5440"))
322 /* to be supported later */
325 exynos_pm_late_initcall();
331 * register the standard cpu IO areas
334 void __init
exynos_init_io(struct map_desc
*mach_desc
, int size
)
336 struct map_desc
*iodesc
= exynos_iodesc
;
337 int iodesc_sz
= ARRAY_SIZE(exynos_iodesc
);
338 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
339 unsigned long root
= of_get_flat_dt_root();
341 /* initialize the io descriptors we need for initialization */
342 if (of_flat_dt_is_compatible(root
, "samsung,exynos5440")) {
343 iodesc
= exynos5440_iodesc
;
344 iodesc_sz
= ARRAY_SIZE(exynos5440_iodesc
);
348 iotable_init(iodesc
, iodesc_sz
);
351 iotable_init(mach_desc
, size
);
353 /* detect cpu id and rev. */
354 s5p_init_cpu(S5P_VA_CHIPID
);
356 s3c_init_cpu(samsung_cpu_id
, cpu_ids
, ARRAY_SIZE(cpu_ids
));
359 static void __init
exynos4_map_io(void)
361 iotable_init(exynos4_iodesc
, ARRAY_SIZE(exynos4_iodesc
));
363 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0
)
364 iotable_init(exynos4_iodesc0
, ARRAY_SIZE(exynos4_iodesc0
));
366 iotable_init(exynos4_iodesc1
, ARRAY_SIZE(exynos4_iodesc1
));
368 /* initialize device information early */
369 exynos4_default_sdhci0();
370 exynos4_default_sdhci1();
371 exynos4_default_sdhci2();
372 exynos4_default_sdhci3();
374 s3c_adc_setname("samsung-adc-v3");
376 s3c_fimc_setname(0, "exynos4-fimc");
377 s3c_fimc_setname(1, "exynos4-fimc");
378 s3c_fimc_setname(2, "exynos4-fimc");
379 s3c_fimc_setname(3, "exynos4-fimc");
381 s3c_sdhci_setname(0, "exynos4-sdhci");
382 s3c_sdhci_setname(1, "exynos4-sdhci");
383 s3c_sdhci_setname(2, "exynos4-sdhci");
384 s3c_sdhci_setname(3, "exynos4-sdhci");
386 /* The I2C bus controllers are directly compatible with s3c2440 */
387 s3c_i2c0_setname("s3c2440-i2c");
388 s3c_i2c1_setname("s3c2440-i2c");
389 s3c_i2c2_setname("s3c2440-i2c");
391 s5p_fb_setname(0, "exynos4-fb");
392 s5p_hdmi_setname("exynos4-hdmi");
394 s3c64xx_spi_setname("exynos4210-spi");
397 static void __init
exynos5_map_io(void)
399 iotable_init(exynos5_iodesc
, ARRAY_SIZE(exynos5_iodesc
));
402 static void __init
exynos4_init_clocks(int xtal
)
404 printk(KERN_DEBUG
"%s: initializing clocks\n", __func__
);
406 s3c24xx_register_baseclocks(xtal
);
407 s5p_register_clocks(xtal
);
409 if (soc_is_exynos4210())
410 exynos4210_register_clocks();
411 else if (soc_is_exynos4212() || soc_is_exynos4412())
412 exynos4212_register_clocks();
414 exynos4_register_clocks();
415 exynos4_setup_clocks();
418 static void __init
exynos5440_map_io(void)
420 iotable_init(exynos5440_iodesc0
, ARRAY_SIZE(exynos5440_iodesc0
));
423 static void __init
exynos5_init_clocks(int xtal
)
425 printk(KERN_DEBUG
"%s: initializing clocks\n", __func__
);
427 s3c24xx_register_baseclocks(xtal
);
428 s5p_register_clocks(xtal
);
430 exynos5_register_clocks();
431 exynos5_setup_clocks();
434 #define COMBINER_ENABLE_SET 0x0
435 #define COMBINER_ENABLE_CLEAR 0x4
436 #define COMBINER_INT_STATUS 0xC
438 static DEFINE_SPINLOCK(irq_controller_lock
);
440 struct combiner_chip_data
{
441 unsigned int irq_offset
;
442 unsigned int irq_mask
;
446 static struct irq_domain
*combiner_irq_domain
;
447 static struct combiner_chip_data combiner_data
[MAX_COMBINER_NR
];
449 static inline void __iomem
*combiner_base(struct irq_data
*data
)
451 struct combiner_chip_data
*combiner_data
=
452 irq_data_get_irq_chip_data(data
);
454 return combiner_data
->base
;
457 static void combiner_mask_irq(struct irq_data
*data
)
459 u32 mask
= 1 << (data
->hwirq
% 32);
461 __raw_writel(mask
, combiner_base(data
) + COMBINER_ENABLE_CLEAR
);
464 static void combiner_unmask_irq(struct irq_data
*data
)
466 u32 mask
= 1 << (data
->hwirq
% 32);
468 __raw_writel(mask
, combiner_base(data
) + COMBINER_ENABLE_SET
);
471 static void combiner_handle_cascade_irq(unsigned int irq
, struct irq_desc
*desc
)
473 struct combiner_chip_data
*chip_data
= irq_get_handler_data(irq
);
474 struct irq_chip
*chip
= irq_get_chip(irq
);
475 unsigned int cascade_irq
, combiner_irq
;
476 unsigned long status
;
478 chained_irq_enter(chip
, desc
);
480 spin_lock(&irq_controller_lock
);
481 status
= __raw_readl(chip_data
->base
+ COMBINER_INT_STATUS
);
482 spin_unlock(&irq_controller_lock
);
483 status
&= chip_data
->irq_mask
;
488 combiner_irq
= __ffs(status
);
490 cascade_irq
= combiner_irq
+ (chip_data
->irq_offset
& ~31);
491 if (unlikely(cascade_irq
>= NR_IRQS
))
492 do_bad_IRQ(cascade_irq
, desc
);
494 generic_handle_irq(cascade_irq
);
497 chained_irq_exit(chip
, desc
);
500 static struct irq_chip combiner_chip
= {
502 .irq_mask
= combiner_mask_irq
,
503 .irq_unmask
= combiner_unmask_irq
,
506 static void __init
combiner_cascade_irq(unsigned int combiner_nr
, unsigned int irq
)
510 if (soc_is_exynos5250())
511 max_nr
= EXYNOS5_MAX_COMBINER_NR
;
513 max_nr
= EXYNOS4_MAX_COMBINER_NR
;
515 if (combiner_nr
>= max_nr
)
517 if (irq_set_handler_data(irq
, &combiner_data
[combiner_nr
]) != 0)
519 irq_set_chained_handler(irq
, combiner_handle_cascade_irq
);
522 static void __init
combiner_init_one(unsigned int combiner_nr
,
525 combiner_data
[combiner_nr
].base
= base
;
526 combiner_data
[combiner_nr
].irq_offset
= irq_find_mapping(
527 combiner_irq_domain
, combiner_nr
* MAX_IRQ_IN_COMBINER
);
528 combiner_data
[combiner_nr
].irq_mask
= 0xff << ((combiner_nr
% 4) << 3);
530 /* Disable all interrupts */
531 __raw_writel(combiner_data
[combiner_nr
].irq_mask
,
532 base
+ COMBINER_ENABLE_CLEAR
);
536 static int combiner_irq_domain_xlate(struct irq_domain
*d
,
537 struct device_node
*controller
,
538 const u32
*intspec
, unsigned int intsize
,
539 unsigned long *out_hwirq
,
540 unsigned int *out_type
)
542 if (d
->of_node
!= controller
)
548 *out_hwirq
= intspec
[0] * MAX_IRQ_IN_COMBINER
+ intspec
[1];
554 static int combiner_irq_domain_xlate(struct irq_domain
*d
,
555 struct device_node
*controller
,
556 const u32
*intspec
, unsigned int intsize
,
557 unsigned long *out_hwirq
,
558 unsigned int *out_type
)
564 static int combiner_irq_domain_map(struct irq_domain
*d
, unsigned int irq
,
567 irq_set_chip_and_handler(irq
, &combiner_chip
, handle_level_irq
);
568 irq_set_chip_data(irq
, &combiner_data
[hw
>> 3]);
569 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
574 static struct irq_domain_ops combiner_irq_domain_ops
= {
575 .xlate
= combiner_irq_domain_xlate
,
576 .map
= combiner_irq_domain_map
,
579 static void __init
combiner_init(void __iomem
*combiner_base
,
580 struct device_node
*np
)
582 int i
, irq
, irq_base
;
583 unsigned int max_nr
, nr_irq
;
586 if (of_property_read_u32(np
, "samsung,combiner-nr", &max_nr
)) {
587 pr_warning("%s: number of combiners not specified, "
588 "setting default as %d.\n",
589 __func__
, EXYNOS4_MAX_COMBINER_NR
);
590 max_nr
= EXYNOS4_MAX_COMBINER_NR
;
593 max_nr
= soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR
:
594 EXYNOS4_MAX_COMBINER_NR
;
596 nr_irq
= max_nr
* MAX_IRQ_IN_COMBINER
;
598 irq_base
= irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq
, 0);
599 if (IS_ERR_VALUE(irq_base
)) {
600 irq_base
= COMBINER_IRQ(0, 0);
601 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__
, irq_base
);
604 combiner_irq_domain
= irq_domain_add_legacy(np
, nr_irq
, irq_base
, 0,
605 &combiner_irq_domain_ops
, &combiner_data
);
606 if (WARN_ON(!combiner_irq_domain
)) {
607 pr_warning("%s: irq domain init failed\n", __func__
);
611 for (i
= 0; i
< max_nr
; i
++) {
612 combiner_init_one(i
, combiner_base
+ (i
>> 2) * 0x10);
616 irq
= irq_of_parse_and_map(np
, i
);
618 combiner_cascade_irq(i
, irq
);
623 static int __init
combiner_of_init(struct device_node
*np
,
624 struct device_node
*parent
)
626 void __iomem
*combiner_base
;
628 combiner_base
= of_iomap(np
, 0);
629 if (!combiner_base
) {
630 pr_err("%s: failed to map combiner registers\n", __func__
);
634 combiner_init(combiner_base
, np
);
639 static const struct of_device_id exynos_dt_irq_match
[] = {
640 { .compatible
= "arm,cortex-a9-gic", .data
= gic_of_init
, },
641 { .compatible
= "arm,cortex-a15-gic", .data
= gic_of_init
, },
642 { .compatible
= "samsung,exynos4210-combiner",
643 .data
= combiner_of_init
, },
648 void __init
exynos4_init_irq(void)
650 unsigned int gic_bank_offset
;
652 gic_bank_offset
= soc_is_exynos4412() ? 0x4000 : 0x8000;
654 if (!of_have_populated_dt())
655 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST
, S5P_VA_GIC_CPU
, gic_bank_offset
, NULL
);
658 of_irq_init(exynos_dt_irq_match
);
661 if (!of_have_populated_dt())
662 combiner_init(S5P_VA_COMBINER_BASE
, NULL
);
665 * The parameters of s5p_init_irq() are for VIC init.
666 * Theses parameters should be NULL and 0 because EXYNOS4
667 * uses GIC instead of VIC.
669 s5p_init_irq(NULL
, 0);
672 void __init
exynos5_init_irq(void)
675 of_irq_init(exynos_dt_irq_match
);
678 * The parameters of s5p_init_irq() are for VIC init.
679 * Theses parameters should be NULL and 0 because EXYNOS4
680 * uses GIC instead of VIC.
682 if (!of_machine_is_compatible("samsung,exynos5440"))
683 s5p_init_irq(NULL
, 0);
685 gic_arch_extn
.irq_set_wake
= s3c_irq_wake
;
688 struct bus_type exynos_subsys
= {
689 .name
= "exynos-core",
690 .dev_name
= "exynos-core",
693 static struct device exynos4_dev
= {
694 .bus
= &exynos_subsys
,
697 static int __init
exynos_core_init(void)
699 return subsys_system_register(&exynos_subsys
, NULL
);
701 core_initcall(exynos_core_init
);
703 #ifdef CONFIG_CACHE_L2X0
704 static int __init
exynos4_l2x0_cache_init(void)
708 if (soc_is_exynos5250() || soc_is_exynos5440())
711 ret
= l2x0_of_init(L2_AUX_VAL
, L2_AUX_MASK
);
713 l2x0_regs_phys
= virt_to_phys(&l2x0_saved_regs
);
714 clean_dcache_area(&l2x0_regs_phys
, sizeof(unsigned long));
718 if (!(__raw_readl(S5P_VA_L2CC
+ L2X0_CTRL
) & 0x1)) {
719 l2x0_saved_regs
.phy_base
= EXYNOS4_PA_L2CC
;
720 /* TAG, Data Latency Control: 2 cycles */
721 l2x0_saved_regs
.tag_latency
= 0x110;
723 if (soc_is_exynos4212() || soc_is_exynos4412())
724 l2x0_saved_regs
.data_latency
= 0x120;
726 l2x0_saved_regs
.data_latency
= 0x110;
728 l2x0_saved_regs
.prefetch_ctrl
= 0x30000007;
729 l2x0_saved_regs
.pwr_ctrl
=
730 (L2X0_DYNAMIC_CLK_GATING_EN
| L2X0_STNDBY_MODE_EN
);
732 l2x0_regs_phys
= virt_to_phys(&l2x0_saved_regs
);
734 __raw_writel(l2x0_saved_regs
.tag_latency
,
735 S5P_VA_L2CC
+ L2X0_TAG_LATENCY_CTRL
);
736 __raw_writel(l2x0_saved_regs
.data_latency
,
737 S5P_VA_L2CC
+ L2X0_DATA_LATENCY_CTRL
);
739 /* L2X0 Prefetch Control */
740 __raw_writel(l2x0_saved_regs
.prefetch_ctrl
,
741 S5P_VA_L2CC
+ L2X0_PREFETCH_CTRL
);
743 /* L2X0 Power Control */
744 __raw_writel(l2x0_saved_regs
.pwr_ctrl
,
745 S5P_VA_L2CC
+ L2X0_POWER_CTRL
);
747 clean_dcache_area(&l2x0_regs_phys
, sizeof(unsigned long));
748 clean_dcache_area(&l2x0_saved_regs
, sizeof(struct l2x0_regs
));
751 l2x0_init(S5P_VA_L2CC
, L2_AUX_VAL
, L2_AUX_MASK
);
754 early_initcall(exynos4_l2x0_cache_init
);
757 static int __init
exynos_init(void)
759 printk(KERN_INFO
"EXYNOS: Initializing architecture\n");
761 return device_register(&exynos4_dev
);
764 /* uart registration process */
766 static void __init
exynos4_init_uarts(struct s3c2410_uartcfg
*cfg
, int no
)
768 struct s3c2410_uartcfg
*tcfg
= cfg
;
771 for (ucnt
= 0; ucnt
< no
; ucnt
++, tcfg
++)
772 tcfg
->has_fracval
= 1;
774 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources
, cfg
, no
);
777 static void __iomem
*exynos_eint_base
;
779 static DEFINE_SPINLOCK(eint_lock
);
781 static unsigned int eint0_15_data
[16];
783 static inline int exynos4_irq_to_gpio(unsigned int irq
)
785 if (irq
< IRQ_EINT(0))
790 return EXYNOS4_GPX0(irq
);
794 return EXYNOS4_GPX1(irq
);
798 return EXYNOS4_GPX2(irq
);
802 return EXYNOS4_GPX3(irq
);
807 static inline int exynos5_irq_to_gpio(unsigned int irq
)
809 if (irq
< IRQ_EINT(0))
814 return EXYNOS5_GPX0(irq
);
818 return EXYNOS5_GPX1(irq
);
822 return EXYNOS5_GPX2(irq
);
826 return EXYNOS5_GPX3(irq
);
831 static unsigned int exynos4_eint0_15_src_int
[16] = {
850 static unsigned int exynos5_eint0_15_src_int
[16] = {
868 static inline void exynos_irq_eint_mask(struct irq_data
*data
)
872 spin_lock(&eint_lock
);
873 mask
= __raw_readl(EINT_MASK(exynos_eint_base
, data
->irq
));
874 mask
|= EINT_OFFSET_BIT(data
->irq
);
875 __raw_writel(mask
, EINT_MASK(exynos_eint_base
, data
->irq
));
876 spin_unlock(&eint_lock
);
879 static void exynos_irq_eint_unmask(struct irq_data
*data
)
883 spin_lock(&eint_lock
);
884 mask
= __raw_readl(EINT_MASK(exynos_eint_base
, data
->irq
));
885 mask
&= ~(EINT_OFFSET_BIT(data
->irq
));
886 __raw_writel(mask
, EINT_MASK(exynos_eint_base
, data
->irq
));
887 spin_unlock(&eint_lock
);
890 static inline void exynos_irq_eint_ack(struct irq_data
*data
)
892 __raw_writel(EINT_OFFSET_BIT(data
->irq
),
893 EINT_PEND(exynos_eint_base
, data
->irq
));
896 static void exynos_irq_eint_maskack(struct irq_data
*data
)
898 exynos_irq_eint_mask(data
);
899 exynos_irq_eint_ack(data
);
902 static int exynos_irq_eint_set_type(struct irq_data
*data
, unsigned int type
)
904 int offs
= EINT_OFFSET(data
->irq
);
910 case IRQ_TYPE_EDGE_RISING
:
911 newvalue
= S5P_IRQ_TYPE_EDGE_RISING
;
914 case IRQ_TYPE_EDGE_FALLING
:
915 newvalue
= S5P_IRQ_TYPE_EDGE_FALLING
;
918 case IRQ_TYPE_EDGE_BOTH
:
919 newvalue
= S5P_IRQ_TYPE_EDGE_BOTH
;
922 case IRQ_TYPE_LEVEL_LOW
:
923 newvalue
= S5P_IRQ_TYPE_LEVEL_LOW
;
926 case IRQ_TYPE_LEVEL_HIGH
:
927 newvalue
= S5P_IRQ_TYPE_LEVEL_HIGH
;
931 printk(KERN_ERR
"No such irq type %d", type
);
935 shift
= (offs
& 0x7) * 4;
938 spin_lock(&eint_lock
);
939 ctrl
= __raw_readl(EINT_CON(exynos_eint_base
, data
->irq
));
941 ctrl
|= newvalue
<< shift
;
942 __raw_writel(ctrl
, EINT_CON(exynos_eint_base
, data
->irq
));
943 spin_unlock(&eint_lock
);
945 if (soc_is_exynos5250())
946 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data
->irq
), S3C_GPIO_SFN(0xf));
948 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data
->irq
), S3C_GPIO_SFN(0xf));
953 static struct irq_chip exynos_irq_eint
= {
954 .name
= "exynos-eint",
955 .irq_mask
= exynos_irq_eint_mask
,
956 .irq_unmask
= exynos_irq_eint_unmask
,
957 .irq_mask_ack
= exynos_irq_eint_maskack
,
958 .irq_ack
= exynos_irq_eint_ack
,
959 .irq_set_type
= exynos_irq_eint_set_type
,
961 .irq_set_wake
= s3c_irqext_wake
,
966 * exynos4_irq_demux_eint
968 * This function demuxes the IRQ from from EINTs 16 to 31.
969 * It is designed to be inlined into the specific handler
970 * s5p_irq_demux_eintX_Y.
972 * Each EINT pend/mask registers handle eight of them.
974 static inline void exynos_irq_demux_eint(unsigned int start
)
978 u32 status
= __raw_readl(EINT_PEND(exynos_eint_base
, start
));
979 u32 mask
= __raw_readl(EINT_MASK(exynos_eint_base
, start
));
985 irq
= fls(status
) - 1;
986 generic_handle_irq(irq
+ start
);
987 status
&= ~(1 << irq
);
991 static void exynos_irq_demux_eint16_31(unsigned int irq
, struct irq_desc
*desc
)
993 struct irq_chip
*chip
= irq_get_chip(irq
);
994 chained_irq_enter(chip
, desc
);
995 exynos_irq_demux_eint(IRQ_EINT(16));
996 exynos_irq_demux_eint(IRQ_EINT(24));
997 chained_irq_exit(chip
, desc
);
1000 static void exynos_irq_eint0_15(unsigned int irq
, struct irq_desc
*desc
)
1002 u32
*irq_data
= irq_get_handler_data(irq
);
1003 struct irq_chip
*chip
= irq_get_chip(irq
);
1005 chained_irq_enter(chip
, desc
);
1006 generic_handle_irq(*irq_data
);
1007 chained_irq_exit(chip
, desc
);
1010 static int __init
exynos_init_irq_eint(void)
1014 #ifdef CONFIG_PINCTRL_SAMSUNG
1016 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
1017 * functionality along with support for external gpio and wakeup
1018 * interrupts. If the samsung pinctrl driver is enabled and includes
1019 * the wakeup interrupt support, then the setting up external wakeup
1020 * interrupts here can be skipped. This check here is temporary to
1021 * allow exynos4 platforms that do not use Samsung pinctrl driver to
1022 * co-exist with platforms that do. When all of the Samsung Exynos4
1023 * platforms switch over to using the pinctrl driver, the wakeup
1024 * interrupt support code here can be completely removed.
1026 static const struct of_device_id exynos_pinctrl_ids
[] = {
1027 { .compatible
= "samsung,pinctrl-exynos4210", },
1028 { .compatible
= "samsung,pinctrl-exynos4x12", },
1030 struct device_node
*pctrl_np
, *wkup_np
;
1031 const char *wkup_compat
= "samsung,exynos4210-wakeup-eint";
1033 for_each_matching_node(pctrl_np
, exynos_pinctrl_ids
) {
1034 if (of_device_is_available(pctrl_np
)) {
1035 wkup_np
= of_find_compatible_node(pctrl_np
, NULL
,
1042 if (soc_is_exynos5440())
1045 if (soc_is_exynos5250())
1046 exynos_eint_base
= ioremap(EXYNOS5_PA_GPIO1
, SZ_4K
);
1048 exynos_eint_base
= ioremap(EXYNOS4_PA_GPIO2
, SZ_4K
);
1050 if (exynos_eint_base
== NULL
) {
1051 pr_err("unable to ioremap for EINT base address\n");
1055 for (irq
= 0 ; irq
<= 31 ; irq
++) {
1056 irq_set_chip_and_handler(IRQ_EINT(irq
), &exynos_irq_eint
,
1058 set_irq_flags(IRQ_EINT(irq
), IRQF_VALID
);
1061 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31
, exynos_irq_demux_eint16_31
);
1063 for (irq
= 0 ; irq
<= 15 ; irq
++) {
1064 eint0_15_data
[irq
] = IRQ_EINT(irq
);
1066 if (soc_is_exynos5250()) {
1067 irq_set_handler_data(exynos5_eint0_15_src_int
[irq
],
1068 &eint0_15_data
[irq
]);
1069 irq_set_chained_handler(exynos5_eint0_15_src_int
[irq
],
1070 exynos_irq_eint0_15
);
1072 irq_set_handler_data(exynos4_eint0_15_src_int
[irq
],
1073 &eint0_15_data
[irq
]);
1074 irq_set_chained_handler(exynos4_eint0_15_src_int
[irq
],
1075 exynos_irq_eint0_15
);
1081 arch_initcall(exynos_init_irq_eint
);