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[deliverable/linux.git] / arch / arm / mach-exynos / common.c
1 /*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/irqchip.h>
16 #include <linux/io.h>
17 #include <linux/device.h>
18 #include <linux/gpio.h>
19 #include <linux/sched.h>
20 #include <linux/serial_core.h>
21 #include <linux/of.h>
22 #include <linux/of_fdt.h>
23 #include <linux/of_irq.h>
24 #include <linux/export.h>
25 #include <linux/irqdomain.h>
26 #include <linux/irqchip.h>
27 #include <linux/of_address.h>
28 #include <linux/irqchip/arm-gic.h>
29
30 #include <asm/proc-fns.h>
31 #include <asm/exception.h>
32 #include <asm/hardware/cache-l2x0.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/irq.h>
35 #include <asm/cacheflush.h>
36
37 #include <mach/regs-irq.h>
38 #include <mach/regs-pmu.h>
39 #include <mach/regs-gpio.h>
40
41 #include <plat/cpu.h>
42 #include <plat/clock.h>
43 #include <plat/devs.h>
44 #include <plat/pm.h>
45 #include <plat/sdhci.h>
46 #include <plat/gpio-cfg.h>
47 #include <plat/adc-core.h>
48 #include <plat/fb-core.h>
49 #include <plat/fimc-core.h>
50 #include <plat/iic-core.h>
51 #include <plat/tv-core.h>
52 #include <plat/spi-core.h>
53 #include <plat/regs-serial.h>
54
55 #include "common.h"
56 #define L2_AUX_VAL 0x7C470001
57 #define L2_AUX_MASK 0xC200ffff
58
59 static const char name_exynos4210[] = "EXYNOS4210";
60 static const char name_exynos4212[] = "EXYNOS4212";
61 static const char name_exynos4412[] = "EXYNOS4412";
62 static const char name_exynos5250[] = "EXYNOS5250";
63 static const char name_exynos5440[] = "EXYNOS5440";
64
65 static void exynos4_map_io(void);
66 static void exynos5_map_io(void);
67 static void exynos5440_map_io(void);
68 static void exynos4_init_clocks(int xtal);
69 static void exynos5_init_clocks(int xtal);
70 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
71 static int exynos_init(void);
72
73 static struct cpu_table cpu_ids[] __initdata = {
74 {
75 .idcode = EXYNOS4210_CPU_ID,
76 .idmask = EXYNOS4_CPU_MASK,
77 .map_io = exynos4_map_io,
78 .init_clocks = exynos4_init_clocks,
79 .init_uarts = exynos4_init_uarts,
80 .init = exynos_init,
81 .name = name_exynos4210,
82 }, {
83 .idcode = EXYNOS4212_CPU_ID,
84 .idmask = EXYNOS4_CPU_MASK,
85 .map_io = exynos4_map_io,
86 .init_clocks = exynos4_init_clocks,
87 .init_uarts = exynos4_init_uarts,
88 .init = exynos_init,
89 .name = name_exynos4212,
90 }, {
91 .idcode = EXYNOS4412_CPU_ID,
92 .idmask = EXYNOS4_CPU_MASK,
93 .map_io = exynos4_map_io,
94 .init_clocks = exynos4_init_clocks,
95 .init_uarts = exynos4_init_uarts,
96 .init = exynos_init,
97 .name = name_exynos4412,
98 }, {
99 .idcode = EXYNOS5250_SOC_ID,
100 .idmask = EXYNOS5_SOC_MASK,
101 .map_io = exynos5_map_io,
102 .init_clocks = exynos5_init_clocks,
103 .init = exynos_init,
104 .name = name_exynos5250,
105 }, {
106 .idcode = EXYNOS5440_SOC_ID,
107 .idmask = EXYNOS5_SOC_MASK,
108 .map_io = exynos5440_map_io,
109 .init = exynos_init,
110 .name = name_exynos5440,
111 },
112 };
113
114 /* Initial IO mappings */
115
116 static struct map_desc exynos_iodesc[] __initdata = {
117 {
118 .virtual = (unsigned long)S5P_VA_CHIPID,
119 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
120 .length = SZ_4K,
121 .type = MT_DEVICE,
122 },
123 };
124
125 #ifdef CONFIG_ARCH_EXYNOS5
126 static struct map_desc exynos5440_iodesc[] __initdata = {
127 {
128 .virtual = (unsigned long)S5P_VA_CHIPID,
129 .pfn = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
130 .length = SZ_4K,
131 .type = MT_DEVICE,
132 },
133 };
134 #endif
135
136 static struct map_desc exynos4_iodesc[] __initdata = {
137 {
138 .virtual = (unsigned long)S3C_VA_SYS,
139 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
140 .length = SZ_64K,
141 .type = MT_DEVICE,
142 }, {
143 .virtual = (unsigned long)S3C_VA_TIMER,
144 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
145 .length = SZ_16K,
146 .type = MT_DEVICE,
147 }, {
148 .virtual = (unsigned long)S3C_VA_WATCHDOG,
149 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
150 .length = SZ_4K,
151 .type = MT_DEVICE,
152 }, {
153 .virtual = (unsigned long)S5P_VA_SROMC,
154 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
155 .length = SZ_4K,
156 .type = MT_DEVICE,
157 }, {
158 .virtual = (unsigned long)S5P_VA_SYSTIMER,
159 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
160 .length = SZ_4K,
161 .type = MT_DEVICE,
162 }, {
163 .virtual = (unsigned long)S5P_VA_PMU,
164 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
165 .length = SZ_64K,
166 .type = MT_DEVICE,
167 }, {
168 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
169 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
170 .length = SZ_4K,
171 .type = MT_DEVICE,
172 }, {
173 .virtual = (unsigned long)S5P_VA_GIC_CPU,
174 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
175 .length = SZ_64K,
176 .type = MT_DEVICE,
177 }, {
178 .virtual = (unsigned long)S5P_VA_GIC_DIST,
179 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
180 .length = SZ_64K,
181 .type = MT_DEVICE,
182 }, {
183 .virtual = (unsigned long)S3C_VA_UART,
184 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
185 .length = SZ_512K,
186 .type = MT_DEVICE,
187 }, {
188 .virtual = (unsigned long)S5P_VA_CMU,
189 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
190 .length = SZ_128K,
191 .type = MT_DEVICE,
192 }, {
193 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
194 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
195 .length = SZ_8K,
196 .type = MT_DEVICE,
197 }, {
198 .virtual = (unsigned long)S5P_VA_L2CC,
199 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
200 .length = SZ_4K,
201 .type = MT_DEVICE,
202 }, {
203 .virtual = (unsigned long)S5P_VA_DMC0,
204 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
205 .length = SZ_64K,
206 .type = MT_DEVICE,
207 }, {
208 .virtual = (unsigned long)S5P_VA_DMC1,
209 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
210 .length = SZ_64K,
211 .type = MT_DEVICE,
212 }, {
213 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
214 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
215 .length = SZ_4K,
216 .type = MT_DEVICE,
217 },
218 };
219
220 static struct map_desc exynos4_iodesc0[] __initdata = {
221 {
222 .virtual = (unsigned long)S5P_VA_SYSRAM,
223 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
224 .length = SZ_4K,
225 .type = MT_DEVICE,
226 },
227 };
228
229 static struct map_desc exynos4_iodesc1[] __initdata = {
230 {
231 .virtual = (unsigned long)S5P_VA_SYSRAM,
232 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
233 .length = SZ_4K,
234 .type = MT_DEVICE,
235 },
236 };
237
238 static struct map_desc exynos5_iodesc[] __initdata = {
239 {
240 .virtual = (unsigned long)S3C_VA_SYS,
241 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
242 .length = SZ_64K,
243 .type = MT_DEVICE,
244 }, {
245 .virtual = (unsigned long)S3C_VA_TIMER,
246 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
247 .length = SZ_16K,
248 .type = MT_DEVICE,
249 }, {
250 .virtual = (unsigned long)S3C_VA_WATCHDOG,
251 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
252 .length = SZ_4K,
253 .type = MT_DEVICE,
254 }, {
255 .virtual = (unsigned long)S5P_VA_SROMC,
256 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
257 .length = SZ_4K,
258 .type = MT_DEVICE,
259 }, {
260 .virtual = (unsigned long)S5P_VA_SYSRAM,
261 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
262 .length = SZ_4K,
263 .type = MT_DEVICE,
264 }, {
265 .virtual = (unsigned long)S5P_VA_CMU,
266 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
267 .length = 144 * SZ_1K,
268 .type = MT_DEVICE,
269 }, {
270 .virtual = (unsigned long)S5P_VA_PMU,
271 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
272 .length = SZ_64K,
273 .type = MT_DEVICE,
274 }, {
275 .virtual = (unsigned long)S3C_VA_UART,
276 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
277 .length = SZ_512K,
278 .type = MT_DEVICE,
279 },
280 };
281
282 static struct map_desc exynos5440_iodesc0[] __initdata = {
283 {
284 .virtual = (unsigned long)S3C_VA_UART,
285 .pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
286 .length = SZ_512K,
287 .type = MT_DEVICE,
288 },
289 };
290
291 void exynos4_restart(char mode, const char *cmd)
292 {
293 __raw_writel(0x1, S5P_SWRESET);
294 }
295
296 void exynos5_restart(char mode, const char *cmd)
297 {
298 struct device_node *np;
299 u32 val;
300 void __iomem *addr;
301
302 if (of_machine_is_compatible("samsung,exynos5250")) {
303 val = 0x1;
304 addr = EXYNOS_SWRESET;
305 } else if (of_machine_is_compatible("samsung,exynos5440")) {
306 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
307 addr = of_iomap(np, 0) + 0xcc;
308 val = (0xfff << 20) | (0x1 << 16);
309 } else {
310 pr_err("%s: cannot support non-DT\n", __func__);
311 return;
312 }
313
314 __raw_writel(val, addr);
315 }
316
317 void __init exynos_init_late(void)
318 {
319 if (of_machine_is_compatible("samsung,exynos5440"))
320 /* to be supported later */
321 return;
322
323 exynos_pm_late_initcall();
324 }
325
326 /*
327 * exynos_map_io
328 *
329 * register the standard cpu IO areas
330 */
331
332 void __init exynos_init_io(struct map_desc *mach_desc, int size)
333 {
334 struct map_desc *iodesc = exynos_iodesc;
335 int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
336 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
337 unsigned long root = of_get_flat_dt_root();
338
339 /* initialize the io descriptors we need for initialization */
340 if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
341 iodesc = exynos5440_iodesc;
342 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
343 }
344 #endif
345
346 iotable_init(iodesc, iodesc_sz);
347
348 if (mach_desc)
349 iotable_init(mach_desc, size);
350
351 /* detect cpu id and rev. */
352 s5p_init_cpu(S5P_VA_CHIPID);
353
354 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
355 }
356
357 static void __init exynos4_map_io(void)
358 {
359 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
360
361 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
362 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
363 else
364 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
365
366 /* initialize device information early */
367 exynos4_default_sdhci0();
368 exynos4_default_sdhci1();
369 exynos4_default_sdhci2();
370 exynos4_default_sdhci3();
371
372 s3c_adc_setname("samsung-adc-v3");
373
374 s3c_fimc_setname(0, "exynos4-fimc");
375 s3c_fimc_setname(1, "exynos4-fimc");
376 s3c_fimc_setname(2, "exynos4-fimc");
377 s3c_fimc_setname(3, "exynos4-fimc");
378
379 s3c_sdhci_setname(0, "exynos4-sdhci");
380 s3c_sdhci_setname(1, "exynos4-sdhci");
381 s3c_sdhci_setname(2, "exynos4-sdhci");
382 s3c_sdhci_setname(3, "exynos4-sdhci");
383
384 /* The I2C bus controllers are directly compatible with s3c2440 */
385 s3c_i2c0_setname("s3c2440-i2c");
386 s3c_i2c1_setname("s3c2440-i2c");
387 s3c_i2c2_setname("s3c2440-i2c");
388
389 s5p_fb_setname(0, "exynos4-fb");
390 s5p_hdmi_setname("exynos4-hdmi");
391
392 s3c64xx_spi_setname("exynos4210-spi");
393 }
394
395 static void __init exynos5_map_io(void)
396 {
397 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
398 }
399
400 static void __init exynos4_init_clocks(int xtal)
401 {
402 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
403
404 s3c24xx_register_baseclocks(xtal);
405 s5p_register_clocks(xtal);
406
407 if (soc_is_exynos4210())
408 exynos4210_register_clocks();
409 else if (soc_is_exynos4212() || soc_is_exynos4412())
410 exynos4212_register_clocks();
411
412 exynos4_register_clocks();
413 exynos4_setup_clocks();
414 }
415
416 static void __init exynos5440_map_io(void)
417 {
418 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
419 }
420
421 static void __init exynos5_init_clocks(int xtal)
422 {
423 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
424
425 /* EXYNOS5440 can support only common clock framework */
426
427 if (soc_is_exynos5440())
428 return;
429
430 #ifdef CONFIG_SOC_EXYNOS5250
431 s3c24xx_register_baseclocks(xtal);
432 s5p_register_clocks(xtal);
433
434 exynos5_register_clocks();
435 exynos5_setup_clocks();
436 #endif
437 }
438
439 void __init exynos4_init_irq(void)
440 {
441 unsigned int gic_bank_offset;
442
443 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
444
445 if (!of_have_populated_dt())
446 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
447 #ifdef CONFIG_OF
448 else
449 irqchip_init();
450 #endif
451
452 if (!of_have_populated_dt())
453 combiner_init(S5P_VA_COMBINER_BASE, NULL);
454
455 /*
456 * The parameters of s5p_init_irq() are for VIC init.
457 * Theses parameters should be NULL and 0 because EXYNOS4
458 * uses GIC instead of VIC.
459 */
460 s5p_init_irq(NULL, 0);
461 }
462
463 void __init exynos5_init_irq(void)
464 {
465 #ifdef CONFIG_OF
466 irqchip_init();
467 #endif
468 /*
469 * The parameters of s5p_init_irq() are for VIC init.
470 * Theses parameters should be NULL and 0 because EXYNOS4
471 * uses GIC instead of VIC.
472 */
473 if (!of_machine_is_compatible("samsung,exynos5440"))
474 s5p_init_irq(NULL, 0);
475
476 gic_arch_extn.irq_set_wake = s3c_irq_wake;
477 }
478
479 struct bus_type exynos_subsys = {
480 .name = "exynos-core",
481 .dev_name = "exynos-core",
482 };
483
484 static struct device exynos4_dev = {
485 .bus = &exynos_subsys,
486 };
487
488 static int __init exynos_core_init(void)
489 {
490 return subsys_system_register(&exynos_subsys, NULL);
491 }
492 core_initcall(exynos_core_init);
493
494 #ifdef CONFIG_CACHE_L2X0
495 static int __init exynos4_l2x0_cache_init(void)
496 {
497 int ret;
498
499 if (soc_is_exynos5250() || soc_is_exynos5440())
500 return 0;
501
502 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
503 if (!ret) {
504 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
505 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
506 return 0;
507 }
508
509 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
510 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
511 /* TAG, Data Latency Control: 2 cycles */
512 l2x0_saved_regs.tag_latency = 0x110;
513
514 if (soc_is_exynos4212() || soc_is_exynos4412())
515 l2x0_saved_regs.data_latency = 0x120;
516 else
517 l2x0_saved_regs.data_latency = 0x110;
518
519 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
520 l2x0_saved_regs.pwr_ctrl =
521 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
522
523 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
524
525 __raw_writel(l2x0_saved_regs.tag_latency,
526 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
527 __raw_writel(l2x0_saved_regs.data_latency,
528 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
529
530 /* L2X0 Prefetch Control */
531 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
532 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
533
534 /* L2X0 Power Control */
535 __raw_writel(l2x0_saved_regs.pwr_ctrl,
536 S5P_VA_L2CC + L2X0_POWER_CTRL);
537
538 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
539 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
540 }
541
542 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
543 return 0;
544 }
545 early_initcall(exynos4_l2x0_cache_init);
546 #endif
547
548 static int __init exynos_init(void)
549 {
550 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
551
552 return device_register(&exynos4_dev);
553 }
554
555 /* uart registration process */
556
557 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
558 {
559 struct s3c2410_uartcfg *tcfg = cfg;
560 u32 ucnt;
561
562 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
563 tcfg->has_fracval = 1;
564
565 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
566 }
567
568 static void __iomem *exynos_eint_base;
569
570 static DEFINE_SPINLOCK(eint_lock);
571
572 static unsigned int eint0_15_data[16];
573
574 static inline int exynos4_irq_to_gpio(unsigned int irq)
575 {
576 if (irq < IRQ_EINT(0))
577 return -EINVAL;
578
579 irq -= IRQ_EINT(0);
580 if (irq < 8)
581 return EXYNOS4_GPX0(irq);
582
583 irq -= 8;
584 if (irq < 8)
585 return EXYNOS4_GPX1(irq);
586
587 irq -= 8;
588 if (irq < 8)
589 return EXYNOS4_GPX2(irq);
590
591 irq -= 8;
592 if (irq < 8)
593 return EXYNOS4_GPX3(irq);
594
595 return -EINVAL;
596 }
597
598 static inline int exynos5_irq_to_gpio(unsigned int irq)
599 {
600 if (irq < IRQ_EINT(0))
601 return -EINVAL;
602
603 irq -= IRQ_EINT(0);
604 if (irq < 8)
605 return EXYNOS5_GPX0(irq);
606
607 irq -= 8;
608 if (irq < 8)
609 return EXYNOS5_GPX1(irq);
610
611 irq -= 8;
612 if (irq < 8)
613 return EXYNOS5_GPX2(irq);
614
615 irq -= 8;
616 if (irq < 8)
617 return EXYNOS5_GPX3(irq);
618
619 return -EINVAL;
620 }
621
622 static unsigned int exynos4_eint0_15_src_int[16] = {
623 EXYNOS4_IRQ_EINT0,
624 EXYNOS4_IRQ_EINT1,
625 EXYNOS4_IRQ_EINT2,
626 EXYNOS4_IRQ_EINT3,
627 EXYNOS4_IRQ_EINT4,
628 EXYNOS4_IRQ_EINT5,
629 EXYNOS4_IRQ_EINT6,
630 EXYNOS4_IRQ_EINT7,
631 EXYNOS4_IRQ_EINT8,
632 EXYNOS4_IRQ_EINT9,
633 EXYNOS4_IRQ_EINT10,
634 EXYNOS4_IRQ_EINT11,
635 EXYNOS4_IRQ_EINT12,
636 EXYNOS4_IRQ_EINT13,
637 EXYNOS4_IRQ_EINT14,
638 EXYNOS4_IRQ_EINT15,
639 };
640
641 static unsigned int exynos5_eint0_15_src_int[16] = {
642 EXYNOS5_IRQ_EINT0,
643 EXYNOS5_IRQ_EINT1,
644 EXYNOS5_IRQ_EINT2,
645 EXYNOS5_IRQ_EINT3,
646 EXYNOS5_IRQ_EINT4,
647 EXYNOS5_IRQ_EINT5,
648 EXYNOS5_IRQ_EINT6,
649 EXYNOS5_IRQ_EINT7,
650 EXYNOS5_IRQ_EINT8,
651 EXYNOS5_IRQ_EINT9,
652 EXYNOS5_IRQ_EINT10,
653 EXYNOS5_IRQ_EINT11,
654 EXYNOS5_IRQ_EINT12,
655 EXYNOS5_IRQ_EINT13,
656 EXYNOS5_IRQ_EINT14,
657 EXYNOS5_IRQ_EINT15,
658 };
659 static inline void exynos_irq_eint_mask(struct irq_data *data)
660 {
661 u32 mask;
662
663 spin_lock(&eint_lock);
664 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
665 mask |= EINT_OFFSET_BIT(data->irq);
666 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
667 spin_unlock(&eint_lock);
668 }
669
670 static void exynos_irq_eint_unmask(struct irq_data *data)
671 {
672 u32 mask;
673
674 spin_lock(&eint_lock);
675 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
676 mask &= ~(EINT_OFFSET_BIT(data->irq));
677 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
678 spin_unlock(&eint_lock);
679 }
680
681 static inline void exynos_irq_eint_ack(struct irq_data *data)
682 {
683 __raw_writel(EINT_OFFSET_BIT(data->irq),
684 EINT_PEND(exynos_eint_base, data->irq));
685 }
686
687 static void exynos_irq_eint_maskack(struct irq_data *data)
688 {
689 exynos_irq_eint_mask(data);
690 exynos_irq_eint_ack(data);
691 }
692
693 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
694 {
695 int offs = EINT_OFFSET(data->irq);
696 int shift;
697 u32 ctrl, mask;
698 u32 newvalue = 0;
699
700 switch (type) {
701 case IRQ_TYPE_EDGE_RISING:
702 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
703 break;
704
705 case IRQ_TYPE_EDGE_FALLING:
706 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
707 break;
708
709 case IRQ_TYPE_EDGE_BOTH:
710 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
711 break;
712
713 case IRQ_TYPE_LEVEL_LOW:
714 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
715 break;
716
717 case IRQ_TYPE_LEVEL_HIGH:
718 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
719 break;
720
721 default:
722 printk(KERN_ERR "No such irq type %d", type);
723 return -EINVAL;
724 }
725
726 shift = (offs & 0x7) * 4;
727 mask = 0x7 << shift;
728
729 spin_lock(&eint_lock);
730 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
731 ctrl &= ~mask;
732 ctrl |= newvalue << shift;
733 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
734 spin_unlock(&eint_lock);
735
736 if (soc_is_exynos5250())
737 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
738 else
739 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
740
741 return 0;
742 }
743
744 static struct irq_chip exynos_irq_eint = {
745 .name = "exynos-eint",
746 .irq_mask = exynos_irq_eint_mask,
747 .irq_unmask = exynos_irq_eint_unmask,
748 .irq_mask_ack = exynos_irq_eint_maskack,
749 .irq_ack = exynos_irq_eint_ack,
750 .irq_set_type = exynos_irq_eint_set_type,
751 #ifdef CONFIG_PM
752 .irq_set_wake = s3c_irqext_wake,
753 #endif
754 };
755
756 /*
757 * exynos4_irq_demux_eint
758 *
759 * This function demuxes the IRQ from from EINTs 16 to 31.
760 * It is designed to be inlined into the specific handler
761 * s5p_irq_demux_eintX_Y.
762 *
763 * Each EINT pend/mask registers handle eight of them.
764 */
765 static inline void exynos_irq_demux_eint(unsigned int start)
766 {
767 unsigned int irq;
768
769 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
770 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
771
772 status &= ~mask;
773 status &= 0xff;
774
775 while (status) {
776 irq = fls(status) - 1;
777 generic_handle_irq(irq + start);
778 status &= ~(1 << irq);
779 }
780 }
781
782 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
783 {
784 struct irq_chip *chip = irq_get_chip(irq);
785 chained_irq_enter(chip, desc);
786 exynos_irq_demux_eint(IRQ_EINT(16));
787 exynos_irq_demux_eint(IRQ_EINT(24));
788 chained_irq_exit(chip, desc);
789 }
790
791 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
792 {
793 u32 *irq_data = irq_get_handler_data(irq);
794 struct irq_chip *chip = irq_get_chip(irq);
795
796 chained_irq_enter(chip, desc);
797 generic_handle_irq(*irq_data);
798 chained_irq_exit(chip, desc);
799 }
800
801 static int __init exynos_init_irq_eint(void)
802 {
803 int irq;
804
805 #ifdef CONFIG_PINCTRL_SAMSUNG
806 /*
807 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
808 * functionality along with support for external gpio and wakeup
809 * interrupts. If the samsung pinctrl driver is enabled and includes
810 * the wakeup interrupt support, then the setting up external wakeup
811 * interrupts here can be skipped. This check here is temporary to
812 * allow exynos4 platforms that do not use Samsung pinctrl driver to
813 * co-exist with platforms that do. When all of the Samsung Exynos4
814 * platforms switch over to using the pinctrl driver, the wakeup
815 * interrupt support code here can be completely removed.
816 */
817 static const struct of_device_id exynos_pinctrl_ids[] = {
818 { .compatible = "samsung,exynos4210-pinctrl", },
819 { .compatible = "samsung,exynos4x12-pinctrl", },
820 { .compatible = "samsung,exynos5250-pinctrl", },
821 };
822 struct device_node *pctrl_np, *wkup_np;
823 const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
824
825 for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
826 if (of_device_is_available(pctrl_np)) {
827 wkup_np = of_find_compatible_node(pctrl_np, NULL,
828 wkup_compat);
829 if (wkup_np)
830 return -ENODEV;
831 }
832 }
833 #endif
834 if (soc_is_exynos5440())
835 return 0;
836
837 if (soc_is_exynos5250())
838 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
839 else
840 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
841
842 if (exynos_eint_base == NULL) {
843 pr_err("unable to ioremap for EINT base address\n");
844 return -ENOMEM;
845 }
846
847 for (irq = 0 ; irq <= 31 ; irq++) {
848 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
849 handle_level_irq);
850 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
851 }
852
853 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
854
855 for (irq = 0 ; irq <= 15 ; irq++) {
856 eint0_15_data[irq] = IRQ_EINT(irq);
857
858 if (soc_is_exynos5250()) {
859 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
860 &eint0_15_data[irq]);
861 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
862 exynos_irq_eint0_15);
863 } else {
864 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
865 &eint0_15_data[irq]);
866 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
867 exynos_irq_eint0_15);
868 }
869 }
870
871 return 0;
872 }
873 arch_initcall(exynos_init_irq_eint);
Linux kernel - Deliverables
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