arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/bitops.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/irqchip.h>
  17 #include <linux/io.h>
  18 #include <linux/device.h>
  19 #include <linux/gpio.h>
  20 #include <clocksource/samsung_pwm.h>
  21 #include <linux/sched.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/of.h>
  24 #include <linux/of_fdt.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/export.h>
  27 #include <linux/irqdomain.h>
  28 #include <linux/of_address.h>
  29 #include <linux/clocksource.h>
  30 #include <linux/clk-provider.h>
  31 #include <linux/irqchip/arm-gic.h>
  32 #include <linux/irqchip/chained_irq.h>
  33
  34 #include <asm/proc-fns.h>
  35 #include <asm/exception.h>
  36 #include <asm/hardware/cache-l2x0.h>
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/irq.h>
  39 #include <asm/cacheflush.h>
  40
  41 #include <mach/regs-irq.h>
  42 #include <mach/regs-pmu.h>
  43 #include <mach/regs-gpio.h>
  44
  45 #include <plat/cpu.h>
  46 #include <plat/pm.h>
  47 #include <plat/regs-serial.h>
  48
  49 #include "common.h"
  50 #define L2_AUX_VAL 0x7C470001
  51 #define L2_AUX_MASK 0xC200ffff
  52
  53 static const char name_exynos4210[] = "EXYNOS4210";
  54 static const char name_exynos4212[] = "EXYNOS4212";
  55 static const char name_exynos4412[] = "EXYNOS4412";
  56 static const char name_exynos5250[] = "EXYNOS5250";
  57 static const char name_exynos5440[] = "EXYNOS5440";
  58
  59 static void exynos4_map_io(void);
  60 static void exynos5_map_io(void);
  61 static void exynos5440_map_io(void);
  62 static int exynos_init(void);
  63
  64 unsigned long xxti_f = 0, xusbxti_f = 0;
  65
  66 static struct cpu_table cpu_ids[] __initdata = {
  67         {
  68                 .idcode         = EXYNOS4210_CPU_ID,
  69                 .idmask         = EXYNOS4_CPU_MASK,
  70                 .map_io         = exynos4_map_io,
  71                 .init           = exynos_init,
  72                 .name           = name_exynos4210,
  73         }, {
  74                 .idcode         = EXYNOS4212_CPU_ID,
  75                 .idmask         = EXYNOS4_CPU_MASK,
  76                 .map_io         = exynos4_map_io,
  77                 .init           = exynos_init,
  78                 .name           = name_exynos4212,
  79         }, {
  80                 .idcode         = EXYNOS4412_CPU_ID,
  81                 .idmask         = EXYNOS4_CPU_MASK,
  82                 .map_io         = exynos4_map_io,
  83                 .init           = exynos_init,
  84                 .name           = name_exynos4412,
  85         }, {
  86                 .idcode         = EXYNOS5250_SOC_ID,
  87                 .idmask         = EXYNOS5_SOC_MASK,
  88                 .map_io         = exynos5_map_io,
  89                 .init           = exynos_init,
  90                 .name           = name_exynos5250,
  91         }, {
  92                 .idcode         = EXYNOS5440_SOC_ID,
  93                 .idmask         = EXYNOS5_SOC_MASK,
  94                 .map_io         = exynos5440_map_io,
  95                 .init           = exynos_init,
  96                 .name           = name_exynos5440,
  97         },
  98 };
  99
 100 /* Initial IO mappings */
 101
 102 static struct map_desc exynos4_iodesc[] __initdata = {
 103         {
 104                 .virtual        = (unsigned long)S3C_VA_SYS,
 105                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 106                 .length         = SZ_64K,
 107                 .type           = MT_DEVICE,
 108         }, {
 109                 .virtual        = (unsigned long)S3C_VA_TIMER,
 110                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 111                 .length         = SZ_16K,
 112                 .type           = MT_DEVICE,
 113         }, {
 114                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 115                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 116                 .length         = SZ_4K,
 117                 .type           = MT_DEVICE,
 118         }, {
 119                 .virtual        = (unsigned long)S5P_VA_SROMC,
 120                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 121                 .length         = SZ_4K,
 122                 .type           = MT_DEVICE,
 123         }, {
 124                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 125                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 126                 .length         = SZ_4K,
 127                 .type           = MT_DEVICE,
 128         }, {
 129                 .virtual        = (unsigned long)S5P_VA_PMU,
 130                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 131                 .length         = SZ_64K,
 132                 .type           = MT_DEVICE,
 133         }, {
 134                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 135                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 136                 .length         = SZ_4K,
 137                 .type           = MT_DEVICE,
 138         }, {
 139                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 140                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 141                 .length         = SZ_64K,
 142                 .type           = MT_DEVICE,
 143         }, {
 144                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 145                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 146                 .length         = SZ_64K,
 147                 .type           = MT_DEVICE,
 148         }, {
 149                 .virtual        = (unsigned long)S3C_VA_UART,
 150                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 151                 .length         = SZ_512K,
 152                 .type           = MT_DEVICE,
 153         }, {
 154                 .virtual        = (unsigned long)S5P_VA_CMU,
 155                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 156                 .length         = SZ_128K,
 157                 .type           = MT_DEVICE,
 158         }, {
 159                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 160                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 161                 .length         = SZ_8K,
 162                 .type           = MT_DEVICE,
 163         }, {
 164                 .virtual        = (unsigned long)S5P_VA_L2CC,
 165                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 166                 .length         = SZ_4K,
 167                 .type           = MT_DEVICE,
 168         }, {
 169                 .virtual        = (unsigned long)S5P_VA_DMC0,
 170                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 171                 .length         = SZ_64K,
 172                 .type           = MT_DEVICE,
 173         }, {
 174                 .virtual        = (unsigned long)S5P_VA_DMC1,
 175                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 176                 .length         = SZ_64K,
 177                 .type           = MT_DEVICE,
 178         }, {
 179                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 180                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 181                 .length         = SZ_4K,
 182                 .type           = MT_DEVICE,
 183         },
 184 };
 185
 186 static struct map_desc exynos4_iodesc0[] __initdata = {
 187         {
 188                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 189                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 190                 .length         = SZ_4K,
 191                 .type           = MT_DEVICE,
 192         },
 193 };
 194
 195 static struct map_desc exynos4_iodesc1[] __initdata = {
 196         {
 197                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 198                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 199                 .length         = SZ_4K,
 200                 .type           = MT_DEVICE,
 201         },
 202 };
 203
 204 static struct map_desc exynos4210_iodesc[] __initdata = {
 205         {
 206                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 207                 .pfn            = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
 208                 .length         = SZ_4K,
 209                 .type           = MT_DEVICE,
 210         },
 211 };
 212
 213 static struct map_desc exynos4x12_iodesc[] __initdata = {
 214         {
 215                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 216                 .pfn            = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
 217                 .length         = SZ_4K,
 218                 .type           = MT_DEVICE,
 219         },
 220 };
 221
 222 static struct map_desc exynos5250_iodesc[] __initdata = {
 223         {
 224                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 225                 .pfn            = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
 226                 .length         = SZ_4K,
 227                 .type           = MT_DEVICE,
 228         },
 229 };
 230
 231 static struct map_desc exynos5_iodesc[] __initdata = {
 232         {
 233                 .virtual        = (unsigned long)S3C_VA_SYS,
 234                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 235                 .length         = SZ_64K,
 236                 .type           = MT_DEVICE,
 237         }, {
 238                 .virtual        = (unsigned long)S3C_VA_TIMER,
 239                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 240                 .length         = SZ_16K,
 241                 .type           = MT_DEVICE,
 242         }, {
 243                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 244                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 245                 .length         = SZ_4K,
 246                 .type           = MT_DEVICE,
 247         }, {
 248                 .virtual        = (unsigned long)S5P_VA_SROMC,
 249                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 250                 .length         = SZ_4K,
 251                 .type           = MT_DEVICE,
 252         }, {
 253                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 254                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 255                 .length         = SZ_4K,
 256                 .type           = MT_DEVICE,
 257         }, {
 258                 .virtual        = (unsigned long)S5P_VA_CMU,
 259                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 260                 .length         = 144 * SZ_1K,
 261                 .type           = MT_DEVICE,
 262         }, {
 263                 .virtual        = (unsigned long)S5P_VA_PMU,
 264                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 265                 .length         = SZ_64K,
 266                 .type           = MT_DEVICE,
 267         }, {
 268                 .virtual        = (unsigned long)S3C_VA_UART,
 269                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 270                 .length         = SZ_512K,
 271                 .type           = MT_DEVICE,
 272         },
 273 };
 274
 275 static struct map_desc exynos5440_iodesc0[] __initdata = {
 276         {
 277                 .virtual        = (unsigned long)S3C_VA_UART,
 278                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 279                 .length         = SZ_512K,
 280                 .type           = MT_DEVICE,
 281         },
 282 };
 283
 284 void exynos4_restart(char mode, const char *cmd)
 285 {
 286         __raw_writel(0x1, S5P_SWRESET);
 287 }
 288
 289 void exynos5_restart(char mode, const char *cmd)
 290 {
 291         struct device_node *np;
 292         u32 val;
 293         void __iomem *addr;
 294
 295         if (of_machine_is_compatible("samsung,exynos5250")) {
 296                 val = 0x1;
 297                 addr = EXYNOS_SWRESET;
 298         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 299                 u32 status;
 300                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 301
 302                 addr = of_iomap(np, 0) + 0xbc;
 303                 status = __raw_readl(addr);
 304
 305                 addr = of_iomap(np, 0) + 0xcc;
 306                 val = __raw_readl(addr);
 307
 308                 val = (val & 0xffff0000) | (status & 0xffff);
 309         } else {
 310                 pr_err("%s: cannot support non-DT\n", __func__);
 311                 return;
 312         }
 313
 314         __raw_writel(val, addr);
 315 }
 316
 317 void __init exynos_init_late(void)
 318 {
 319         if (of_machine_is_compatible("samsung,exynos5440"))
 320                 /* to be supported later */
 321                 return;
 322
 323         exynos_pm_late_initcall();
 324 }
 325
 326 int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 327                                         int depth, void *data)
 328 {
 329         struct map_desc iodesc;
 330         __be32 *reg;
 331         unsigned long len;
 332
 333         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
 334                 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
 335                 return 0;
 336
 337         reg = of_get_flat_dt_prop(node, "reg", &len);
 338         if (reg == NULL || len != (sizeof(unsigned long) * 2))
 339                 return 0;
 340
 341         iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 342         iodesc.length = be32_to_cpu(reg[1]) - 1;
 343         iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
 344         iodesc.type = MT_DEVICE;
 345         iotable_init(&iodesc, 1);
 346         return 1;
 347 }
 348
 349 /*
 350  * exynos_map_io
 351  *
 352  * register the standard cpu IO areas
 353  */
 354
 355 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 356 {
 357         debug_ll_io_init();
 358
 359         of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 360
 361         if (mach_desc)
 362                 iotable_init(mach_desc, size);
 363
 364         /* detect cpu id and rev. */
 365         s5p_init_cpu(S5P_VA_CHIPID);
 366
 367         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 368 }
 369
 370 static void __init exynos4_map_io(void)
 371 {
 372         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 373
 374         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 375                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 376         else
 377                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 378
 379         if (soc_is_exynos4210())
 380                 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
 381         if (soc_is_exynos4212() || soc_is_exynos4412())
 382                 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
 383 }
 384
 385 static void __init exynos5_map_io(void)
 386 {
 387         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 388
 389         if (soc_is_exynos5250())
 390                 iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 391 }
 392
 393 static void __init exynos5440_map_io(void)
 394 {
 395         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 396 }
 397
 398 void __init exynos_init_time(void)
 399 {
 400         of_clk_init(NULL);
 401         clocksource_of_init();
 402 }
 403
 404 void __init exynos4_init_irq(void)
 405 {
 406         irqchip_init();
 407 }
 408
 409 void __init exynos5_init_irq(void)
 410 {
 411         irqchip_init();
 412 }
 413
 414 struct bus_type exynos_subsys = {
 415         .name           = "exynos-core",
 416         .dev_name       = "exynos-core",
 417 };
 418
 419 static struct device exynos4_dev = {
 420         .bus    = &exynos_subsys,
 421 };
 422
 423 static int __init exynos_core_init(void)
 424 {
 425         return subsys_system_register(&exynos_subsys, NULL);
 426 }
 427 core_initcall(exynos_core_init);
 428
 429 #ifdef CONFIG_CACHE_L2X0
 430 static int __init exynos4_l2x0_cache_init(void)
 431 {
 432         int ret;
 433
 434         if (soc_is_exynos5250() || soc_is_exynos5440())
 435                 return 0;
 436
 437         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 438         if (!ret) {
 439                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 440                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 441                 return 0;
 442         }
 443
 444         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 445                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 446                 /* TAG, Data Latency Control: 2 cycles */
 447                 l2x0_saved_regs.tag_latency = 0x110;
 448
 449                 if (soc_is_exynos4212() || soc_is_exynos4412())
 450                         l2x0_saved_regs.data_latency = 0x120;
 451                 else
 452                         l2x0_saved_regs.data_latency = 0x110;
 453
 454                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 455                 l2x0_saved_regs.pwr_ctrl =
 456                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 457
 458                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 459
 460                 __raw_writel(l2x0_saved_regs.tag_latency,
 461                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 462                 __raw_writel(l2x0_saved_regs.data_latency,
 463                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 464
 465                 /* L2X0 Prefetch Control */
 466                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 467                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 468
 469                 /* L2X0 Power Control */
 470                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 471                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 472
 473                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 474                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 475         }
 476
 477         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 478         return 0;
 479 }
 480 early_initcall(exynos4_l2x0_cache_init);
 481 #endif
 482
 483 static int __init exynos_init(void)
 484 {
 485         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 486
 487         return device_register(&exynos4_dev);
 488 }