arch/arm/mach-exynos/exynos.c

   1 /*
   2  * SAMSUNG EXYNOS Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/serial_s3c.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_fdt.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_domain.h>
  22 #include <linux/irqchip.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/hardware/cache-l2x0.h>
  26 #include <asm/mach/arch.h>
  27 #include <asm/mach/map.h>
  28 #include <asm/memory.h>
  29
  30 #include "common.h"
  31 #include "mfc.h"
  32 #include "regs-pmu.h"
  33 #include "regs-sys.h"
  34
  35 void __iomem *pmu_base_addr;
  36
  37 static struct map_desc exynos4_iodesc[] __initdata = {
  38         {
  39                 .virtual        = (unsigned long)S3C_VA_SYS,
  40                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
  41                 .length         = SZ_64K,
  42                 .type           = MT_DEVICE,
  43         }, {
  44                 .virtual        = (unsigned long)S3C_VA_TIMER,
  45                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
  46                 .length         = SZ_16K,
  47                 .type           = MT_DEVICE,
  48         }, {
  49                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
  50                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
  51                 .length         = SZ_4K,
  52                 .type           = MT_DEVICE,
  53         }, {
  54                 .virtual        = (unsigned long)S5P_VA_SROMC,
  55                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
  56                 .length         = SZ_4K,
  57                 .type           = MT_DEVICE,
  58         }, {
  59                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
  60                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  61                 .length         = SZ_4K,
  62                 .type           = MT_DEVICE,
  63         }, {
  64                 .virtual        = (unsigned long)S5P_VA_PMU,
  65                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
  66                 .length         = SZ_64K,
  67                 .type           = MT_DEVICE,
  68         }, {
  69                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  70                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  71                 .length         = SZ_4K,
  72                 .type           = MT_DEVICE,
  73         }, {
  74                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
  75                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
  76                 .length         = SZ_64K,
  77                 .type           = MT_DEVICE,
  78         }, {
  79                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
  80                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
  81                 .length         = SZ_64K,
  82                 .type           = MT_DEVICE,
  83         }, {
  84                 .virtual        = (unsigned long)S5P_VA_CMU,
  85                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
  86                 .length         = SZ_128K,
  87                 .type           = MT_DEVICE,
  88         }, {
  89                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  90                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  91                 .length         = SZ_8K,
  92                 .type           = MT_DEVICE,
  93         }, {
  94                 .virtual        = (unsigned long)S5P_VA_L2CC,
  95                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
  96                 .length         = SZ_4K,
  97                 .type           = MT_DEVICE,
  98         }, {
  99                 .virtual        = (unsigned long)S5P_VA_DMC0,
 100                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 101                 .length         = SZ_64K,
 102                 .type           = MT_DEVICE,
 103         }, {
 104                 .virtual        = (unsigned long)S5P_VA_DMC1,
 105                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 106                 .length         = SZ_64K,
 107                 .type           = MT_DEVICE,
 108         }, {
 109                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 110                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 111                 .length         = SZ_4K,
 112                 .type           = MT_DEVICE,
 113         },
 114 };
 115
 116 static struct map_desc exynos5_iodesc[] __initdata = {
 117         {
 118                 .virtual        = (unsigned long)S3C_VA_SYS,
 119                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 120                 .length         = SZ_64K,
 121                 .type           = MT_DEVICE,
 122         }, {
 123                 .virtual        = (unsigned long)S3C_VA_TIMER,
 124                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 125                 .length         = SZ_16K,
 126                 .type           = MT_DEVICE,
 127         }, {
 128                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 129                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 130                 .length         = SZ_4K,
 131                 .type           = MT_DEVICE,
 132         }, {
 133                 .virtual        = (unsigned long)S5P_VA_SROMC,
 134                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 135                 .length         = SZ_4K,
 136                 .type           = MT_DEVICE,
 137         }, {
 138                 .virtual        = (unsigned long)S5P_VA_CMU,
 139                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 140                 .length         = 144 * SZ_1K,
 141                 .type           = MT_DEVICE,
 142         }, {
 143                 .virtual        = (unsigned long)S5P_VA_PMU,
 144                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 145                 .length         = SZ_64K,
 146                 .type           = MT_DEVICE,
 147         },
 148 };
 149
 150 static void exynos_restart(enum reboot_mode mode, const char *cmd)
 151 {
 152         struct device_node *np;
 153         u32 val = 0x1;
 154         void __iomem *addr = EXYNOS_SWRESET;
 155
 156         if (of_machine_is_compatible("samsung,exynos5440")) {
 157                 u32 status;
 158                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 159
 160                 addr = of_iomap(np, 0) + 0xbc;
 161                 status = __raw_readl(addr);
 162
 163                 addr = of_iomap(np, 0) + 0xcc;
 164                 val = __raw_readl(addr);
 165
 166                 val = (val & 0xffff0000) | (status & 0xffff);
 167         }
 168
 169         __raw_writel(val, addr);
 170 }
 171
 172 static struct platform_device exynos_cpuidle = {
 173         .name              = "exynos_cpuidle",
 174         .dev.platform_data = exynos_enter_aftr,
 175         .id                = -1,
 176 };
 177
 178 void __init exynos_cpuidle_init(void)
 179 {
 180         if (soc_is_exynos4210() || soc_is_exynos5250())
 181                 platform_device_register(&exynos_cpuidle);
 182 }
 183
 184 void __init exynos_cpufreq_init(void)
 185 {
 186         platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
 187 }
 188
 189 void __iomem *sysram_base_addr;
 190 void __iomem *sysram_ns_base_addr;
 191
 192 void __init exynos_sysram_init(void)
 193 {
 194         struct device_node *node;
 195
 196         for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
 197                 if (!of_device_is_available(node))
 198                         continue;
 199                 sysram_base_addr = of_iomap(node, 0);
 200                 break;
 201         }
 202
 203         for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
 204                 if (!of_device_is_available(node))
 205                         continue;
 206                 sysram_ns_base_addr = of_iomap(node, 0);
 207                 break;
 208         }
 209 }
 210
 211 static void __init exynos_init_late(void)
 212 {
 213         if (of_machine_is_compatible("samsung,exynos5440"))
 214                 /* to be supported later */
 215                 return;
 216
 217         pm_genpd_poweroff_unused();
 218         exynos_pm_init();
 219 }
 220
 221 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 222                                         int depth, void *data)
 223 {
 224         struct map_desc iodesc;
 225         const __be32 *reg;
 226         int len;
 227
 228         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
 229                 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
 230                 return 0;
 231
 232         reg = of_get_flat_dt_prop(node, "reg", &len);
 233         if (reg == NULL || len != (sizeof(unsigned long) * 2))
 234                 return 0;
 235
 236         iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 237         iodesc.length = be32_to_cpu(reg[1]) - 1;
 238         iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
 239         iodesc.type = MT_DEVICE;
 240         iotable_init(&iodesc, 1);
 241         return 1;
 242 }
 243
 244 /*
 245  * exynos_map_io
 246  *
 247  * register the standard cpu IO areas
 248  */
 249 static void __init exynos_map_io(void)
 250 {
 251         if (soc_is_exynos4())
 252                 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 253
 254         if (soc_is_exynos5())
 255                 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 256 }
 257
 258 static void __init exynos_init_io(void)
 259 {
 260         debug_ll_io_init();
 261
 262         of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 263
 264         /* detect cpu id and rev. */
 265         s5p_init_cpu(S5P_VA_CHIPID);
 266
 267         exynos_map_io();
 268 }
 269
 270 static const struct of_device_id exynos_dt_pmu_match[] = {
 271         { .compatible = "samsung,exynos3250-pmu" },
 272         { .compatible = "samsung,exynos4210-pmu" },
 273         { .compatible = "samsung,exynos4212-pmu" },
 274         { .compatible = "samsung,exynos4412-pmu" },
 275         { .compatible = "samsung,exynos5250-pmu" },
 276         { .compatible = "samsung,exynos5420-pmu" },
 277         { /*sentinel*/ },
 278 };
 279
 280 static void exynos_map_pmu(void)
 281 {
 282         struct device_node *np;
 283
 284         np = of_find_matching_node(NULL, exynos_dt_pmu_match);
 285         if (np)
 286                 pmu_base_addr = of_iomap(np, 0);
 287
 288         if (!pmu_base_addr)
 289                 panic("failed to find exynos pmu register\n");
 290 }
 291
 292 static void __init exynos_init_irq(void)
 293 {
 294         irqchip_init();
 295         /*
 296          * Since platsmp.c needs pmu base address by the time
 297          * DT is not unflatten so we can't use DT APIs before
 298          * init_irq
 299          */
 300         exynos_map_pmu();
 301 }
 302
 303 static void __init exynos_dt_machine_init(void)
 304 {
 305         struct device_node *i2c_np;
 306         const char *i2c_compat = "samsung,s3c2440-i2c";
 307         unsigned int tmp;
 308         int id;
 309
 310         /*
 311          * Exynos5's legacy i2c controller and new high speed i2c
 312          * controller have muxed interrupt sources. By default the
 313          * interrupts for 4-channel HS-I2C controller are enabled.
 314          * If node for first four channels of legacy i2c controller
 315          * are available then re-configure the interrupts via the
 316          * system register.
 317          */
 318         if (soc_is_exynos5()) {
 319                 for_each_compatible_node(i2c_np, NULL, i2c_compat) {
 320                         if (of_device_is_available(i2c_np)) {
 321                                 id = of_alias_get_id(i2c_np, "i2c");
 322                                 if (id < 4) {
 323                                         tmp = readl(EXYNOS5_SYS_I2C_CFG);
 324                                         writel(tmp & ~(0x1 << id),
 325                                                         EXYNOS5_SYS_I2C_CFG);
 326                                 }
 327                         }
 328                 }
 329         }
 330
 331         /*
 332          * This is called from smp_prepare_cpus if we've built for SMP, but
 333          * we still need to set it up for PM and firmware ops if not.
 334          */
 335         if (!IS_ENABLED(CONFIG_SMP))
 336                 exynos_sysram_init();
 337
 338         exynos_cpuidle_init();
 339         exynos_cpufreq_init();
 340
 341         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 342 }
 343
 344 static char const *exynos_dt_compat[] __initconst = {
 345         "samsung,exynos3",
 346         "samsung,exynos3250",
 347         "samsung,exynos4",
 348         "samsung,exynos4210",
 349         "samsung,exynos4212",
 350         "samsung,exynos4412",
 351         "samsung,exynos5",
 352         "samsung,exynos5250",
 353         "samsung,exynos5260",
 354         "samsung,exynos5420",
 355         "samsung,exynos5440",
 356         NULL
 357 };
 358
 359 static void __init exynos_reserve(void)
 360 {
 361 #ifdef CONFIG_S5P_DEV_MFC
 362         int i;
 363         char *mfc_mem[] = {
 364                 "samsung,mfc-v5",
 365                 "samsung,mfc-v6",
 366                 "samsung,mfc-v7",
 367         };
 368
 369         for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
 370                 if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
 371                         break;
 372 #endif
 373 }
 374
 375 DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
 376         /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
 377         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 378         .l2c_aux_val    = 0x3c400001,
 379         .l2c_aux_mask   = 0xc20fffff,
 380         .smp            = smp_ops(exynos_smp_ops),
 381         .map_io         = exynos_init_io,
 382         .init_early     = exynos_firmware_init,
 383         .init_irq       = exynos_init_irq,
 384         .init_machine   = exynos_dt_machine_init,
 385         .init_late      = exynos_init_late,
 386         .dt_compat      = exynos_dt_compat,
 387         .restart        = exynos_restart,
 388         .reserve        = exynos_reserve,
 389 MACHINE_END