arch/arm/mach-exynos/hotplug.c

   1 /* linux arch/arm/mach-exynos4/hotplug.c
   2  *
   3  *  Cloned from linux/arch/arm/mach-realview/hotplug.c
   4  *
   5  *  Copyright (C) 2002 ARM Ltd.
   6  *  All Rights Reserved
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/errno.h>
  15 #include <linux/smp.h>
  16 #include <linux/io.h>
  17
  18 #include <asm/cacheflush.h>
  19 #include <asm/cp15.h>
  20 #include <asm/smp_plat.h>
  21
  22 #include <plat/cpu.h>
  23
  24 #include "common.h"
  25 #include "regs-pmu.h"
  26
  27 static inline void cpu_enter_lowpower_a9(void)
  28 {
  29         unsigned int v;
  30
  31         asm volatile(
  32         "       mcr     p15, 0, %1, c7, c5, 0\n"
  33         "       mcr     p15, 0, %1, c7, c10, 4\n"
  34         /*
  35          * Turn off coherency
  36          */
  37         "       mrc     p15, 0, %0, c1, c0, 1\n"
  38         "       bic     %0, %0, %3\n"
  39         "       mcr     p15, 0, %0, c1, c0, 1\n"
  40         "       mrc     p15, 0, %0, c1, c0, 0\n"
  41         "       bic     %0, %0, %2\n"
  42         "       mcr     p15, 0, %0, c1, c0, 0\n"
  43           : "=&r" (v)
  44           : "r" (0), "Ir" (CR_C), "Ir" (0x40)
  45           : "cc");
  46 }
  47
  48 static inline void cpu_enter_lowpower_a15(void)
  49 {
  50         unsigned int v;
  51
  52         asm volatile(
  53         "       mrc     p15, 0, %0, c1, c0, 0\n"
  54         "       bic     %0, %0, %1\n"
  55         "       mcr     p15, 0, %0, c1, c0, 0\n"
  56           : "=&r" (v)
  57           : "Ir" (CR_C)
  58           : "cc");
  59
  60         flush_cache_louis();
  61
  62         asm volatile(
  63         /*
  64         * Turn off coherency
  65         */
  66         "       mrc     p15, 0, %0, c1, c0, 1\n"
  67         "       bic     %0, %0, %1\n"
  68         "       mcr     p15, 0, %0, c1, c0, 1\n"
  69         : "=&r" (v)
  70         : "Ir" (0x40)
  71         : "cc");
  72
  73         isb();
  74         dsb();
  75 }
  76
  77 static inline void cpu_leave_lowpower(void)
  78 {
  79         unsigned int v;
  80
  81         asm volatile(
  82         "mrc    p15, 0, %0, c1, c0, 0\n"
  83         "       orr     %0, %0, %1\n"
  84         "       mcr     p15, 0, %0, c1, c0, 0\n"
  85         "       mrc     p15, 0, %0, c1, c0, 1\n"
  86         "       orr     %0, %0, %2\n"
  87         "       mcr     p15, 0, %0, c1, c0, 1\n"
  88           : "=&r" (v)
  89           : "Ir" (CR_C), "Ir" (0x40)
  90           : "cc");
  91 }
  92
  93 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
  94 {
  95         for (;;) {
  96
  97                 /* make cpu1 to be turned off at next WFI command */
  98                 if (cpu == 1)
  99                         __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
 100
 101                 /*
 102                  * here's the WFI
 103                  */
 104                 asm(".word      0xe320f003\n"
 105                     :
 106                     :
 107                     : "memory", "cc");
 108
 109                 if (pen_release == cpu_logical_map(cpu)) {
 110                         /*
 111                          * OK, proper wakeup, we're done
 112                          */
 113                         break;
 114                 }
 115
 116                 /*
 117                  * Getting here, means that we have come out of WFI without
 118                  * having been woken up - this shouldn't happen
 119                  *
 120                  * Just note it happening - when we're woken, we can report
 121                  * its occurrence.
 122                  */
 123                 (*spurious)++;
 124         }
 125 }
 126
 127 /*
 128  * platform-specific code to shutdown a CPU
 129  *
 130  * Called with IRQs disabled
 131  */
 132 void __ref exynos_cpu_die(unsigned int cpu)
 133 {
 134         int spurious = 0;
 135         int primary_part = 0;
 136
 137         /*
 138          * we're ready for shutdown now, so do it.
 139          * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
 140          * number by reading the Main ID register and then perform the
 141          * appropriate sequence for entering low power.
 142          */
 143         asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
 144         if ((primary_part & 0xfff0) == 0xc0f0)
 145                 cpu_enter_lowpower_a15();
 146         else
 147                 cpu_enter_lowpower_a9();
 148
 149         platform_do_lowpower(cpu, &spurious);
 150
 151         /*
 152          * bring this CPU back into the world of cache
 153          * coherency, and then restore interrupts
 154          */
 155         cpu_leave_lowpower();
 156
 157         if (spurious)
 158                 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 159 }