arch/arm/mach-exynos/include/mach/regs-usb-phy.h

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   3  * Author: Joonyoung Shim <jy0922.shim@samsung.com>
   4  *
   5  * This program is free software; you can redistribute  it and/or modify it
   6  * under  the terms of  the GNU General  Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #ifndef __PLAT_S5P_REGS_USB_PHY_H
  12 #define __PLAT_S5P_REGS_USB_PHY_H
  13
  14 #define EXYNOS4_HSOTG_PHYREG(x)         ((x) + S3C_VA_USB_HSPHY)
  15
  16 #define EXYNOS4_PHYPWR                  EXYNOS4_HSOTG_PHYREG(0x00)
  17 #define PHY1_HSIC_NORMAL_MASK           (0xf << 9)
  18 #define PHY1_HSIC1_SLEEP                (1 << 12)
  19 #define PHY1_HSIC1_FORCE_SUSPEND        (1 << 11)
  20 #define PHY1_HSIC0_SLEEP                (1 << 10)
  21 #define PHY1_HSIC0_FORCE_SUSPEND        (1 << 9)
  22
  23 #define PHY1_STD_NORMAL_MASK            (0x7 << 6)
  24 #define PHY1_STD_SLEEP                  (1 << 8)
  25 #define PHY1_STD_ANALOG_POWERDOWN       (1 << 7)
  26 #define PHY1_STD_FORCE_SUSPEND          (1 << 6)
  27
  28 #define PHY0_NORMAL_MASK                (0x39 << 0)
  29 #define PHY0_SLEEP                      (1 << 5)
  30 #define PHY0_OTG_DISABLE                (1 << 4)
  31 #define PHY0_ANALOG_POWERDOWN           (1 << 3)
  32 #define PHY0_FORCE_SUSPEND              (1 << 0)
  33
  34 #define EXYNOS4_PHYCLK                  EXYNOS4_HSOTG_PHYREG(0x04)
  35 #define PHY1_COMMON_ON_N                (1 << 7)
  36 #define PHY0_COMMON_ON_N                (1 << 4)
  37 #define PHY0_ID_PULLUP                  (1 << 2)
  38
  39 #define EXYNOS4_CLKSEL_SHIFT            (0)
  40
  41 #define EXYNOS4210_CLKSEL_MASK          (0x3 << 0)
  42 #define EXYNOS4210_CLKSEL_48M           (0x0 << 0)
  43 #define EXYNOS4210_CLKSEL_12M           (0x2 << 0)
  44 #define EXYNOS4210_CLKSEL_24M           (0x3 << 0)
  45
  46 #define EXYNOS4X12_CLKSEL_MASK          (0x7 << 0)
  47 #define EXYNOS4X12_CLKSEL_9600K         (0x0 << 0)
  48 #define EXYNOS4X12_CLKSEL_10M           (0x1 << 0)
  49 #define EXYNOS4X12_CLKSEL_12M           (0x2 << 0)
  50 #define EXYNOS4X12_CLKSEL_19200K        (0x3 << 0)
  51 #define EXYNOS4X12_CLKSEL_20M           (0x4 << 0)
  52 #define EXYNOS4X12_CLKSEL_24M           (0x5 << 0)
  53
  54 #define EXYNOS4_RSTCON                  EXYNOS4_HSOTG_PHYREG(0x08)
  55 #define HOST_LINK_PORT_SWRST_MASK       (0xf << 6)
  56 #define HOST_LINK_PORT2_SWRST           (1 << 9)
  57 #define HOST_LINK_PORT1_SWRST           (1 << 8)
  58 #define HOST_LINK_PORT0_SWRST           (1 << 7)
  59 #define HOST_LINK_ALL_SWRST             (1 << 6)
  60
  61 #define PHY1_SWRST_MASK                 (0x7 << 3)
  62 #define PHY1_HSIC_SWRST                 (1 << 5)
  63 #define PHY1_STD_SWRST                  (1 << 4)
  64 #define PHY1_ALL_SWRST                  (1 << 3)
  65
  66 #define PHY0_SWRST_MASK                 (0x7 << 0)
  67 #define PHY0_PHYLINK_SWRST              (1 << 2)
  68 #define PHY0_HLINK_SWRST                (1 << 1)
  69 #define PHY0_SWRST                      (1 << 0)
  70
  71 #define EXYNOS4_PHY1CON                 EXYNOS4_HSOTG_PHYREG(0x34)
  72 #define FPENABLEN                       (1 << 0)
  73
  74 #endif /* __PLAT_S5P_REGS_USB_PHY_H */