arch/arm/mach-exynos/platsmp.c

   1  /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
   6  *
   7  *  Copyright (C) 2002 ARM Ltd.
   8  *  All Rights Reserved
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/init.h>
  16 #include <linux/errno.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/jiffies.h>
  20 #include <linux/smp.h>
  21 #include <linux/io.h>
  22 #include <linux/of_address.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/cp15.h>
  26 #include <asm/smp_plat.h>
  27 #include <asm/smp_scu.h>
  28 #include <asm/firmware.h>
  29
  30 #include <mach/map.h>
  31
  32 #include "common.h"
  33 #include "regs-pmu.h"
  34
  35 extern void exynos4_secondary_startup(void);
  36
  37 /*
  38  * Set or clear the USE_DELAYED_RESET_ASSERTION option, set on Exynos4 SoCs
  39  * during hot-(un)plugging CPUx.
  40  *
  41  * The feature can be cleared safely during first boot of secondary CPU.
  42  *
  43  * Exynos4 SoCs require setting USE_DELAYED_RESET_ASSERTION during powering
  44  * down a CPU so the CPU idle clock down feature could properly detect global
  45  * idle state when CPUx is off.
  46  */
  47 static void exynos_set_delayed_reset_assertion(u32 core_id, bool enable)
  48 {
  49         if (soc_is_exynos4()) {
  50                 unsigned int tmp;
  51
  52                 tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));
  53                 if (enable)
  54                         tmp |= S5P_USE_DELAYED_RESET_ASSERTION;
  55                 else
  56                         tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION);
  57                 pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));
  58         }
  59 }
  60
  61 #ifdef CONFIG_HOTPLUG_CPU
  62 static inline void cpu_leave_lowpower(u32 core_id)
  63 {
  64         unsigned int v;
  65
  66         asm volatile(
  67         "mrc    p15, 0, %0, c1, c0, 0\n"
  68         "       orr     %0, %0, %1\n"
  69         "       mcr     p15, 0, %0, c1, c0, 0\n"
  70         "       mrc     p15, 0, %0, c1, c0, 1\n"
  71         "       orr     %0, %0, %2\n"
  72         "       mcr     p15, 0, %0, c1, c0, 1\n"
  73           : "=&r" (v)
  74           : "Ir" (CR_C), "Ir" (0x40)
  75           : "cc");
  76
  77          exynos_set_delayed_reset_assertion(core_id, false);
  78 }
  79
  80 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
  81 {
  82         u32 mpidr = cpu_logical_map(cpu);
  83         u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
  84
  85         for (;;) {
  86
  87                 /* Turn the CPU off on next WFI instruction. */
  88                 exynos_cpu_power_down(core_id);
  89
  90                 /*
  91                  * Exynos4 SoCs require setting
  92                  * USE_DELAYED_RESET_ASSERTION so the CPU idle
  93                  * clock down feature could properly detect
  94                  * global idle state when CPUx is off.
  95                  */
  96                 exynos_set_delayed_reset_assertion(core_id, true);
  97
  98                 wfi();
  99
 100                 if (pen_release == core_id) {
 101                         /*
 102                          * OK, proper wakeup, we're done
 103                          */
 104                         break;
 105                 }
 106
 107                 /*
 108                  * Getting here, means that we have come out of WFI without
 109                  * having been woken up - this shouldn't happen
 110                  *
 111                  * Just note it happening - when we're woken, we can report
 112                  * its occurrence.
 113                  */
 114                 (*spurious)++;
 115         }
 116 }
 117 #endif /* CONFIG_HOTPLUG_CPU */
 118
 119 /**
 120  * exynos_core_power_down : power down the specified cpu
 121  * @cpu : the cpu to power down
 122  *
 123  * Power down the specified cpu. The sequence must be finished by a
 124  * call to cpu_do_idle()
 125  *
 126  */
 127 void exynos_cpu_power_down(int cpu)
 128 {
 129         if (cpu == 0 && (of_machine_is_compatible("samsung,exynos5420") ||
 130                 of_machine_is_compatible("samsung,exynos5800"))) {
 131                 /*
 132                  * Bypass power down for CPU0 during suspend. Check for
 133                  * the SYS_PWR_REG value to decide if we are suspending
 134                  * the system.
 135                  */
 136                 int val = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 137
 138                 if (!(val & S5P_CORE_LOCAL_PWR_EN))
 139                         return;
 140         }
 141         pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 142 }
 143
 144 /**
 145  * exynos_cpu_power_up : power up the specified cpu
 146  * @cpu : the cpu to power up
 147  *
 148  * Power up the specified cpu
 149  */
 150 void exynos_cpu_power_up(int cpu)
 151 {
 152         pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
 153                         EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 154 }
 155
 156 /**
 157  * exynos_cpu_power_state : returns the power state of the cpu
 158  * @cpu : the cpu to retrieve the power state from
 159  *
 160  */
 161 int exynos_cpu_power_state(int cpu)
 162 {
 163         return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
 164                         S5P_CORE_LOCAL_PWR_EN);
 165 }
 166
 167 /**
 168  * exynos_cluster_power_down : power down the specified cluster
 169  * @cluster : the cluster to power down
 170  */
 171 void exynos_cluster_power_down(int cluster)
 172 {
 173         pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
 174 }
 175
 176 /**
 177  * exynos_cluster_power_up : power up the specified cluster
 178  * @cluster : the cluster to power up
 179  */
 180 void exynos_cluster_power_up(int cluster)
 181 {
 182         pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
 183                         EXYNOS_COMMON_CONFIGURATION(cluster));
 184 }
 185
 186 /**
 187  * exynos_cluster_power_state : returns the power state of the cluster
 188  * @cluster : the cluster to retrieve the power state from
 189  *
 190  */
 191 int exynos_cluster_power_state(int cluster)
 192 {
 193         return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
 194                 S5P_CORE_LOCAL_PWR_EN);
 195 }
 196
 197 void __iomem *cpu_boot_reg_base(void)
 198 {
 199         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
 200                 return pmu_base_addr + S5P_INFORM5;
 201         return sysram_base_addr;
 202 }
 203
 204 static inline void __iomem *cpu_boot_reg(int cpu)
 205 {
 206         void __iomem *boot_reg;
 207
 208         boot_reg = cpu_boot_reg_base();
 209         if (!boot_reg)
 210                 return ERR_PTR(-ENODEV);
 211         if (soc_is_exynos4412())
 212                 boot_reg += 4*cpu;
 213         else if (soc_is_exynos5420() || soc_is_exynos5800())
 214                 boot_reg += 4;
 215         return boot_reg;
 216 }
 217
 218 /*
 219  * Set wake up by local power mode and execute software reset for given core.
 220  *
 221  * Currently this is needed only when booting secondary CPU on Exynos3250.
 222  */
 223 static void exynos_core_restart(u32 core_id)
 224 {
 225         u32 val;
 226
 227         if (!of_machine_is_compatible("samsung,exynos3250"))
 228                 return;
 229
 230         val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
 231         val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
 232         pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
 233
 234         pr_info("CPU%u: Software reset\n", core_id);
 235         pmu_raw_writel(EXYNOS_CORE_PO_RESET(core_id), EXYNOS_SWRESET);
 236 }
 237
 238 /*
 239  * Write pen_release in a way that is guaranteed to be visible to all
 240  * observers, irrespective of whether they're taking part in coherency
 241  * or not.  This is necessary for the hotplug code to work reliably.
 242  */
 243 static void write_pen_release(int val)
 244 {
 245         pen_release = val;
 246         smp_wmb();
 247         sync_cache_w(&pen_release);
 248 }
 249
 250 static void __iomem *scu_base_addr(void)
 251 {
 252         return (void __iomem *)(S5P_VA_SCU);
 253 }
 254
 255 static DEFINE_SPINLOCK(boot_lock);
 256
 257 static void exynos_secondary_init(unsigned int cpu)
 258 {
 259         /*
 260          * let the primary processor know we're out of the
 261          * pen, then head off into the C entry point
 262          */
 263         write_pen_release(-1);
 264
 265         /*
 266          * Synchronise with the boot thread.
 267          */
 268         spin_lock(&boot_lock);
 269         spin_unlock(&boot_lock);
 270 }
 271
 272 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 273 {
 274         unsigned long timeout;
 275         u32 mpidr = cpu_logical_map(cpu);
 276         u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 277         int ret = -ENOSYS;
 278
 279         /*
 280          * Set synchronisation state between this boot processor
 281          * and the secondary one
 282          */
 283         spin_lock(&boot_lock);
 284
 285         /*
 286          * The secondary processor is waiting to be released from
 287          * the holding pen - release it, then wait for it to flag
 288          * that it has been released by resetting pen_release.
 289          *
 290          * Note that "pen_release" is the hardware CPU core ID, whereas
 291          * "cpu" is Linux's internal ID.
 292          */
 293         write_pen_release(core_id);
 294
 295         if (!exynos_cpu_power_state(core_id)) {
 296                 exynos_cpu_power_up(core_id);
 297                 timeout = 10;
 298
 299                 /* wait max 10 ms until cpu1 is on */
 300                 while (exynos_cpu_power_state(core_id)
 301                        != S5P_CORE_LOCAL_PWR_EN) {
 302                         if (timeout-- == 0)
 303                                 break;
 304
 305                         mdelay(1);
 306                 }
 307
 308                 if (timeout == 0) {
 309                         printk(KERN_ERR "cpu1 power enable failed");
 310                         spin_unlock(&boot_lock);
 311                         return -ETIMEDOUT;
 312                 }
 313         }
 314
 315         exynos_core_restart(core_id);
 316
 317         /*
 318          * Send the secondary CPU a soft interrupt, thereby causing
 319          * the boot monitor to read the system wide flags register,
 320          * and branch to the address found there.
 321          */
 322
 323         timeout = jiffies + (1 * HZ);
 324         while (time_before(jiffies, timeout)) {
 325                 unsigned long boot_addr;
 326
 327                 smp_rmb();
 328
 329                 boot_addr = virt_to_phys(exynos4_secondary_startup);
 330
 331                 /*
 332                  * Try to set boot address using firmware first
 333                  * and fall back to boot register if it fails.
 334                  */
 335                 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
 336                 if (ret && ret != -ENOSYS)
 337                         goto fail;
 338                 if (ret == -ENOSYS) {
 339                         void __iomem *boot_reg = cpu_boot_reg(core_id);
 340
 341                         if (IS_ERR(boot_reg)) {
 342                                 ret = PTR_ERR(boot_reg);
 343                                 goto fail;
 344                         }
 345                         __raw_writel(boot_addr, boot_reg);
 346                 }
 347
 348                 call_firmware_op(cpu_boot, core_id);
 349
 350                 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 351
 352                 if (pen_release == -1)
 353                         break;
 354
 355                 udelay(10);
 356         }
 357
 358         /* No harm if this is called during first boot of secondary CPU */
 359         exynos_set_delayed_reset_assertion(core_id, false);
 360
 361         /*
 362          * now the secondary core is starting up let it run its
 363          * calibrations, then wait for it to finish
 364          */
 365 fail:
 366         spin_unlock(&boot_lock);
 367
 368         return pen_release != -1 ? ret : 0;
 369 }
 370
 371 /*
 372  * Initialise the CPU possible map early - this describes the CPUs
 373  * which may be present or become present in the system.
 374  */
 375
 376 static void __init exynos_smp_init_cpus(void)
 377 {
 378         void __iomem *scu_base = scu_base_addr();
 379         unsigned int i, ncores;
 380
 381         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 382                 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 383         else
 384                 /*
 385                  * CPU Nodes are passed thru DT and set_cpu_possible
 386                  * is set by "arm_dt_init_cpu_maps".
 387                  */
 388                 return;
 389
 390         /* sanity check */
 391         if (ncores > nr_cpu_ids) {
 392                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 393                         ncores, nr_cpu_ids);
 394                 ncores = nr_cpu_ids;
 395         }
 396
 397         for (i = 0; i < ncores; i++)
 398                 set_cpu_possible(i, true);
 399 }
 400
 401 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 402 {
 403         int i;
 404
 405         exynos_sysram_init();
 406
 407         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 408                 scu_enable(scu_base_addr());
 409
 410         /*
 411          * Write the address of secondary startup into the
 412          * system-wide flags register. The boot monitor waits
 413          * until it receives a soft interrupt, and then the
 414          * secondary CPU branches to this address.
 415          *
 416          * Try using firmware operation first and fall back to
 417          * boot register if it fails.
 418          */
 419         for (i = 1; i < max_cpus; ++i) {
 420                 unsigned long boot_addr;
 421                 u32 mpidr;
 422                 u32 core_id;
 423                 int ret;
 424
 425                 mpidr = cpu_logical_map(i);
 426                 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 427                 boot_addr = virt_to_phys(exynos4_secondary_startup);
 428
 429                 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
 430                 if (ret && ret != -ENOSYS)
 431                         break;
 432                 if (ret == -ENOSYS) {
 433                         void __iomem *boot_reg = cpu_boot_reg(core_id);
 434
 435                         if (IS_ERR(boot_reg))
 436                                 break;
 437                         __raw_writel(boot_addr, boot_reg);
 438                 }
 439         }
 440 }
 441
 442 #ifdef CONFIG_HOTPLUG_CPU
 443 /*
 444  * platform-specific code to shutdown a CPU
 445  *
 446  * Called with IRQs disabled
 447  */
 448 static void exynos_cpu_die(unsigned int cpu)
 449 {
 450         int spurious = 0;
 451         u32 mpidr = cpu_logical_map(cpu);
 452         u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 453
 454         v7_exit_coherency_flush(louis);
 455
 456         platform_do_lowpower(cpu, &spurious);
 457
 458         /*
 459          * bring this CPU back into the world of cache
 460          * coherency, and then restore interrupts
 461          */
 462         cpu_leave_lowpower(core_id);
 463
 464         if (spurious)
 465                 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 466 }
 467 #endif /* CONFIG_HOTPLUG_CPU */
 468
 469 struct smp_operations exynos_smp_ops __initdata = {
 470         .smp_init_cpus          = exynos_smp_init_cpus,
 471         .smp_prepare_cpus       = exynos_smp_prepare_cpus,
 472         .smp_secondary_init     = exynos_secondary_init,
 473         .smp_boot_secondary     = exynos_boot_secondary,
 474 #ifdef CONFIG_HOTPLUG_CPU
 475         .cpu_die                = exynos_cpu_die,
 476 #endif
 477 };