1 /* linux/arch/arm/mach-exynos4/platsmp.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
8 * Copyright (C) 2002 ARM Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
24 #include <asm/cacheflush.h>
25 #include <asm/smp_plat.h>
26 #include <asm/smp_scu.h>
28 #include <mach/hardware.h>
29 #include <mach/regs-clock.h>
30 #include <mach/regs-pmu.h>
36 extern void exynos4_secondary_startup(void);
38 static inline void __iomem
*cpu_boot_reg_base(void)
40 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1
)
45 static inline void __iomem
*cpu_boot_reg(int cpu
)
47 void __iomem
*boot_reg
;
49 boot_reg
= cpu_boot_reg_base();
50 if (soc_is_exynos4412())
56 * Write pen_release in a way that is guaranteed to be visible to all
57 * observers, irrespective of whether they're taking part in coherency
58 * or not. This is necessary for the hotplug code to work reliably.
60 static void write_pen_release(int val
)
64 __cpuc_flush_dcache_area((void *)&pen_release
, sizeof(pen_release
));
65 outer_clean_range(__pa(&pen_release
), __pa(&pen_release
+ 1));
68 static void __iomem
*scu_base_addr(void)
70 return (void __iomem
*)(S5P_VA_SCU
);
73 static DEFINE_SPINLOCK(boot_lock
);
75 static void __cpuinit
exynos_secondary_init(unsigned int cpu
)
78 * let the primary processor know we're out of the
79 * pen, then head off into the C entry point
81 write_pen_release(-1);
84 * Synchronise with the boot thread.
86 spin_lock(&boot_lock
);
87 spin_unlock(&boot_lock
);
90 static int __cpuinit
exynos_boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
92 unsigned long timeout
;
93 unsigned long phys_cpu
= cpu_logical_map(cpu
);
96 * Set synchronisation state between this boot processor
97 * and the secondary one
99 spin_lock(&boot_lock
);
102 * The secondary processor is waiting to be released from
103 * the holding pen - release it, then wait for it to flag
104 * that it has been released by resetting pen_release.
106 * Note that "pen_release" is the hardware CPU ID, whereas
107 * "cpu" is Linux's internal ID.
109 write_pen_release(phys_cpu
);
111 if (!(__raw_readl(S5P_ARM_CORE1_STATUS
) & S5P_CORE_LOCAL_PWR_EN
)) {
112 __raw_writel(S5P_CORE_LOCAL_PWR_EN
,
113 S5P_ARM_CORE1_CONFIGURATION
);
117 /* wait max 10 ms until cpu1 is on */
118 while ((__raw_readl(S5P_ARM_CORE1_STATUS
)
119 & S5P_CORE_LOCAL_PWR_EN
) != S5P_CORE_LOCAL_PWR_EN
) {
127 printk(KERN_ERR
"cpu1 power enable failed");
128 spin_unlock(&boot_lock
);
133 * Send the secondary CPU a soft interrupt, thereby causing
134 * the boot monitor to read the system wide flags register,
135 * and branch to the address found there.
138 timeout
= jiffies
+ (1 * HZ
);
139 while (time_before(jiffies
, timeout
)) {
142 __raw_writel(virt_to_phys(exynos4_secondary_startup
),
143 cpu_boot_reg(phys_cpu
));
144 arch_send_wakeup_ipi_mask(cpumask_of(cpu
));
146 if (pen_release
== -1)
153 * now the secondary core is starting up let it run its
154 * calibrations, then wait for it to finish
156 spin_unlock(&boot_lock
);
158 return pen_release
!= -1 ? -ENOSYS
: 0;
162 * Initialise the CPU possible map early - this describes the CPUs
163 * which may be present or become present in the system.
166 static void __init
exynos_smp_init_cpus(void)
168 void __iomem
*scu_base
= scu_base_addr();
169 unsigned int i
, ncores
;
171 if (soc_is_exynos5250())
174 ncores
= scu_base
? scu_get_core_count(scu_base
) : 1;
177 if (ncores
> nr_cpu_ids
) {
178 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
183 for (i
= 0; i
< ncores
; i
++)
184 set_cpu_possible(i
, true);
187 static void __init
exynos_smp_prepare_cpus(unsigned int max_cpus
)
191 if (!(soc_is_exynos5250() || soc_is_exynos5440()))
192 scu_enable(scu_base_addr());
195 * Write the address of secondary startup into the
196 * system-wide flags register. The boot monitor waits
197 * until it receives a soft interrupt, and then the
198 * secondary CPU branches to this address.
200 for (i
= 1; i
< max_cpus
; ++i
)
201 __raw_writel(virt_to_phys(exynos4_secondary_startup
),
202 cpu_boot_reg(cpu_logical_map(i
)));
205 struct smp_operations exynos_smp_ops __initdata
= {
206 .smp_init_cpus
= exynos_smp_init_cpus
,
207 .smp_prepare_cpus
= exynos_smp_prepare_cpus
,
208 .smp_secondary_init
= exynos_secondary_init
,
209 .smp_boot_secondary
= exynos_boot_secondary
,
210 #ifdef CONFIG_HOTPLUG_CPU
211 .cpu_die
= exynos_cpu_die
,