arch/arm/mach-exynos/platsmp.c

   1  /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
   6  *
   7  *  Copyright (C) 2002 ARM Ltd.
   8  *  All Rights Reserved
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/init.h>
  16 #include <linux/errno.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/jiffies.h>
  20 #include <linux/smp.h>
  21 #include <linux/io.h>
  22 #include <linux/of_address.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/cp15.h>
  26 #include <asm/smp_plat.h>
  27 #include <asm/smp_scu.h>
  28 #include <asm/firmware.h>
  29
  30 #include <mach/map.h>
  31
  32 #include "common.h"
  33 #include "regs-pmu.h"
  34
  35 extern void exynos4_secondary_startup(void);
  36
  37 #ifdef CONFIG_HOTPLUG_CPU
  38 static inline void cpu_leave_lowpower(u32 core_id)
  39 {
  40         unsigned int v;
  41
  42         asm volatile(
  43         "mrc    p15, 0, %0, c1, c0, 0\n"
  44         "       orr     %0, %0, %1\n"
  45         "       mcr     p15, 0, %0, c1, c0, 0\n"
  46         "       mrc     p15, 0, %0, c1, c0, 1\n"
  47         "       orr     %0, %0, %2\n"
  48         "       mcr     p15, 0, %0, c1, c0, 1\n"
  49           : "=&r" (v)
  50           : "Ir" (CR_C), "Ir" (0x40)
  51           : "cc");
  52 }
  53
  54 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
  55 {
  56         u32 mpidr = cpu_logical_map(cpu);
  57         u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
  58
  59         for (;;) {
  60
  61                 /* Turn the CPU off on next WFI instruction. */
  62                 exynos_cpu_power_down(core_id);
  63
  64                 wfi();
  65
  66                 if (pen_release == core_id) {
  67                         /*
  68                          * OK, proper wakeup, we're done
  69                          */
  70                         break;
  71                 }
  72
  73                 /*
  74                  * Getting here, means that we have come out of WFI without
  75                  * having been woken up - this shouldn't happen
  76                  *
  77                  * Just note it happening - when we're woken, we can report
  78                  * its occurrence.
  79                  */
  80                 (*spurious)++;
  81         }
  82 }
  83 #endif /* CONFIG_HOTPLUG_CPU */
  84
  85 /**
  86  * exynos_core_power_down : power down the specified cpu
  87  * @cpu : the cpu to power down
  88  *
  89  * Power down the specified cpu. The sequence must be finished by a
  90  * call to cpu_do_idle()
  91  *
  92  */
  93 void exynos_cpu_power_down(int cpu)
  94 {
  95         u32 core_conf;
  96
  97         if (cpu == 0 && (soc_is_exynos5420() || soc_is_exynos5800())) {
  98                 /*
  99                  * Bypass power down for CPU0 during suspend. Check for
 100                  * the SYS_PWR_REG value to decide if we are suspending
 101                  * the system.
 102                  */
 103                 int val = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 104
 105                 if (!(val & S5P_CORE_LOCAL_PWR_EN))
 106                         return;
 107         }
 108
 109         core_conf = pmu_raw_readl(EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 110         core_conf &= ~S5P_CORE_LOCAL_PWR_EN;
 111         pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 112 }
 113
 114 /**
 115  * exynos_cpu_power_up : power up the specified cpu
 116  * @cpu : the cpu to power up
 117  *
 118  * Power up the specified cpu
 119  */
 120 void exynos_cpu_power_up(int cpu)
 121 {
 122         u32 core_conf = S5P_CORE_LOCAL_PWR_EN;
 123
 124         if (soc_is_exynos3250())
 125                 core_conf |= S5P_CORE_AUTOWAKEUP_EN;
 126
 127         pmu_raw_writel(core_conf,
 128                         EXYNOS_ARM_CORE_CONFIGURATION(cpu));
 129 }
 130
 131 /**
 132  * exynos_cpu_power_state : returns the power state of the cpu
 133  * @cpu : the cpu to retrieve the power state from
 134  *
 135  */
 136 int exynos_cpu_power_state(int cpu)
 137 {
 138         return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
 139                         S5P_CORE_LOCAL_PWR_EN);
 140 }
 141
 142 /**
 143  * exynos_cluster_power_down : power down the specified cluster
 144  * @cluster : the cluster to power down
 145  */
 146 void exynos_cluster_power_down(int cluster)
 147 {
 148         pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
 149 }
 150
 151 /**
 152  * exynos_cluster_power_up : power up the specified cluster
 153  * @cluster : the cluster to power up
 154  */
 155 void exynos_cluster_power_up(int cluster)
 156 {
 157         pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
 158                         EXYNOS_COMMON_CONFIGURATION(cluster));
 159 }
 160
 161 /**
 162  * exynos_cluster_power_state : returns the power state of the cluster
 163  * @cluster : the cluster to retrieve the power state from
 164  *
 165  */
 166 int exynos_cluster_power_state(int cluster)
 167 {
 168         return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
 169                 S5P_CORE_LOCAL_PWR_EN);
 170 }
 171
 172 void __iomem *cpu_boot_reg_base(void)
 173 {
 174         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
 175                 return pmu_base_addr + S5P_INFORM5;
 176         return sysram_base_addr;
 177 }
 178
 179 static inline void __iomem *cpu_boot_reg(int cpu)
 180 {
 181         void __iomem *boot_reg;
 182
 183         boot_reg = cpu_boot_reg_base();
 184         if (!boot_reg)
 185                 return ERR_PTR(-ENODEV);
 186         if (soc_is_exynos4412())
 187                 boot_reg += 4*cpu;
 188         else if (soc_is_exynos5420() || soc_is_exynos5800())
 189                 boot_reg += 4;
 190         return boot_reg;
 191 }
 192
 193 /*
 194  * Set wake up by local power mode and execute software reset for given core.
 195  *
 196  * Currently this is needed only when booting secondary CPU on Exynos3250.
 197  */
 198 static void exynos_core_restart(u32 core_id)
 199 {
 200         u32 val;
 201
 202         if (!of_machine_is_compatible("samsung,exynos3250"))
 203                 return;
 204
 205         while (!pmu_raw_readl(S5P_PMU_SPARE2))
 206                 udelay(10);
 207         udelay(10);
 208
 209         val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
 210         val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
 211         pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
 212
 213         pr_info("CPU%u: Software reset\n", core_id);
 214         pmu_raw_writel(EXYNOS_CORE_PO_RESET(core_id), EXYNOS_SWRESET);
 215 }
 216
 217 /*
 218  * Write pen_release in a way that is guaranteed to be visible to all
 219  * observers, irrespective of whether they're taking part in coherency
 220  * or not.  This is necessary for the hotplug code to work reliably.
 221  */
 222 static void write_pen_release(int val)
 223 {
 224         pen_release = val;
 225         smp_wmb();
 226         sync_cache_w(&pen_release);
 227 }
 228
 229 static void __iomem *scu_base_addr(void)
 230 {
 231         return (void __iomem *)(S5P_VA_SCU);
 232 }
 233
 234 static DEFINE_SPINLOCK(boot_lock);
 235
 236 static void exynos_secondary_init(unsigned int cpu)
 237 {
 238         /*
 239          * let the primary processor know we're out of the
 240          * pen, then head off into the C entry point
 241          */
 242         write_pen_release(-1);
 243
 244         /*
 245          * Synchronise with the boot thread.
 246          */
 247         spin_lock(&boot_lock);
 248         spin_unlock(&boot_lock);
 249 }
 250
 251 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 252 {
 253         unsigned long timeout;
 254         u32 mpidr = cpu_logical_map(cpu);
 255         u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 256         int ret = -ENOSYS;
 257
 258         /*
 259          * Set synchronisation state between this boot processor
 260          * and the secondary one
 261          */
 262         spin_lock(&boot_lock);
 263
 264         /*
 265          * The secondary processor is waiting to be released from
 266          * the holding pen - release it, then wait for it to flag
 267          * that it has been released by resetting pen_release.
 268          *
 269          * Note that "pen_release" is the hardware CPU core ID, whereas
 270          * "cpu" is Linux's internal ID.
 271          */
 272         write_pen_release(core_id);
 273
 274         if (!exynos_cpu_power_state(core_id)) {
 275                 exynos_cpu_power_up(core_id);
 276                 timeout = 10;
 277
 278                 /* wait max 10 ms until cpu1 is on */
 279                 while (exynos_cpu_power_state(core_id)
 280                        != S5P_CORE_LOCAL_PWR_EN) {
 281                         if (timeout-- == 0)
 282                                 break;
 283
 284                         mdelay(1);
 285                 }
 286
 287                 if (timeout == 0) {
 288                         printk(KERN_ERR "cpu1 power enable failed");
 289                         spin_unlock(&boot_lock);
 290                         return -ETIMEDOUT;
 291                 }
 292         }
 293
 294         exynos_core_restart(core_id);
 295
 296         /*
 297          * Send the secondary CPU a soft interrupt, thereby causing
 298          * the boot monitor to read the system wide flags register,
 299          * and branch to the address found there.
 300          */
 301
 302         timeout = jiffies + (1 * HZ);
 303         while (time_before(jiffies, timeout)) {
 304                 unsigned long boot_addr;
 305
 306                 smp_rmb();
 307
 308                 boot_addr = virt_to_phys(exynos4_secondary_startup);
 309
 310                 /*
 311                  * Try to set boot address using firmware first
 312                  * and fall back to boot register if it fails.
 313                  */
 314                 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
 315                 if (ret && ret != -ENOSYS)
 316                         goto fail;
 317                 if (ret == -ENOSYS) {
 318                         void __iomem *boot_reg = cpu_boot_reg(core_id);
 319
 320                         if (IS_ERR(boot_reg)) {
 321                                 ret = PTR_ERR(boot_reg);
 322                                 goto fail;
 323                         }
 324                         __raw_writel(boot_addr, boot_reg);
 325                 }
 326
 327                 call_firmware_op(cpu_boot, core_id);
 328
 329                 if (soc_is_exynos3250())
 330                         dsb_sev();
 331                 else
 332                         arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 333
 334                 if (pen_release == -1)
 335                         break;
 336
 337                 udelay(10);
 338         }
 339
 340         /*
 341          * now the secondary core is starting up let it run its
 342          * calibrations, then wait for it to finish
 343          */
 344 fail:
 345         spin_unlock(&boot_lock);
 346
 347         return pen_release != -1 ? ret : 0;
 348 }
 349
 350 /*
 351  * Initialise the CPU possible map early - this describes the CPUs
 352  * which may be present or become present in the system.
 353  */
 354
 355 static void __init exynos_smp_init_cpus(void)
 356 {
 357         void __iomem *scu_base = scu_base_addr();
 358         unsigned int i, ncores;
 359
 360         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 361                 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 362         else
 363                 /*
 364                  * CPU Nodes are passed thru DT and set_cpu_possible
 365                  * is set by "arm_dt_init_cpu_maps".
 366                  */
 367                 return;
 368
 369         /* sanity check */
 370         if (ncores > nr_cpu_ids) {
 371                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 372                         ncores, nr_cpu_ids);
 373                 ncores = nr_cpu_ids;
 374         }
 375
 376         for (i = 0; i < ncores; i++)
 377                 set_cpu_possible(i, true);
 378 }
 379
 380 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 381 {
 382         int i;
 383
 384         exynos_sysram_init();
 385
 386         exynos_set_delayed_reset_assertion(true);
 387
 388         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 389                 scu_enable(scu_base_addr());
 390
 391         /*
 392          * Write the address of secondary startup into the
 393          * system-wide flags register. The boot monitor waits
 394          * until it receives a soft interrupt, and then the
 395          * secondary CPU branches to this address.
 396          *
 397          * Try using firmware operation first and fall back to
 398          * boot register if it fails.
 399          */
 400         for (i = 1; i < max_cpus; ++i) {
 401                 unsigned long boot_addr;
 402                 u32 mpidr;
 403                 u32 core_id;
 404                 int ret;
 405
 406                 mpidr = cpu_logical_map(i);
 407                 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 408                 boot_addr = virt_to_phys(exynos4_secondary_startup);
 409
 410                 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
 411                 if (ret && ret != -ENOSYS)
 412                         break;
 413                 if (ret == -ENOSYS) {
 414                         void __iomem *boot_reg = cpu_boot_reg(core_id);
 415
 416                         if (IS_ERR(boot_reg))
 417                                 break;
 418                         __raw_writel(boot_addr, boot_reg);
 419                 }
 420         }
 421 }
 422
 423 #ifdef CONFIG_HOTPLUG_CPU
 424 /*
 425  * platform-specific code to shutdown a CPU
 426  *
 427  * Called with IRQs disabled
 428  */
 429 static void exynos_cpu_die(unsigned int cpu)
 430 {
 431         int spurious = 0;
 432         u32 mpidr = cpu_logical_map(cpu);
 433         u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 434
 435         v7_exit_coherency_flush(louis);
 436
 437         platform_do_lowpower(cpu, &spurious);
 438
 439         /*
 440          * bring this CPU back into the world of cache
 441          * coherency, and then restore interrupts
 442          */
 443         cpu_leave_lowpower(core_id);
 444
 445         if (spurious)
 446                 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 447 }
 448 #endif /* CONFIG_HOTPLUG_CPU */
 449
 450 struct smp_operations exynos_smp_ops __initdata = {
 451         .smp_init_cpus          = exynos_smp_init_cpus,
 452         .smp_prepare_cpus       = exynos_smp_prepare_cpus,
 453         .smp_secondary_init     = exynos_secondary_init,
 454         .smp_boot_secondary     = exynos_boot_secondary,
 455 #ifdef CONFIG_HOTPLUG_CPU
 456         .cpu_die                = exynos_cpu_die,
 457 #endif
 458 };