1 /* linux/arch/arm/mach-exynos4/platsmp.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
8 * Copyright (C) 2002 ARM Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
23 #include <linux/of_address.h>
25 #include <asm/cacheflush.h>
26 #include <asm/smp_plat.h>
27 #include <asm/smp_scu.h>
28 #include <asm/firmware.h>
33 extern void exynos4_secondary_startup(void);
35 static inline void __iomem
*cpu_boot_reg_base(void)
37 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1
)
39 return sysram_base_addr
;
42 static inline void __iomem
*cpu_boot_reg(int cpu
)
44 void __iomem
*boot_reg
;
46 boot_reg
= cpu_boot_reg_base();
48 return ERR_PTR(-ENODEV
);
49 if (soc_is_exynos4412())
51 else if (soc_is_exynos5420() || soc_is_exynos5800())
57 * Write pen_release in a way that is guaranteed to be visible to all
58 * observers, irrespective of whether they're taking part in coherency
59 * or not. This is necessary for the hotplug code to work reliably.
61 static void write_pen_release(int val
)
65 sync_cache_w(&pen_release
);
68 static void __iomem
*scu_base_addr(void)
70 return (void __iomem
*)(S5P_VA_SCU
);
73 static DEFINE_SPINLOCK(boot_lock
);
75 static void exynos_secondary_init(unsigned int cpu
)
78 * let the primary processor know we're out of the
79 * pen, then head off into the C entry point
81 write_pen_release(-1);
84 * Synchronise with the boot thread.
86 spin_lock(&boot_lock
);
87 spin_unlock(&boot_lock
);
90 static int exynos_boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
92 unsigned long timeout
;
93 unsigned long phys_cpu
= cpu_logical_map(cpu
);
97 * Set synchronisation state between this boot processor
98 * and the secondary one
100 spin_lock(&boot_lock
);
103 * The secondary processor is waiting to be released from
104 * the holding pen - release it, then wait for it to flag
105 * that it has been released by resetting pen_release.
107 * Note that "pen_release" is the hardware CPU ID, whereas
108 * "cpu" is Linux's internal ID.
110 write_pen_release(phys_cpu
);
112 if (!exynos_cpu_power_state(cpu
)) {
113 exynos_cpu_power_up(cpu
);
116 /* wait max 10 ms until cpu1 is on */
117 while (exynos_cpu_power_state(cpu
) != S5P_CORE_LOCAL_PWR_EN
) {
125 printk(KERN_ERR
"cpu1 power enable failed");
126 spin_unlock(&boot_lock
);
131 * Send the secondary CPU a soft interrupt, thereby causing
132 * the boot monitor to read the system wide flags register,
133 * and branch to the address found there.
136 timeout
= jiffies
+ (1 * HZ
);
137 while (time_before(jiffies
, timeout
)) {
138 unsigned long boot_addr
;
142 boot_addr
= virt_to_phys(exynos4_secondary_startup
);
145 * Try to set boot address using firmware first
146 * and fall back to boot register if it fails.
148 ret
= call_firmware_op(set_cpu_boot_addr
, phys_cpu
, boot_addr
);
149 if (ret
&& ret
!= -ENOSYS
)
151 if (ret
== -ENOSYS
) {
152 void __iomem
*boot_reg
= cpu_boot_reg(phys_cpu
);
154 if (IS_ERR(boot_reg
)) {
155 ret
= PTR_ERR(boot_reg
);
158 __raw_writel(boot_addr
, cpu_boot_reg(phys_cpu
));
161 call_firmware_op(cpu_boot
, phys_cpu
);
163 arch_send_wakeup_ipi_mask(cpumask_of(cpu
));
165 if (pen_release
== -1)
172 * now the secondary core is starting up let it run its
173 * calibrations, then wait for it to finish
176 spin_unlock(&boot_lock
);
178 return pen_release
!= -1 ? ret
: 0;
182 * Initialise the CPU possible map early - this describes the CPUs
183 * which may be present or become present in the system.
186 static void __init
exynos_smp_init_cpus(void)
188 void __iomem
*scu_base
= scu_base_addr();
189 unsigned int i
, ncores
;
191 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9
)
192 ncores
= scu_base
? scu_get_core_count(scu_base
) : 1;
195 * CPU Nodes are passed thru DT and set_cpu_possible
196 * is set by "arm_dt_init_cpu_maps".
201 if (ncores
> nr_cpu_ids
) {
202 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
207 for (i
= 0; i
< ncores
; i
++)
208 set_cpu_possible(i
, true);
211 static void __init
exynos_smp_prepare_cpus(unsigned int max_cpus
)
215 exynos_sysram_init();
217 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9
)
218 scu_enable(scu_base_addr());
221 * Write the address of secondary startup into the
222 * system-wide flags register. The boot monitor waits
223 * until it receives a soft interrupt, and then the
224 * secondary CPU branches to this address.
226 * Try using firmware operation first and fall back to
227 * boot register if it fails.
229 for (i
= 1; i
< max_cpus
; ++i
) {
230 unsigned long phys_cpu
;
231 unsigned long boot_addr
;
234 phys_cpu
= cpu_logical_map(i
);
235 boot_addr
= virt_to_phys(exynos4_secondary_startup
);
237 ret
= call_firmware_op(set_cpu_boot_addr
, phys_cpu
, boot_addr
);
238 if (ret
&& ret
!= -ENOSYS
)
240 if (ret
== -ENOSYS
) {
241 void __iomem
*boot_reg
= cpu_boot_reg(phys_cpu
);
243 if (IS_ERR(boot_reg
))
245 __raw_writel(boot_addr
, cpu_boot_reg(phys_cpu
));
250 struct smp_operations exynos_smp_ops __initdata
= {
251 .smp_init_cpus
= exynos_smp_init_cpus
,
252 .smp_prepare_cpus
= exynos_smp_prepare_cpus
,
253 .smp_secondary_init
= exynos_secondary_init
,
254 .smp_boot_secondary
= exynos_boot_secondary
,
255 #ifdef CONFIG_HOTPLUG_CPU
256 .cpu_die
= exynos_cpu_die
,